From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E7BCC33CAF for ; Wed, 22 Jan 2020 08:13:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1679324655 for ; Wed, 22 Jan 2020 08:13:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="YyTGJm0C" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729012AbgAVINe (ORCPT ); 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Wed, 22 Jan 2020 02:12:58 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Wed, 22 Jan 2020 02:12:58 -0600 Received: from [10.24.69.159] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 00M8Co0Y069651; Wed, 22 Jan 2020 02:12:51 -0600 Subject: Re: [v3 4/6] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller To: "Lad, Prabhakar" , Rob Herring , Bjorn Helgaas , Mark Rutland , Geert Uytterhoeven , Magnus Damm , Marek Vasut , Yoshihiro Shimoda , linux-pci CC: Catalin Marinas , Will Deacon , Lorenzo Pieralisi , Arnd Bergmann , Greg Kroah-Hartman , Andrew Murray , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , LAK , Linux-Renesas , Chris Paterson , Frank Rowand , Gustavo Pimentel , Jingoo Han , Simon Horman , Shawn Lin , Tom Joseph , Heiko Stuebner , "open list:ARM/Rockchip SoC..." , Lad Prabhakar References: <20200108162211.22358-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20200108162211.22358-5-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Kishon Vijay Abraham I Message-ID: <9c65eb7a-539b-1fa3-f988-40c32aa8dfe3@ti.com> Date: Wed, 22 Jan 2020 13:45:53 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Prabhakar, On 21/01/20 11:27 PM, Lad, Prabhakar wrote: > Hi Rob/Kishon, > > On Wed, Jan 8, 2020 at 4:22 PM Lad Prabhakar wrote: >> >> This patch adds the bindings for the R-Car PCIe endpoint driver. >> >> Signed-off-by: Lad Prabhakar >> --- >> .../devicetree/bindings/pci/rcar-pci-ep.yaml | 76 +++++++++++++++++++ >> 1 file changed, 76 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml >> >> diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml >> new file mode 100644 >> index 000000000000..99c2a1174463 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml >> @@ -0,0 +1,76 @@ >> +# SPDX-License-Identifier: GPL-2.0 >> +# Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/ >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/rcar-pcie-ep.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Renesas R-Car PCIe Endpoint >> + >> +maintainers: >> + - Lad Prabhakar >> + >> +properties: >> + compatible: >> + items: >> + - const: renesas,r8a774c0-pcie-ep >> + - const: renesas,rcar-gen3-pcie-ep >> + >> + reg: >> + maxItems: 5 >> + >> + reg-names: >> + items: >> + - const: apb-base >> + - const: memory0 >> + - const: memory1 >> + - const: memory2 >> + - const: memory3 As I had mentioned in the other patch, I'd prefer if we can create standard binding for representing the memory regions. IMHO we should create subnode for memory regions Each sub-node itself may or may not have more than one memory region. In your platform, since there can be only one allocation in a memory region, there should be 4 sub-nodes for each of the memory region and each node should have page_size (or some equivalent property) property to indicate page_size (= region_size). For a platform that doesn't have the restriction, there can be a single sub-node containing all the memory region. Let's wait for Rob's comment though. Thanks Kishon >> + >> + power-domains: >> + maxItems: 1 >> + >> + resets: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: pcie >> + >> + max-functions: >> + minimum: 1 >> + maximum: 6 >> + >> +required: >> + - compatible >> + - reg >> + - reg-names >> + - resets >> + - power-domains >> + - clocks >> + - clock-names >> + - max-functions >> + > apart from dt_binding_check error are we OK with dt bindings ? > > Cheers, > --Prabhakar > >> +examples: >> + - | >> + #include >> + #include >> + >> + pcie0_ep: pcie-ep@fe000000 { >> + compatible = "renesas,r8a774c0-pcie-ep", >> + "renesas,rcar-gen3-pcie-ep"; >> + reg = <0 0xfe000000 0 0x80000>, >> + <0x0 0xfe100000 0 0x100000>, >> + <0x0 0xfe200000 0 0x200000>, >> + <0x0 0x30000000 0 0x8000000>, >> + <0x0 0x38000000 0 0x8000000>; >> + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; >> + resets = <&cpg 319>; >> + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; >> + clocks = <&cpg CPG_MOD 319>; >> + clock-names = "pcie"; >> + max-functions = /bits/ 8 <1>; >> + }; >> -- >> 2.20.1 >> From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kishon Vijay Abraham I Subject: Re: [v3 4/6] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller Date: Wed, 22 Jan 2020 13:45:53 +0530 Message-ID: <9c65eb7a-539b-1fa3-f988-40c32aa8dfe3@ti.com> References: <20200108162211.22358-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20200108162211.22358-5-prabhakar.mahadev-lad.rj@bp.renesas.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane-mx.org@lists.infradead.org To: "Lad, Prabhakar" , Rob Herring , Bjorn Helgaas , Mark Rutland , Geert Uytterhoeven , Magnus Damm , Marek Vasut , Yoshihiro Shimoda , linux-pci Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Chris Paterson , Lorenzo Pieralisi , Heiko Stuebner , Arnd Bergmann , Jingoo Han , Catalin Marinas , Shawn Lin , Frank Rowand , LKML , Lad Prabhakar , Linux-Renesas , "open list:ARM/Rockchip SoC..." , Tom Joseph , Simon Horman , Greg Kroah-Hartman , Andrew Murray , Gustavo Pimentel , Will Deacon , LAK List-Id: linux-rockchip.vger.kernel.org Hi Prabhakar, On 21/01/20 11:27 PM, Lad, Prabhakar wrote: > Hi Rob/Kishon, > > On Wed, Jan 8, 2020 at 4:22 PM Lad Prabhakar wrote: >> >> This patch adds the bindings for the R-Car PCIe endpoint driver. >> >> Signed-off-by: Lad Prabhakar >> --- >> .../devicetree/bindings/pci/rcar-pci-ep.yaml | 76 +++++++++++++++++++ >> 1 file changed, 76 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml >> >> diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml >> new file mode 100644 >> index 000000000000..99c2a1174463 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml >> @@ -0,0 +1,76 @@ >> +# SPDX-License-Identifier: GPL-2.0 >> +# Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/ >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/rcar-pcie-ep.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Renesas R-Car PCIe Endpoint >> + >> +maintainers: >> + - Lad Prabhakar >> + >> +properties: >> + compatible: >> + items: >> + - const: renesas,r8a774c0-pcie-ep >> + - const: renesas,rcar-gen3-pcie-ep >> + >> + reg: >> + maxItems: 5 >> + >> + reg-names: >> + items: >> + - const: apb-base >> + - const: memory0 >> + - const: memory1 >> + - const: memory2 >> + - const: memory3 As I had mentioned in the other patch, I'd prefer if we can create standard binding for representing the memory regions. IMHO we should create subnode for memory regions Each sub-node itself may or may not have more than one memory region. In your platform, since there can be only one allocation in a memory region, there should be 4 sub-nodes for each of the memory region and each node should have page_size (or some equivalent property) property to indicate page_size (= region_size). For a platform that doesn't have the restriction, there can be a single sub-node containing all the memory region. Let's wait for Rob's comment though. Thanks Kishon >> + >> + power-domains: >> + maxItems: 1 >> + >> + resets: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: pcie >> + >> + max-functions: >> + minimum: 1 >> + maximum: 6 >> + >> +required: >> + - compatible >> + - reg >> + - reg-names >> + - resets >> + - power-domains >> + - clocks >> + - clock-names >> + - max-functions >> + > apart from dt_binding_check error are we OK with dt bindings ? > > Cheers, > --Prabhakar > >> +examples: >> + - | >> + #include >> + #include >> + >> + pcie0_ep: pcie-ep@fe000000 { >> + compatible = "renesas,r8a774c0-pcie-ep", >> + "renesas,rcar-gen3-pcie-ep"; >> + reg = <0 0xfe000000 0 0x80000>, >> + <0x0 0xfe100000 0 0x100000>, >> + <0x0 0xfe200000 0 0x200000>, >> + <0x0 0x30000000 0 0x8000000>, >> + <0x0 0x38000000 0 0x8000000>; >> + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; >> + resets = <&cpg 319>; >> + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; >> + clocks = <&cpg CPG_MOD 319>; >> + clock-names = "pcie"; >> + max-functions = /bits/ 8 <1>; >> + }; >> -- >> 2.20.1 >> From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 876ABC2D0DB for ; Wed, 22 Jan 2020 08:13:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4D9E72253D for ; Wed, 22 Jan 2020 08:13:20 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Wed, 22 Jan 2020 02:12:51 -0600 Subject: Re: [v3 4/6] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller To: "Lad, Prabhakar" , Rob Herring , Bjorn Helgaas , Mark Rutland , Geert Uytterhoeven , Magnus Damm , Marek Vasut , Yoshihiro Shimoda , linux-pci References: <20200108162211.22358-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20200108162211.22358-5-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Kishon Vijay Abraham I Message-ID: <9c65eb7a-539b-1fa3-f988-40c32aa8dfe3@ti.com> Date: Wed, 22 Jan 2020 13:45:53 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200122_001316_964165_A0F402A3 X-CRM114-Status: GOOD ( 26.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Chris Paterson , Lorenzo Pieralisi , Heiko Stuebner , Arnd Bergmann , Jingoo Han , Catalin Marinas , Shawn Lin , Frank Rowand , LKML , Lad Prabhakar , Linux-Renesas , "open list:ARM/Rockchip SoC..." , Tom Joseph , Simon Horman , Greg Kroah-Hartman , Andrew Murray , Gustavo Pimentel , Will Deacon , LAK Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Prabhakar, On 21/01/20 11:27 PM, Lad, Prabhakar wrote: > Hi Rob/Kishon, > > On Wed, Jan 8, 2020 at 4:22 PM Lad Prabhakar wrote: >> >> This patch adds the bindings for the R-Car PCIe endpoint driver. >> >> Signed-off-by: Lad Prabhakar >> --- >> .../devicetree/bindings/pci/rcar-pci-ep.yaml | 76 +++++++++++++++++++ >> 1 file changed, 76 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml >> >> diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml >> new file mode 100644 >> index 000000000000..99c2a1174463 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml >> @@ -0,0 +1,76 @@ >> +# SPDX-License-Identifier: GPL-2.0 >> +# Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/ >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/rcar-pcie-ep.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Renesas R-Car PCIe Endpoint >> + >> +maintainers: >> + - Lad Prabhakar >> + >> +properties: >> + compatible: >> + items: >> + - const: renesas,r8a774c0-pcie-ep >> + - const: renesas,rcar-gen3-pcie-ep >> + >> + reg: >> + maxItems: 5 >> + >> + reg-names: >> + items: >> + - const: apb-base >> + - const: memory0 >> + - const: memory1 >> + - const: memory2 >> + - const: memory3 As I had mentioned in the other patch, I'd prefer if we can create standard binding for representing the memory regions. IMHO we should create subnode for memory regions Each sub-node itself may or may not have more than one memory region. In your platform, since there can be only one allocation in a memory region, there should be 4 sub-nodes for each of the memory region and each node should have page_size (or some equivalent property) property to indicate page_size (= region_size). For a platform that doesn't have the restriction, there can be a single sub-node containing all the memory region. Let's wait for Rob's comment though. Thanks Kishon >> + >> + power-domains: >> + maxItems: 1 >> + >> + resets: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: pcie >> + >> + max-functions: >> + minimum: 1 >> + maximum: 6 >> + >> +required: >> + - compatible >> + - reg >> + - reg-names >> + - resets >> + - power-domains >> + - clocks >> + - clock-names >> + - max-functions >> + > apart from dt_binding_check error are we OK with dt bindings ? > > Cheers, > --Prabhakar > >> +examples: >> + - | >> + #include >> + #include >> + >> + pcie0_ep: pcie-ep@fe000000 { >> + compatible = "renesas,r8a774c0-pcie-ep", >> + "renesas,rcar-gen3-pcie-ep"; >> + reg = <0 0xfe000000 0 0x80000>, >> + <0x0 0xfe100000 0 0x100000>, >> + <0x0 0xfe200000 0 0x200000>, >> + <0x0 0x30000000 0 0x8000000>, >> + <0x0 0x38000000 0 0x8000000>; >> + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; >> + resets = <&cpg 319>; >> + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; >> + clocks = <&cpg CPG_MOD 319>; >> + clock-names = "pcie"; >> + max-functions = /bits/ 8 <1>; >> + }; >> -- >> 2.20.1 >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel