* [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation
@ 2021-09-09 23:07 José Roberto de Souza
2021-09-09 23:07 ` [Intel-gfx] [PATCH 2/5] drm/i915/display/adlp: Add new PSR2 workarounds José Roberto de Souza
` (7 more replies)
0 siblings, 8 replies; 19+ messages in thread
From: José Roberto de Souza @ 2021-09-09 23:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Gwan-gyeong Mun, José Roberto de Souza
As the SU_REGION_START begins at 0, the SU_REGION_END should be number
of lines - 1.
BSpec: 50424
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3f6fb7d67f84d..36816abb3bcc0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1501,7 +1501,7 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
if (IS_ALDERLAKE_P(dev_priv)) {
val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
- val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
+ val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1);
} else {
drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
--
2.33.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 2/5] drm/i915/display/adlp: Add new PSR2 workarounds
2021-09-09 23:07 [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation José Roberto de Souza
@ 2021-09-09 23:07 ` José Roberto de Souza
2021-09-10 13:38 ` Gwan-gyeong Mun
2021-09-09 23:07 ` [Intel-gfx] [PATCH 3/5] drm/i915/display: Wait at least 2 frames before selective update José Roberto de Souza
` (6 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: José Roberto de Souza @ 2021-09-09 23:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Gwan-gyeong Mun, José Roberto de Souza
Wa_16014451276 fixes the starting coordinate for PSR2 selective
updates. CHICKEN_TRANS definition of the workaround bit has a wrong
name based on workaround definition and HSD.
Wa_14014971508 allows the screen to continue to be updated when
coming back from DC5/DC6 and SF_SINGLE_FULL_FRAME bit is not kept
set in PSR2_MAN_TRK_CTL.
Wa_16012604467 fixes underruns when exiting PSR2 when it is in one
of its internal states.
Wa_14014971508 is still in pending status in BSpec but by
the time this is reviewed and ready to be merged it will be finalized.
BSpec: 54369
BSpec: 50054
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 23 ++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 36816abb3bcc0..92c0b2159559f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1086,6 +1086,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
intel_de_write(dev_priv, reg, chicken);
}
+ /* Wa_16014451276:adlp */
+ if (IS_ALDERLAKE_P(dev_priv) &&
+ intel_dp->psr.psr2_enabled)
+ intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
+ D13_1_BASED_X_GRANULARITY);
+
/*
* Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
* mask LPSP to avoid dependency on other drivers that might block
@@ -1131,6 +1137,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
TRANS_SET_CONTEXT_LATENCY_MASK,
TRANS_SET_CONTEXT_LATENCY_VALUE(1));
+
+ /* Wa_16012604467:adlp */
+ if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
+ intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
+ CLKGATE_DIS_MISC_DMASC_GATING_DIS);
}
static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
@@ -1320,6 +1331,11 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
TRANS_SET_CONTEXT_LATENCY_MASK, 0);
+ /* Wa_16012604467:adlp */
+ if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
+ intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
+ CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
+
intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
/* Disable PSR on Sink */
@@ -1488,8 +1504,13 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
u32 val = PSR2_MAN_TRK_CTL_ENABLE;
if (full_update) {
+ /*
+ * Wa_14014971508:adlp
+ * SINGLE_FULL_FRAME bit is not hold in register so can not be
+ * restored by DMC, so using CONTINUOS_FULL_FRAME to mimic that
+ */
if (IS_ALDERLAKE_P(dev_priv))
- val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+ val |= ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
else
val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2853cc005ee6..0de2f7541da6c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8235,6 +8235,7 @@ enum {
#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
+#define D13_1_BASED_X_GRANULARITY REG_BIT(18)
#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
@@ -12789,4 +12790,7 @@ enum skl_power_gate {
#define CLKREQ_POLICY _MMIO(0x101038)
#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
+#define CLKGATE_DIS_MISC _MMIO(0x46534)
+#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
+
#endif /* _I915_REG_H_ */
--
2.33.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 3/5] drm/i915/display: Wait at least 2 frames before selective update
2021-09-09 23:07 [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation José Roberto de Souza
2021-09-09 23:07 ` [Intel-gfx] [PATCH 2/5] drm/i915/display/adlp: Add new PSR2 workarounds José Roberto de Souza
@ 2021-09-09 23:07 ` José Roberto de Souza
2021-09-10 13:26 ` Gwan-gyeong Mun
2021-09-09 23:07 ` [Intel-gfx] [PATCH 4/5] drm/i915/display/psr: Use drm damage helpers to calculate plane damaged area José Roberto de Souza
` (5 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: José Roberto de Souza @ 2021-09-09 23:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Gwan-gyeong Mun, José Roberto de Souza
BSpec states that the minimum number of frames before selective update
is 2, so making sure this minimum limit is fulfilled.
BSpec: 50422
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 92c0b2159559f..1a3effa3ce709 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -510,7 +510,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
val |= EDP_Y_COORDINATE_ENABLE;
- val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
+ val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2));
val |= intel_psr2_get_tp_time(intel_dp);
/* Wa_22012278275:adl-p */
--
2.33.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 4/5] drm/i915/display/psr: Use drm damage helpers to calculate plane damaged area
2021-09-09 23:07 [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation José Roberto de Souza
2021-09-09 23:07 ` [Intel-gfx] [PATCH 2/5] drm/i915/display/adlp: Add new PSR2 workarounds José Roberto de Souza
2021-09-09 23:07 ` [Intel-gfx] [PATCH 3/5] drm/i915/display: Wait at least 2 frames before selective update José Roberto de Souza
@ 2021-09-09 23:07 ` José Roberto de Souza
2021-09-13 16:03 ` Gwan-gyeong Mun
2021-09-09 23:07 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled José Roberto de Souza
` (4 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: José Roberto de Souza @ 2021-09-09 23:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter, Gwan-gyeong Mun, José Roberto de Souza
drm_atomic_helper_damage_iter_init() + drm_atomic_for_each_plane_damage()
returns the full plane area in case no damaged area was set by
userspace or it was discarted by driver.
This is important to fix the rendering of userspace applications that
does frontbuffer rendering and notify driver about dirty areas but do
not set any dirty clips.
With this we don't need to worry about to check and mark the whole
area as damaged in page flips.
Another important change here is the move of
drm_atomic_add_affected_planes() call, it needs to called late
otherwise the area of all the planes would be added to pipe_clip and
not saving power.
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 37 +++++++++---------------
1 file changed, 13 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1a3effa3ce709..670b0ceba110f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -22,6 +22,7 @@
*/
#include <drm/drm_atomic_helper.h>
+#include <drm/drm_damage_helper.h>
#include "display/intel_dp.h"
@@ -1577,10 +1578,6 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
if (!crtc_state->enable_psr2_sel_fetch)
return 0;
- ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
- if (ret)
- return ret;
-
/*
* Calculate minimal selective fetch area of each plane and calculate
* the pipe damaged area.
@@ -1590,8 +1587,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
new_plane_state, i) {
struct drm_rect src, damaged_area = { .y1 = -1 };
- struct drm_mode_rect *damaged_clips;
- u32 num_clips, j;
+ struct drm_atomic_helper_damage_iter iter;
+ struct drm_rect clip;
if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
continue;
@@ -1611,8 +1608,6 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
break;
}
- num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi);
-
/*
* If visibility or plane moved, mark the whole plane area as
* damaged as it needs to be complete redraw in the new and old
@@ -1633,14 +1628,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
clip_area_update(&pipe_clip, &damaged_area);
}
continue;
- } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha ||
- (!num_clips &&
- new_plane_state->uapi.fb != old_plane_state->uapi.fb)) {
- /*
- * If the plane don't have damaged areas but the
- * framebuffer changed or alpha changed, mark the whole
- * plane area as damaged.
- */
+ } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
+ /* If alpha changed mark the whole plane area as damaged */
damaged_area.y1 = new_plane_state->uapi.dst.y1;
damaged_area.y2 = new_plane_state->uapi.dst.y2;
clip_area_update(&pipe_clip, &damaged_area);
@@ -1648,15 +1637,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
}
drm_rect_fp_to_int(&src, &new_plane_state->uapi.src);
- damaged_clips = drm_plane_get_damage_clips(&new_plane_state->uapi);
- for (j = 0; j < num_clips; j++) {
- struct drm_rect clip;
-
- clip.x1 = damaged_clips[j].x1;
- clip.y1 = damaged_clips[j].y1;
- clip.x2 = damaged_clips[j].x2;
- clip.y2 = damaged_clips[j].y2;
+ drm_atomic_helper_damage_iter_init(&iter,
+ &old_plane_state->uapi,
+ &new_plane_state->uapi);
+ drm_atomic_for_each_plane_damage(&iter, &clip) {
if (drm_rect_intersect(&clip, &src))
clip_area_update(&damaged_area, &clip);
}
@@ -1672,6 +1657,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
if (full_update)
goto skip_sel_fetch_set_loop;
+ ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
+ if (ret)
+ return ret;
+
intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
/*
--
2.33.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 5/5] drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled
2021-09-09 23:07 [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation José Roberto de Souza
` (2 preceding siblings ...)
2021-09-09 23:07 ` [Intel-gfx] [PATCH 4/5] drm/i915/display/psr: Use drm damage helpers to calculate plane damaged area José Roberto de Souza
@ 2021-09-09 23:07 ` José Roberto de Souza
2021-09-10 13:29 ` Gwan-gyeong Mun
2021-09-10 0:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation Patchwork
` (3 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: José Roberto de Souza @ 2021-09-09 23:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Gwan-gyeong Mun, José Roberto de Souza
Not sure why but when moving the cursor fast it causes some artifacts
of the cursor to be left in the cursor path, adding some pixels above
the cursor to the damaged area fixes the issue, so leaving this as a
workaround until proper fix is found.
This is reproducile on TGL and ADL-P.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 670b0ceba110f..18e721dde22e2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1565,6 +1565,28 @@ static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *c
drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
}
+/*
+ * FIXME: Not sure why but when moving the cursor fast it causes some artifacts
+ * of the cursor to be left in the cursor path, adding some pixels above the
+ * cursor to the damaged area fixes the issue.
+ */
+static void cursor_area_workaround(const struct intel_plane_state *new_plane_state,
+ struct drm_rect *damaged_area,
+ struct drm_rect *pipe_clip)
+{
+ const struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
+ int height;
+
+ if (plane->id != PLANE_CURSOR)
+ return;
+
+ height = drm_rect_height(&new_plane_state->uapi.dst) / 2;
+ damaged_area->y1 -= height;
+ damaged_area->y1 = max(damaged_area->y1, 0);
+
+ clip_area_update(pipe_clip, damaged_area);
+}
+
int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -1627,6 +1649,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
damaged_area.y2 = new_plane_state->uapi.dst.y2;
clip_area_update(&pipe_clip, &damaged_area);
}
+
+ cursor_area_workaround(new_plane_state, &damaged_area,
+ &pipe_clip);
continue;
} else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
/* If alpha changed mark the whole plane area as damaged */
--
2.33.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation
2021-09-09 23:07 [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation José Roberto de Souza
` (3 preceding siblings ...)
2021-09-09 23:07 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled José Roberto de Souza
@ 2021-09-10 0:11 ` Patchwork
2021-09-10 0:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2021-09-10 0:11 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation
URL : https://patchwork.freedesktop.org/series/94526/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation
2021-09-09 23:07 [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation José Roberto de Souza
` (4 preceding siblings ...)
2021-09-10 0:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation Patchwork
@ 2021-09-10 0:39 ` Patchwork
2021-09-10 2:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-10 13:39 ` [Intel-gfx] [PATCH 1/5] " Gwan-gyeong Mun
7 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2021-09-10 0:39 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3690 bytes --]
== Series Details ==
Series: series starting with [1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation
URL : https://patchwork.freedesktop.org/series/94526/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10566 -> Patchwork_21008
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/index.html
Known issues
------------
Here are the changes found in Patchwork_21008 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-kbl-7567u: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/fi-kbl-7567u/igt@amdgpu/amd_cs_nop@sync-gfx0.html
* igt@fbdev@write:
- fi-bdw-gvtdvm: NOTRUN -> [SKIP][2] ([fdo#109271]) +5 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/fi-bdw-gvtdvm/igt@fbdev@write.html
* igt@gem_exec_suspend@basic-s0:
- fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][3] ([i915#146])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/fi-bdw-gvtdvm/igt@gem_exec_suspend@basic-s0.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-rkl-guc: [PASS][4] -> [SKIP][5] ([fdo#109308])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/fi-rkl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/fi-rkl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][6] -> [INCOMPLETE][7] ([i915#3921])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: [DMESG-WARN][8] -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
Participating hosts (44 -> 39)
------------------------------
Additional (1): fi-bdw-gvtdvm
Missing (6): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-4 fi-bdw-samus bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10566 -> Patchwork_21008
CI-20190529: 20190529
CI_DRM_10566: 8c2d4adb2cd72ea1fae0c95562362319406f6d8e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6203: 64452a46b57ca4ef35eb65a547df8ed1b131e8f0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21008: 6a5a62753b84653003695a67a8aea3cf44a2ab05 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6a5a62753b84 drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled
cce24682af93 drm/i915/display/psr: Use drm damage helpers to calculate plane damaged area
2c287be2545f drm/i915/display: Wait at least 2 frames before selective update
922da922a44f drm/i915/display/adlp: Add new PSR2 workarounds
f02430c9cb76 drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/index.html
[-- Attachment #2: Type: text/html, Size: 4529 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation
2021-09-09 23:07 [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation José Roberto de Souza
` (5 preceding siblings ...)
2021-09-10 0:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-09-10 2:26 ` Patchwork
2021-09-10 13:39 ` [Intel-gfx] [PATCH 1/5] " Gwan-gyeong Mun
7 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2021-09-10 2:26 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30324 bytes --]
== Series Details ==
Series: series starting with [1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation
URL : https://patchwork.freedesktop.org/series/94526/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10566_full -> Patchwork_21008_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21008_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21008_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21008_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@system-suspend-devices:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-iclb3/igt@i915_pm_rpm@system-suspend-devices.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-iclb4/igt@i915_pm_rpm@system-suspend-devices.html
Known issues
------------
Here are the changes found in Patchwork_21008_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_ctx_persistence@legacy-engines-mixed-process:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-snb6/igt@gem_ctx_persistence@legacy-engines-mixed-process.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-tglb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb1/igt@gem_exec_fair@basic-none-share@rcs0.html
- shard-apl: [PASS][8] -> [SKIP][9] ([fdo#109271])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-apl6/igt@gem_exec_fair@basic-none-share@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
- shard-skl: NOTRUN -> [SKIP][10] ([fdo#109271]) +9 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-skl4/igt@gem_render_copy@y-tiled-to-vebox-yf-tiled.html
* igt@gem_softpin@evict-snoop:
- shard-tglb: NOTRUN -> [SKIP][11] ([fdo#109312])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@gem_softpin@evict-snoop.html
* igt@gem_spin_batch@user-each:
- shard-skl: [PASS][12] -> [FAIL][13] ([i915#2898])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-skl8/igt@gem_spin_batch@user-each.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-skl3/igt@gem_spin_batch@user-each.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3323])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][15] ([i915#3318])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-skl4/igt@gem_userptr_blits@vma-merge.html
* igt@gen3_mixed_blits:
- shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271]) +52 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-kbl1/igt@gen3_mixed_blits.html
* igt@gen7_exec_parse@basic-offset:
- shard-tglb: NOTRUN -> [SKIP][17] ([fdo#109289])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#2856])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@gen9_exec_parse@bb-start-cmd.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#454])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271]) +259 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl2/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_selftest@live@gt_lrc:
- shard-tglb: NOTRUN -> [DMESG-FAIL][22] ([i915#2373])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- shard-tglb: NOTRUN -> [DMESG-FAIL][23] ([i915#1759] / [i915#2291])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-tglb: [PASS][24] -> [INCOMPLETE][25] ([i915#456]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-tglb6/igt@i915_suspend@fence-restore-tiled2untiled.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb7/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3777]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-tglb: NOTRUN -> [SKIP][27] ([fdo#111615])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#3689] / [i915#3886])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +9 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl8/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3886]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-kbl1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][31] ([i915#3689])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#109284] / [fdo#111827]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +19 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl2/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_color_chamelium@pipe-a-ctm-0-75:
- shard-kbl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-kbl1/igt@kms_color_chamelium@pipe-a-ctm-0-75.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-snb: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +19 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-snb7/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-a-gamma:
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109284] / [fdo#111827]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-iclb5/igt@kms_color_chamelium@pipe-a-gamma.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][37] ([i915#1319]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl8/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-a-cursor-32x32-offscreen:
- shard-tglb: NOTRUN -> [SKIP][38] ([i915#3319]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-32x32-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-max-size-sliding:
- shard-glk: NOTRUN -> [SKIP][39] ([fdo#109271])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-glk5/igt@kms_cursor_crc@pipe-b-cursor-max-size-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#3359]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#2346])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [PASS][43] -> [FAIL][44] ([i915#79])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [PASS][45] -> [DMESG-WARN][46] ([i915#180])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
- shard-skl: [PASS][47] -> [INCOMPLETE][48] ([i915#146] / [i915#198])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-skl4/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [PASS][49] -> [FAIL][50] ([i915#2122])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-skl8/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-skl: NOTRUN -> [INCOMPLETE][51] ([i915#3699])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-skl4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt:
- shard-snb: NOTRUN -> [SKIP][52] ([fdo#109271]) +369 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-cpu:
- shard-tglb: NOTRUN -> [SKIP][53] ([fdo#111825]) +14 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_invalid_dotclock:
- shard-tglb: NOTRUN -> [SKIP][54] ([fdo#110577])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@kms_invalid_dotclock.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533]) +3 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#533])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-kbl7/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-skl: [PASS][57] -> [INCOMPLETE][58] ([i915#198])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-skl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][60] -> [FAIL][61] ([fdo#108145] / [i915#265])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][62] ([fdo#108145] / [i915#265])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][63] ([i915#265])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-a-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][64] ([i915#3536])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@kms_plane_lowres@pipe-a-tiling-none.html
* igt@kms_plane_lowres@pipe-c-tiling-none:
- shard-iclb: NOTRUN -> [SKIP][65] ([i915#3536])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-iclb5/igt@kms_plane_lowres@pipe-c-tiling-none.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2733])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#658]) +4 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#658])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-kbl1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#2920])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: NOTRUN -> [SKIP][70] ([fdo#109441])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-iclb5/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][71] -> [SKIP][72] ([fdo#109441])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-tglb: NOTRUN -> [FAIL][73] ([i915#132] / [i915#3467])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@kms_psr@psr2_sprite_plane_move.html
* igt@nouveau_crc@pipe-b-source-outp-inactive:
- shard-tglb: NOTRUN -> [SKIP][74] ([i915#2530])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@nouveau_crc@pipe-b-source-outp-inactive.html
* igt@prime_nv_pcopy@test3_2:
- shard-tglb: NOTRUN -> [SKIP][75] ([fdo#109291]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@prime_nv_pcopy@test3_2.html
* igt@syncobj_timeline@single-wait-available-signaled:
- shard-glk: [PASS][76] -> [DMESG-WARN][77] ([i915#118] / [i915#95])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-glk9/igt@syncobj_timeline@single-wait-available-signaled.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-glk4/igt@syncobj_timeline@single-wait-available-signaled.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2994])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl2/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@split-25:
- shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2994])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-kbl1/igt@sysfs_clients@split-25.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][80] ([i915#658]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-iclb6/igt@feature_discovery@psr2.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_ctx_persistence@many-contexts:
- {shard-rkl}: [FAIL][82] ([i915#2410]) -> [PASS][83] +2 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-6/igt@gem_ctx_persistence@many-contexts.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-6/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][84] ([i915#2369] / [i915#3063] / [i915#3648]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-tglb8/igt@gem_eio@unwedge-stress.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb3/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- {shard-rkl}: [FAIL][86] ([i915#2846]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-1/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][88] ([i915#2842]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][90] ([i915#2842]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_workarounds@suspend-resume:
- shard-kbl: [INCOMPLETE][92] ([i915#155]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-kbl4/igt@gem_workarounds@suspend-resume.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-kbl1/igt@gem_workarounds@suspend-resume.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][94] ([i915#1436] / [i915#716]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-glk5/igt@gen9_exec_parse@allowed-all.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-glk5/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_backlight@basic-brightness:
- {shard-rkl}: [SKIP][96] ([i915#3012]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-5/igt@i915_pm_backlight@basic-brightness.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-6/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][98] ([i915#454]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-iclb1/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-rkl}: [SKIP][100] ([i915#1397]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-5/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-tglb: [INCOMPLETE][102] ([i915#2411] / [i915#456] / [i915#750]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-tglb7/igt@i915_pm_rpm@system-suspend-execbuf.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb2/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-skl: [INCOMPLETE][104] ([i915#151]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-skl3/igt@i915_pm_rpm@system-suspend-modeset.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-skl4/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@kms_async_flips@test-cursor:
- {shard-rkl}: [SKIP][106] ([i915#1845]) -> [PASS][107] +10 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-5/igt@kms_async_flips@test-cursor.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-6/igt@kms_async_flips@test-cursor.html
* igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0:
- {shard-rkl}: [SKIP][108] ([i915#3721]) -> [PASS][109] +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-5/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- {shard-rkl}: [SKIP][110] ([i915#3638]) -> [PASS][111] +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-5/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-270:
- {shard-rkl}: [SKIP][112] ([fdo#111614]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-5/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-6/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
* igt@kms_color@pipe-a-ctm-0-25:
- {shard-rkl}: [SKIP][114] ([i915#1149] / [i915#1849] / [i915#4070]) -> [PASS][115] +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-5/igt@kms_color@pipe-a-ctm-0-25.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-6/igt@kms_color@pipe-a-ctm-0-25.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen:
- {shard-rkl}: [SKIP][116] ([fdo#112022] / [i915#4070]) -> [PASS][117] +6 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-5/igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][118] ([i915#180]) -> [PASS][119] +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge:
- {shard-rkl}: [SKIP][120] ([i915#1849] / [i915#4070]) -> [PASS][121] +3 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-5/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- {shard-rkl}: [SKIP][122] ([fdo#111825] / [i915#4070]) -> [PASS][123] +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
- shard-skl: [FAIL][124] ([i915#2346] / [i915#533]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled:
- {shard-rkl}: [SKIP][126] ([fdo#111314]) -> [PASS][127] +5 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][128] ([i915#180] / [i915#1982]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][130] ([i915#2122]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [DMESG-WARN][132] ([i915#180]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen:
- {shard-rkl}: [SKIP][134] ([i915#1849]) -> [PASS][135] +22 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][136] ([i915#1188]) -> [PASS][137] +1 similar issue
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-tglb: [INCOMPLETE][138] -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10566/shard-tglb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/shard-tglb5/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_psr@primary_render:
- {shard-rkl}: [SKIP][140] ([i915#1072]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.or
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21008/index.html
[-- Attachment #2: Type: text/html, Size: 33484 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 3/5] drm/i915/display: Wait at least 2 frames before selective update
2021-09-09 23:07 ` [Intel-gfx] [PATCH 3/5] drm/i915/display: Wait at least 2 frames before selective update José Roberto de Souza
@ 2021-09-10 13:26 ` Gwan-gyeong Mun
0 siblings, 0 replies; 19+ messages in thread
From: Gwan-gyeong Mun @ 2021-09-10 13:26 UTC (permalink / raw)
To: José Roberto de Souza, intel-gfx
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
On 9/10/21 2:07 AM, José Roberto de Souza wrote:
> BSpec states that the minimum number of frames before selective update
> is 2, so making sure this minimum limit is fulfilled.
>
> BSpec: 50422
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 92c0b2159559f..1a3effa3ce709 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -510,7 +510,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
> val |= EDP_Y_COORDINATE_ENABLE;
>
> - val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
> + val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2));
> val |= intel_psr2_get_tp_time(intel_dp);
>
> /* Wa_22012278275:adl-p */
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 5/5] drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled
2021-09-09 23:07 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled José Roberto de Souza
@ 2021-09-10 13:29 ` Gwan-gyeong Mun
0 siblings, 0 replies; 19+ messages in thread
From: Gwan-gyeong Mun @ 2021-09-10 13:29 UTC (permalink / raw)
To: José Roberto de Souza, intel-gfx
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
On 9/10/21 2:07 AM, José Roberto de Souza wrote:
> Not sure why but when moving the cursor fast it causes some artifacts
> of the cursor to be left in the cursor path, adding some pixels above
> the cursor to the damaged area fixes the issue, so leaving this as a
> workaround until proper fix is found.
>
> This is reproducile on TGL and ADL-P.
>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 670b0ceba110f..18e721dde22e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1565,6 +1565,28 @@ static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *c
> drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
> }
>
> +/*
> + * FIXME: Not sure why but when moving the cursor fast it causes some artifacts
> + * of the cursor to be left in the cursor path, adding some pixels above the
> + * cursor to the damaged area fixes the issue.
> + */
> +static void cursor_area_workaround(const struct intel_plane_state *new_plane_state,
> + struct drm_rect *damaged_area,
> + struct drm_rect *pipe_clip)
> +{
> + const struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
> + int height;
> +
> + if (plane->id != PLANE_CURSOR)
> + return;
> +
> + height = drm_rect_height(&new_plane_state->uapi.dst) / 2;
> + damaged_area->y1 -= height;
> + damaged_area->y1 = max(damaged_area->y1, 0);
> +
> + clip_area_update(pipe_clip, damaged_area);
> +}
> +
> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -1627,6 +1649,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> damaged_area.y2 = new_plane_state->uapi.dst.y2;
> clip_area_update(&pipe_clip, &damaged_area);
> }
> +
> + cursor_area_workaround(new_plane_state, &damaged_area,
> + &pipe_clip);
> continue;
> } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
> /* If alpha changed mark the whole plane area as damaged */
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 2/5] drm/i915/display/adlp: Add new PSR2 workarounds
2021-09-09 23:07 ` [Intel-gfx] [PATCH 2/5] drm/i915/display/adlp: Add new PSR2 workarounds José Roberto de Souza
@ 2021-09-10 13:38 ` Gwan-gyeong Mun
2021-09-10 16:29 ` Souza, Jose
0 siblings, 1 reply; 19+ messages in thread
From: Gwan-gyeong Mun @ 2021-09-10 13:38 UTC (permalink / raw)
To: José Roberto de Souza, intel-gfx
On 9/10/21 2:07 AM, José Roberto de Souza wrote:
> Wa_16014451276 fixes the starting coordinate for PSR2 selective
> updates. CHICKEN_TRANS definition of the workaround bit has a wrong
> name based on workaround definition and HSD.
>
> Wa_14014971508 allows the screen to continue to be updated when
> coming back from DC5/DC6 and SF_SINGLE_FULL_FRAME bit is not kept
> set in PSR2_MAN_TRK_CTL.
>
> Wa_16012604467 fixes underruns when exiting PSR2 when it is in one
> of its internal states.
>
> Wa_14014971508 is still in pending status in BSpec but by
> the time this is reviewed and ready to be merged it will be finalized.
>
> BSpec: 54369
> BSpec: 50054
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 23 ++++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 2 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 36816abb3bcc0..92c0b2159559f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1086,6 +1086,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
> intel_de_write(dev_priv, reg, chicken);
> }
>
> + /* Wa_16014451276:adlp */
> + if (IS_ALDERLAKE_P(dev_priv) &&
> + intel_dp->psr.psr2_enabled)
> + intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
> + D13_1_BASED_X_GRANULARITY);
Depending on the capability of the PSR panel, the following setting may
not be necessary, could you add some comments such as "force enable
1-based X granularity on PSR2 VSC SDP"?
> +
> /*
> * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
> * mask LPSP to avoid dependency on other drivers that might block
> @@ -1131,6 +1137,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
> TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
> TRANS_SET_CONTEXT_LATENCY_MASK,
> TRANS_SET_CONTEXT_LATENCY_VALUE(1));
> +
> + /* Wa_16012604467:adlp */
> + if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
> + intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
> + CLKGATE_DIS_MISC_DMASC_GATING_DIS);
> }
>
> static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
> @@ -1320,6 +1331,11 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
> TRANS_SET_CONTEXT_LATENCY_MASK, 0);
>
> + /* Wa_16012604467:adlp */
> + if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
> + intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
> + CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
> +
> intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
>
> /* Disable PSR on Sink */
> @@ -1488,8 +1504,13 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
> u32 val = PSR2_MAN_TRK_CTL_ENABLE;
>
> if (full_update) {
> + /*
> + * Wa_14014971508:adlp
> + * SINGLE_FULL_FRAME bit is not hold in register so can not be
> + * restored by DMC, so using CONTINUOS_FULL_FRAME to mimic that
> + */
> if (IS_ALDERLAKE_P(dev_priv))
> - val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> + val |= ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
> else
> val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c2853cc005ee6..0de2f7541da6c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8235,6 +8235,7 @@ enum {
> #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
> #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
> #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
> +#define D13_1_BASED_X_GRANULARITY REG_BIT(18)
The meaning of this macro is to set "force enable 1-based X granularity
on PSR2 VSC SDP" in Display 13.1 ADL, so the meaning of the macro may be
a little ambiguous.
> #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
> #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
> #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
> @@ -12789,4 +12790,7 @@ enum skl_power_gate {
> #define CLKREQ_POLICY _MMIO(0x101038)
> #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
>
> +#define CLKGATE_DIS_MISC _MMIO(0x46534)
> +#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
> +
> #endif /* _I915_REG_H_ */
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation
2021-09-09 23:07 [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation José Roberto de Souza
` (6 preceding siblings ...)
2021-09-10 2:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-09-10 13:39 ` Gwan-gyeong Mun
7 siblings, 0 replies; 19+ messages in thread
From: Gwan-gyeong Mun @ 2021-09-10 13:39 UTC (permalink / raw)
To: José Roberto de Souza, intel-gfx
Looks good to me.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
On 9/10/21 2:07 AM, José Roberto de Souza wrote:
> As the SU_REGION_START begins at 0, the SU_REGION_END should be number
> of lines - 1.
>
> BSpec: 50424
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 3f6fb7d67f84d..36816abb3bcc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1501,7 +1501,7 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
>
> if (IS_ALDERLAKE_P(dev_priv)) {
> val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
> - val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
> + val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1);
> } else {
> drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 2/5] drm/i915/display/adlp: Add new PSR2 workarounds
2021-09-10 13:38 ` Gwan-gyeong Mun
@ 2021-09-10 16:29 ` Souza, Jose
2021-09-13 16:09 ` Gwan-gyeong Mun
0 siblings, 1 reply; 19+ messages in thread
From: Souza, Jose @ 2021-09-10 16:29 UTC (permalink / raw)
To: Mun, Gwan-gyeong, intel-gfx
On Fri, 2021-09-10 at 16:38 +0300, Gwan-gyeong Mun wrote:
>
> On 9/10/21 2:07 AM, José Roberto de Souza wrote:
> > Wa_16014451276 fixes the starting coordinate for PSR2 selective
> > updates. CHICKEN_TRANS definition of the workaround bit has a wrong
> > name based on workaround definition and HSD.
> >
> > Wa_14014971508 allows the screen to continue to be updated when
> > coming back from DC5/DC6 and SF_SINGLE_FULL_FRAME bit is not kept
> > set in PSR2_MAN_TRK_CTL.
> >
> > Wa_16012604467 fixes underruns when exiting PSR2 when it is in one
> > of its internal states.
> >
> > Wa_14014971508 is still in pending status in BSpec but by
> > the time this is reviewed and ready to be merged it will be finalized.
> >
> > BSpec: 54369
> > BSpec: 50054
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 23 ++++++++++++++++++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > 2 files changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 36816abb3bcc0..92c0b2159559f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1086,6 +1086,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
> > intel_de_write(dev_priv, reg, chicken);
> > }
> >
> > + /* Wa_16014451276:adlp */
> > + if (IS_ALDERLAKE_P(dev_priv) &&
> > + intel_dp->psr.psr2_enabled)
> > + intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
> > + D13_1_BASED_X_GRANULARITY);
> Depending on the capability of the PSR panel, the following setting may
> not be necessary, could you add some comments such as "force enable
> 1-based X granularity on PSR2 VSC SDP"?
It was made sure that all alderlake-P BOM panels will have 1-based X granularity, I can add something like that.
> > +
> > /*
> > * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
> > * mask LPSP to avoid dependency on other drivers that might block
> > @@ -1131,6 +1137,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
> > TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
> > TRANS_SET_CONTEXT_LATENCY_MASK,
> > TRANS_SET_CONTEXT_LATENCY_VALUE(1));
> > +
> > + /* Wa_16012604467:adlp */
> > + if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
> > + intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
> > + CLKGATE_DIS_MISC_DMASC_GATING_DIS);
> > }
> >
> > static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
> > @@ -1320,6 +1331,11 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> > TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
> > TRANS_SET_CONTEXT_LATENCY_MASK, 0);
> >
> > + /* Wa_16012604467:adlp */
> > + if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
> > + intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
> > + CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
> > +
> > intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
> >
> > /* Disable PSR on Sink */
> > @@ -1488,8 +1504,13 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
> > u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> >
> > if (full_update) {
> > + /*
> > + * Wa_14014971508:adlp
> > + * SINGLE_FULL_FRAME bit is not hold in register so can not be
> > + * restored by DMC, so using CONTINUOS_FULL_FRAME to mimic that
> > + */
> > if (IS_ALDERLAKE_P(dev_priv))
> > - val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > + val |= ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
> > else
> > val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c2853cc005ee6..0de2f7541da6c 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8235,6 +8235,7 @@ enum {
> > #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
> > #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
> > #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
> > +#define D13_1_BASED_X_GRANULARITY REG_BIT(18)
> The meaning of this macro is to set "force enable 1-based X granularity
> on PSR2 VSC SDP" in Display 13.1 ADL, so the meaning of the macro may be
> a little ambiguous.
The name of registers are set to match specification name as close as possible not the use or meaning.
> > #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
> > #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
> > #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
> > @@ -12789,4 +12790,7 @@ enum skl_power_gate {
> > #define CLKREQ_POLICY _MMIO(0x101038)
> > #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
> >
> > +#define CLKGATE_DIS_MISC _MMIO(0x46534)
> > +#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
> > +
> > #endif /* _I915_REG_H_ */
> >
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915/display/psr: Use drm damage helpers to calculate plane damaged area
2021-09-09 23:07 ` [Intel-gfx] [PATCH 4/5] drm/i915/display/psr: Use drm damage helpers to calculate plane damaged area José Roberto de Souza
@ 2021-09-13 16:03 ` Gwan-gyeong Mun
2021-09-13 16:45 ` Souza, Jose
0 siblings, 1 reply; 19+ messages in thread
From: Gwan-gyeong Mun @ 2021-09-13 16:03 UTC (permalink / raw)
To: José Roberto de Souza, intel-gfx; +Cc: Daniel Vetter
On 9/10/21 2:07 AM, José Roberto de Souza wrote:
> drm_atomic_helper_damage_iter_init() + drm_atomic_for_each_plane_damage()
> returns the full plane area in case no damaged area was set by
> userspace or it was discarted by driver.
>
> This is important to fix the rendering of userspace applications that
> does frontbuffer rendering and notify driver about dirty areas but do
> not set any dirty clips.
>
> With this we don't need to worry about to check and mark the whole
> area as damaged in page flips.
>
> Another important change here is the move of
> drm_atomic_add_affected_planes() call, it needs to called late
> otherwise the area of all the planes would be added to pipe_clip and
> not saving power.
>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 37 +++++++++---------------
> 1 file changed, 13 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 1a3effa3ce709..670b0ceba110f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -22,6 +22,7 @@
> */
>
> #include <drm/drm_atomic_helper.h>
> +#include <drm/drm_damage_helper.h>
>
> #include "display/intel_dp.h"
>
> @@ -1577,10 +1578,6 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> if (!crtc_state->enable_psr2_sel_fetch)
> return 0;
>
> - ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
> - if (ret)
> - return ret;
> -
> /*
> * Calculate minimal selective fetch area of each plane and calculate
> * the pipe damaged area.
> @@ -1590,8 +1587,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
> new_plane_state, i) {
> struct drm_rect src, damaged_area = { .y1 = -1 };
> - struct drm_mode_rect *damaged_clips;
> - u32 num_clips, j;
> + struct drm_atomic_helper_damage_iter iter;
> + struct drm_rect clip;
>
> if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
> continue;
> @@ -1611,8 +1608,6 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> break;
> }
>
> - num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi);
> -
> /*
> * If visibility or plane moved, mark the whole plane area as
> * damaged as it needs to be complete redraw in the new and old
> @@ -1633,14 +1628,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> clip_area_update(&pipe_clip, &damaged_area);
> }
> continue;
> - } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha ||
> - (!num_clips &&
> - new_plane_state->uapi.fb != old_plane_state->uapi.fb)) {
> - /*
> - * If the plane don't have damaged areas but the
> - * framebuffer changed or alpha changed, mark the whole
> - * plane area as damaged.
> - */
> + } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
> + /* If alpha changed mark the whole plane area as damaged */
> damaged_area.y1 = new_plane_state->uapi.dst.y1;
> damaged_area.y2 = new_plane_state->uapi.dst.y2;
> clip_area_update(&pipe_clip, &damaged_area);
> @@ -1648,15 +1637,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> }
>
> drm_rect_fp_to_int(&src, &new_plane_state->uapi.src);
> - damaged_clips = drm_plane_get_damage_clips(&new_plane_state->uapi);
>
> - for (j = 0; j < num_clips; j++) {
> - struct drm_rect clip;
> -
> - clip.x1 = damaged_clips[j].x1;
> - clip.y1 = damaged_clips[j].y1;
> - clip.x2 = damaged_clips[j].x2;
> - clip.y2 = damaged_clips[j].y2;
> + drm_atomic_helper_damage_iter_init(&iter,
> + &old_plane_state->uapi,
> + &new_plane_state->uapi);
In the description of the drm_atomic_helper_damage_iter_init() function
says, in order to use drm_atomic_helper_damage_iter_init(), the driver
requires that the drm_atomic_helper_check_plane_state() helper function
should be called in advance.
However, in i915, drm_atomic_helper_check_plane_state() helper is not
used, and intel_atomic_plane_check_clipping() handles src.
And i915 is not using the atomic_check callback of
drm_plane_helper_funcs. Is it fine to use
drm_atomic_helper_damage_iter_init() in this case as well?
> + drm_atomic_for_each_plane_damage(&iter, &clip) {
> if (drm_rect_intersect(&clip, &src))
> clip_area_update(&damaged_area, &clip);
> }
> @@ -1672,6 +1657,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> if (full_update)
> goto skip_sel_fetch_set_loop;
>
> + ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
> + if (ret)
> + return ret;
> +
> intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
>
> /*
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 2/5] drm/i915/display/adlp: Add new PSR2 workarounds
2021-09-10 16:29 ` Souza, Jose
@ 2021-09-13 16:09 ` Gwan-gyeong Mun
2021-09-13 17:00 ` Souza, Jose
0 siblings, 1 reply; 19+ messages in thread
From: Gwan-gyeong Mun @ 2021-09-13 16:09 UTC (permalink / raw)
To: Souza, Jose, intel-gfx
On 9/10/21 7:29 PM, Souza, Jose wrote:
> On Fri, 2021-09-10 at 16:38 +0300, Gwan-gyeong Mun wrote:
>>
>> On 9/10/21 2:07 AM, José Roberto de Souza wrote:
>>> Wa_16014451276 fixes the starting coordinate for PSR2 selective
>>> updates. CHICKEN_TRANS definition of the workaround bit has a wrong
>>> name based on workaround definition and HSD.
>>>
>>> Wa_14014971508 allows the screen to continue to be updated when
>>> coming back from DC5/DC6 and SF_SINGLE_FULL_FRAME bit is not kept
>>> set in PSR2_MAN_TRK_CTL.
>>>
>>> Wa_16012604467 fixes underruns when exiting PSR2 when it is in one
>>> of its internal states.
>>>
>>> Wa_14014971508 is still in pending status in BSpec but by
>>> the time this is reviewed and ready to be merged it will be finalized.
>>>
>>> BSpec: 54369
>>> BSpec: 50054
>>> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_psr.c | 23 ++++++++++++++++++++++-
>>> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
>>> 2 files changed, 26 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index 36816abb3bcc0..92c0b2159559f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -1086,6 +1086,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
>>> intel_de_write(dev_priv, reg, chicken);
>>> }
>>>
>>> +/* Wa_16014451276:adlp */
>>> +if (IS_ALDERLAKE_P(dev_priv) &&
>>> + intel_dp->psr.psr2_enabled)
>>> +intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
>>> + D13_1_BASED_X_GRANULARITY);
>> Depending on the capability of the PSR panel, the following setting may
>> not be necessary, could you add some comments such as "force enable
>> 1-based X granularity on PSR2 VSC SDP"?
>
> It was made sure that all alderlake-P BOM panels will have 1-based X granularity, I can add something like that.
>
>
>>> +
>>> /*
>>> * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
>>> * mask LPSP to avoid dependency on other drivers that might block
>>> @@ -1131,6 +1137,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
>>> TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
>>> TRANS_SET_CONTEXT_LATENCY_MASK,
>>> TRANS_SET_CONTEXT_LATENCY_VALUE(1));
>>> +
>>> +/* Wa_16012604467:adlp */
>>> +if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
>>> +intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
>>> + CLKGATE_DIS_MISC_DMASC_GATING_DIS);
>>> }
>>>
>>> static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
>>> @@ -1320,6 +1331,11 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>>> TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
>>> TRANS_SET_CONTEXT_LATENCY_MASK, 0);
>>>
>>> +/* Wa_16012604467:adlp */
>>> +if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
>>> +intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
>>> + CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
>>> +
>>> intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
>>>
>>> /* Disable PSR on Sink */
>>> @@ -1488,8 +1504,13 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
>>> u32 val = PSR2_MAN_TRK_CTL_ENABLE;
>>>
>>> if (full_update) {
>>> +/*
>>> + * Wa_14014971508:adlp
>>> + * SINGLE_FULL_FRAME bit is not hold in register so can not be
>>> + * restored by DMC, so using CONTINUOS_FULL_FRAME to mimic that
>>> + */
>>> if (IS_ALDERLAKE_P(dev_priv))
>>> -val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
>>> +val |= ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
>>> else
>>> val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index c2853cc005ee6..0de2f7541da6c 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -8235,6 +8235,7 @@ enum {
>>> #define VSC_DATA_SEL_SOFTWARE_CONTROLREG_BIT(25) /* GLK */
>>> #define FECSTALL_DIS_DPTSTREAM_DPTTGREG_BIT(23)
>>> #define DDI_TRAINING_OVERRIDE_ENABLEREG_BIT(19)
>>> +#define D13_1_BASED_X_GRANULARITYREG_BIT(18)
>> The meaning of this macro is to set "force enable 1-based X granularity
>> on PSR2 VSC SDP" in Display 13.1 ADL, so the meaning of the macro may be
>> a little ambiguous.
>
> The name of registers are set to match specification name as close as possible not the use or meaning.
Yes, just looking at the macro, I thought that it could be interpreted
in two ways: D13 / 1_BASED_X_GRANULARITY or D13_1 / BASED_X_GRANULARITY.
If our macro naming convention is fine in this case, then I don't think
the code is the problem either.
>
>>> #define DDI_TRAINING_OVERRIDE_VALUEREG_BIT(18)
>>> #define DDIE_TRAINING_OVERRIDE_ENABLEREG_BIT(17) /* CHICKEN_TRANS_A only */
>>> #define DDIE_TRAINING_OVERRIDE_VALUEREG_BIT(16) /* CHICKEN_TRANS_A only */
>>> @@ -12789,4 +12790,7 @@ enum skl_power_gate {
>>> #define CLKREQ_POLICY_MMIO(0x101038)
>>> #define CLKREQ_POLICY_MEM_UP_OVRDREG_BIT(1)
>>>
>>> +#define CLKGATE_DIS_MISC_MMIO(0x46534)
>>> +#define CLKGATE_DIS_MISC_DMASC_GATING_DISREG_BIT(21)
>>> +
>>> #endif /* _I915_REG_H_ */
>>>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915/display/psr: Use drm damage helpers to calculate plane damaged area
2021-09-13 16:03 ` Gwan-gyeong Mun
@ 2021-09-13 16:45 ` Souza, Jose
2021-09-14 12:42 ` Gwan-gyeong Mun
0 siblings, 1 reply; 19+ messages in thread
From: Souza, Jose @ 2021-09-13 16:45 UTC (permalink / raw)
To: Mun, Gwan-gyeong, intel-gfx; +Cc: daniel
On Mon, 2021-09-13 at 19:03 +0300, Gwan-gyeong Mun wrote:
>
> On 9/10/21 2:07 AM, José Roberto de Souza wrote:
> > drm_atomic_helper_damage_iter_init() + drm_atomic_for_each_plane_damage()
> > returns the full plane area in case no damaged area was set by
> > userspace or it was discarted by driver.
> >
> > This is important to fix the rendering of userspace applications that
> > does frontbuffer rendering and notify driver about dirty areas but do
> > not set any dirty clips.
> >
> > With this we don't need to worry about to check and mark the whole
> > area as damaged in page flips.
> >
> > Another important change here is the move of
> > drm_atomic_add_affected_planes() call, it needs to called late
> > otherwise the area of all the planes would be added to pipe_clip and
> > not saving power.
> >
> > Cc: Daniel Vetter <daniel@ffwll.ch>
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 37 +++++++++---------------
> > 1 file changed, 13 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 1a3effa3ce709..670b0ceba110f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -22,6 +22,7 @@
> > */
> >
> > #include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_damage_helper.h>
> >
> > #include "display/intel_dp.h"
> >
> > @@ -1577,10 +1578,6 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > if (!crtc_state->enable_psr2_sel_fetch)
> > return 0;
> >
> > - ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
> > - if (ret)
> > - return ret;
> > -
> > /*
> > * Calculate minimal selective fetch area of each plane and calculate
> > * the pipe damaged area.
> > @@ -1590,8 +1587,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
> > new_plane_state, i) {
> > struct drm_rect src, damaged_area = { .y1 = -1 };
> > - struct drm_mode_rect *damaged_clips;
> > - u32 num_clips, j;
> > + struct drm_atomic_helper_damage_iter iter;
> > + struct drm_rect clip;
> >
> > if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
> > continue;
> > @@ -1611,8 +1608,6 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > break;
> > }
> >
> > - num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi);
> > -
> > /*
> > * If visibility or plane moved, mark the whole plane area as
> > * damaged as it needs to be complete redraw in the new and old
> > @@ -1633,14 +1628,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > clip_area_update(&pipe_clip, &damaged_area);
> > }
> > continue;
> > - } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha ||
> > - (!num_clips &&
> > - new_plane_state->uapi.fb != old_plane_state->uapi.fb)) {
> > - /*
> > - * If the plane don't have damaged areas but the
> > - * framebuffer changed or alpha changed, mark the whole
> > - * plane area as damaged.
> > - */
> > + } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
> > + /* If alpha changed mark the whole plane area as damaged */
> > damaged_area.y1 = new_plane_state->uapi.dst.y1;
> > damaged_area.y2 = new_plane_state->uapi.dst.y2;
> > clip_area_update(&pipe_clip, &damaged_area);
> > @@ -1648,15 +1637,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > }
> >
> > drm_rect_fp_to_int(&src, &new_plane_state->uapi.src);
> > - damaged_clips = drm_plane_get_damage_clips(&new_plane_state->uapi);
> >
> > - for (j = 0; j < num_clips; j++) {
> > - struct drm_rect clip;
> > -
> > - clip.x1 = damaged_clips[j].x1;
> > - clip.y1 = damaged_clips[j].y1;
> > - clip.x2 = damaged_clips[j].x2;
> > - clip.y2 = damaged_clips[j].y2;
> > + drm_atomic_helper_damage_iter_init(&iter,
> > + &old_plane_state->uapi,
> > + &new_plane_state->uapi);
> In the description of the drm_atomic_helper_damage_iter_init() function
> says, in order to use drm_atomic_helper_damage_iter_init(), the driver
> requires that the drm_atomic_helper_check_plane_state() helper function
> should be called in advance.
> However, in i915, drm_atomic_helper_check_plane_state() helper is not
> used, and intel_atomic_plane_check_clipping() handles src.
> And i915 is not using the atomic_check callback of
> drm_plane_helper_funcs. Is it fine to use
> drm_atomic_helper_damage_iter_init() in this case as well?
intel_atomic_plane_check_clipping() does the src rect rotation, scale and clipping that drm_atomic_helper_check_plane_state() also do, so we are safe
here.
> > + drm_atomic_for_each_plane_damage(&iter, &clip) {
> > if (drm_rect_intersect(&clip, &src))
> > clip_area_update(&damaged_area, &clip);
> > }
> > @@ -1672,6 +1657,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > if (full_update)
> > goto skip_sel_fetch_set_loop;
> >
> > + ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
> > + if (ret)
> > + return ret;
> > +
> > intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
> >
> > /*
> >
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 2/5] drm/i915/display/adlp: Add new PSR2 workarounds
2021-09-13 16:09 ` Gwan-gyeong Mun
@ 2021-09-13 17:00 ` Souza, Jose
2021-09-14 12:39 ` Gwan-gyeong Mun
0 siblings, 1 reply; 19+ messages in thread
From: Souza, Jose @ 2021-09-13 17:00 UTC (permalink / raw)
To: Mun, Gwan-gyeong, intel-gfx
On Mon, 2021-09-13 at 19:09 +0300, Gwan-gyeong Mun wrote:
>
> On 9/10/21 7:29 PM, Souza, Jose wrote:
> > On Fri, 2021-09-10 at 16:38 +0300, Gwan-gyeong Mun wrote:
> > >
> > > On 9/10/21 2:07 AM, José Roberto de Souza wrote:
> > > > Wa_16014451276 fixes the starting coordinate for PSR2 selective
> > > > updates. CHICKEN_TRANS definition of the workaround bit has a wrong
> > > > name based on workaround definition and HSD.
> > > >
> > > > Wa_14014971508 allows the screen to continue to be updated when
> > > > coming back from DC5/DC6 and SF_SINGLE_FULL_FRAME bit is not kept
> > > > set in PSR2_MAN_TRK_CTL.
> > > >
> > > > Wa_16012604467 fixes underruns when exiting PSR2 when it is in one
> > > > of its internal states.
> > > >
> > > > Wa_14014971508 is still in pending status in BSpec but by
> > > > the time this is reviewed and ready to be merged it will be finalized.
> > > >
> > > > BSpec: 54369
> > > > BSpec: 50054
> > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 23 ++++++++++++++++++++++-
> > > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > > > 2 files changed, 26 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 36816abb3bcc0..92c0b2159559f 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -1086,6 +1086,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
> > > > intel_de_write(dev_priv, reg, chicken);
> > > > }
> > > >
> > > > +/* Wa_16014451276:adlp */
> > > > +if (IS_ALDERLAKE_P(dev_priv) &&
> > > > + intel_dp->psr.psr2_enabled)
> > > > +intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
> > > > + D13_1_BASED_X_GRANULARITY);
> > > Depending on the capability of the PSR panel, the following setting may
> > > not be necessary, could you add some comments such as "force enable
> > > 1-based X granularity on PSR2 VSC SDP"?
> >
> > It was made sure that all alderlake-P BOM panels will have 1-based X granularity, I can add something like that.
> >
> >
> > > > +
> > > > /*
> > > > * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
> > > > * mask LPSP to avoid dependency on other drivers that might block
> > > > @@ -1131,6 +1137,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
> > > > TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
> > > > TRANS_SET_CONTEXT_LATENCY_MASK,
> > > > TRANS_SET_CONTEXT_LATENCY_VALUE(1));
> > > > +
> > > > +/* Wa_16012604467:adlp */
> > > > +if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
> > > > +intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
> > > > + CLKGATE_DIS_MISC_DMASC_GATING_DIS);
> > > > }
> > > >
> > > > static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
> > > > @@ -1320,6 +1331,11 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> > > > TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
> > > > TRANS_SET_CONTEXT_LATENCY_MASK, 0);
> > > >
> > > > +/* Wa_16012604467:adlp */
> > > > +if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
> > > > +intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
> > > > + CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
> > > > +
> > > > intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
> > > >
> > > > /* Disable PSR on Sink */
> > > > @@ -1488,8 +1504,13 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
> > > > u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> > > >
> > > > if (full_update) {
> > > > +/*
> > > > + * Wa_14014971508:adlp
> > > > + * SINGLE_FULL_FRAME bit is not hold in register so can not be
> > > > + * restored by DMC, so using CONTINUOS_FULL_FRAME to mimic that
> > > > + */
> > > > if (IS_ALDERLAKE_P(dev_priv))
> > > > -val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > > > +val |= ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
> > > > else
> > > > val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index c2853cc005ee6..0de2f7541da6c 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -8235,6 +8235,7 @@ enum {
> > > > #define VSC_DATA_SEL_SOFTWARE_CONTROLREG_BIT(25) /* GLK */
> > > > #define FECSTALL_DIS_DPTSTREAM_DPTTGREG_BIT(23)
> > > > #define DDI_TRAINING_OVERRIDE_ENABLEREG_BIT(19)
> > > > +#define D13_1_BASED_X_GRANULARITYREG_BIT(18)
> > > The meaning of this macro is to set "force enable 1-based X granularity
> > > on PSR2 VSC SDP" in Display 13.1 ADL, so the meaning of the macro may be
> > > a little ambiguous.
> >
> > The name of registers are set to match specification name as close as possible not the use or meaning.
> Yes, just looking at the macro, I thought that it could be interpreted
> in two ways: D13 / 1_BASED_X_GRANULARITY or D13_1 / BASED_X_GRANULARITY.
> If our macro naming convention is fine in this case, then I don't think
> the code is the problem either.
Okay yes someone could interpret into those 2 ways but checking bspec makes it clears that it is the first one.
I can rename to ADLP_1_BASED_X_GRANULARITY if you think it would make it better.
> >
> > > > #define DDI_TRAINING_OVERRIDE_VALUEREG_BIT(18)
> > > > #define DDIE_TRAINING_OVERRIDE_ENABLEREG_BIT(17) /* CHICKEN_TRANS_A only */
> > > > #define DDIE_TRAINING_OVERRIDE_VALUEREG_BIT(16) /* CHICKEN_TRANS_A only */
> > > > @@ -12789,4 +12790,7 @@ enum skl_power_gate {
> > > > #define CLKREQ_POLICY_MMIO(0x101038)
> > > > #define CLKREQ_POLICY_MEM_UP_OVRDREG_BIT(1)
> > > >
> > > > +#define CLKGATE_DIS_MISC_MMIO(0x46534)
> > > > +#define CLKGATE_DIS_MISC_DMASC_GATING_DISREG_BIT(21)
> > > > +
> > > > #endif /* _I915_REG_H_ */
> > > >
> >
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 2/5] drm/i915/display/adlp: Add new PSR2 workarounds
2021-09-13 17:00 ` Souza, Jose
@ 2021-09-14 12:39 ` Gwan-gyeong Mun
0 siblings, 0 replies; 19+ messages in thread
From: Gwan-gyeong Mun @ 2021-09-14 12:39 UTC (permalink / raw)
To: Souza, Jose, intel-gfx
On 9/13/21 8:00 PM, Souza, Jose wrote:
> On Mon, 2021-09-13 at 19:09 +0300, Gwan-gyeong Mun wrote:
>>
>> On 9/10/21 7:29 PM, Souza, Jose wrote:
>>> On Fri, 2021-09-10 at 16:38 +0300, Gwan-gyeong Mun wrote:
>>>>
>>>> On 9/10/21 2:07 AM, José Roberto de Souza wrote:
>>>>> Wa_16014451276 fixes the starting coordinate for PSR2 selective
>>>>> updates. CHICKEN_TRANS definition of the workaround bit has a wrong
>>>>> name based on workaround definition and HSD.
>>>>>
>>>>> Wa_14014971508 allows the screen to continue to be updated when
>>>>> coming back from DC5/DC6 and SF_SINGLE_FULL_FRAME bit is not kept
>>>>> set in PSR2_MAN_TRK_CTL.
>>>>>
>>>>> Wa_16012604467 fixes underruns when exiting PSR2 when it is in one
>>>>> of its internal states.
>>>>>
>>>>> Wa_14014971508 is still in pending status in BSpec but by
>>>>> the time this is reviewed and ready to be merged it will be finalized.
>>>>>
>>>>> BSpec: 54369
>>>>> BSpec: 50054
>>>>> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>>>>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/display/intel_psr.c | 23 ++++++++++++++++++++++-
>>>>> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
>>>>> 2 files changed, 26 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> index 36816abb3bcc0..92c0b2159559f 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> @@ -1086,6 +1086,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
>>>>> intel_de_write(dev_priv, reg, chicken);
>>>>> }
>>>>>
>>>>> +/* Wa_16014451276:adlp */
>>>>> +if (IS_ALDERLAKE_P(dev_priv) &&
>>>>> + intel_dp->psr.psr2_enabled)
>>>>> +intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
>>>>> + D13_1_BASED_X_GRANULARITY);
>>>> Depending on the capability of the PSR panel, the following setting may
>>>> not be necessary, could you add some comments such as "force enable
>>>> 1-based X granularity on PSR2 VSC SDP"?
>>>
>>> It was made sure that all alderlake-P BOM panels will have 1-based X granularity, I can add something like that.
>>>
>>>
>>>>> +
>>>>> /*
>>>>> * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
>>>>> * mask LPSP to avoid dependency on other drivers that might block
>>>>> @@ -1131,6 +1137,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
>>>>> TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
>>>>> TRANS_SET_CONTEXT_LATENCY_MASK,
>>>>> TRANS_SET_CONTEXT_LATENCY_VALUE(1));
>>>>> +
>>>>> +/* Wa_16012604467:adlp */
>>>>> +if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
>>>>> +intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
>>>>> + CLKGATE_DIS_MISC_DMASC_GATING_DIS);
>>>>> }
>>>>>
>>>>> static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
>>>>> @@ -1320,6 +1331,11 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>>>>> TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
>>>>> TRANS_SET_CONTEXT_LATENCY_MASK, 0);
>>>>>
>>>>> +/* Wa_16012604467:adlp */
>>>>> +if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
>>>>> +intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
>>>>> + CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
>>>>> +
>>>>> intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
>>>>>
>>>>> /* Disable PSR on Sink */
>>>>> @@ -1488,8 +1504,13 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
>>>>> u32 val = PSR2_MAN_TRK_CTL_ENABLE;
>>>>>
>>>>> if (full_update) {
>>>>> +/*
>>>>> + * Wa_14014971508:adlp
>>>>> + * SINGLE_FULL_FRAME bit is not hold in register so can not be
>>>>> + * restored by DMC, so using CONTINUOS_FULL_FRAME to mimic that
>>>>> + */
>>>>> if (IS_ALDERLAKE_P(dev_priv))
>>>>> -val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
>>>>> +val |= ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
>>>>> else
>>>>> val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>>> index c2853cc005ee6..0de2f7541da6c 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>>> @@ -8235,6 +8235,7 @@ enum {
>>>>> #define VSC_DATA_SEL_SOFTWARE_CONTROLREG_BIT(25) /* GLK */
>>>>> #define FECSTALL_DIS_DPTSTREAM_DPTTGREG_BIT(23)
>>>>> #define DDI_TRAINING_OVERRIDE_ENABLEREG_BIT(19)
>>>>> +#define D13_1_BASED_X_GRANULARITYREG_BIT(18)
>>>> The meaning of this macro is to set "force enable 1-based X granularity
>>>> on PSR2 VSC SDP" in Display 13.1 ADL, so the meaning of the macro may be
>>>> a little ambiguous.
>>>
>>> The name of registers are set to match specification name as close as possible not the use or meaning.
>> Yes, just looking at the macro, I thought that it could be interpreted
>> in two ways: D13 / 1_BASED_X_GRANULARITY or D13_1 / BASED_X_GRANULARITY.
>> If our macro naming convention is fine in this case, then I don't think
>> the code is the problem either.
>
> Okay yes someone could interpret into those 2 ways but checking bspec makes it clears that it is the first one.
> I can rename to ADLP_1_BASED_X_GRANULARITY if you think it would make it better.
>
the ADLP_1_BASED_X_GRANULARITY you suggested looks better.
>>>
>>>>> #define DDI_TRAINING_OVERRIDE_VALUEREG_BIT(18)
>>>>> #define DDIE_TRAINING_OVERRIDE_ENABLEREG_BIT(17) /* CHICKEN_TRANS_A only */
>>>>> #define DDIE_TRAINING_OVERRIDE_VALUEREG_BIT(16) /* CHICKEN_TRANS_A only */
>>>>> @@ -12789,4 +12790,7 @@ enum skl_power_gate {
>>>>> #define CLKREQ_POLICY_MMIO(0x101038)
>>>>> #define CLKREQ_POLICY_MEM_UP_OVRDREG_BIT(1)
>>>>>
>>>>> +#define CLKGATE_DIS_MISC_MMIO(0x46534)
>>>>> +#define CLKGATE_DIS_MISC_DMASC_GATING_DISREG_BIT(21)
>>>>> +
>>>>> #endif /* _I915_REG_H_ */
>>>>>
>>>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915/display/psr: Use drm damage helpers to calculate plane damaged area
2021-09-13 16:45 ` Souza, Jose
@ 2021-09-14 12:42 ` Gwan-gyeong Mun
0 siblings, 0 replies; 19+ messages in thread
From: Gwan-gyeong Mun @ 2021-09-14 12:42 UTC (permalink / raw)
To: Souza, Jose, intel-gfx; +Cc: daniel
On 9/13/21 7:45 PM, Souza, Jose wrote:
> On Mon, 2021-09-13 at 19:03 +0300, Gwan-gyeong Mun wrote:
>>
>> On 9/10/21 2:07 AM, José Roberto de Souza wrote:
>>> drm_atomic_helper_damage_iter_init() + drm_atomic_for_each_plane_damage()
>>> returns the full plane area in case no damaged area was set by
>>> userspace or it was discarted by driver.
>>>
>>> This is important to fix the rendering of userspace applications that
>>> does frontbuffer rendering and notify driver about dirty areas but do
>>> not set any dirty clips.
>>>
>>> With this we don't need to worry about to check and mark the whole
>>> area as damaged in page flips.
>>>
>>> Another important change here is the move of
>>> drm_atomic_add_affected_planes() call, it needs to called late
>>> otherwise the area of all the planes would be added to pipe_clip and
>>> not saving power.
>>>
>>> Cc: Daniel Vetter <daniel@ffwll.ch>
>>> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_psr.c | 37 +++++++++---------------
>>> 1 file changed, 13 insertions(+), 24 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index 1a3effa3ce709..670b0ceba110f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -22,6 +22,7 @@
>>> */
>>>
>>> #include <drm/drm_atomic_helper.h>
>>> +#include <drm/drm_damage_helper.h>
>>>
>>> #include "display/intel_dp.h"
>>>
>>> @@ -1577,10 +1578,6 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>> if (!crtc_state->enable_psr2_sel_fetch)
>>> return 0;
>>>
>>> -ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
>>> -if (ret)
>>> -return ret;
>>> -
>>> /*
>>> * Calculate minimal selective fetch area of each plane and calculate
>>> * the pipe damaged area.
>>> @@ -1590,8 +1587,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>> for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
>>> new_plane_state, i) {
>>> struct drm_rect src, damaged_area = { .y1 = -1 };
>>> -struct drm_mode_rect *damaged_clips;
>>> -u32 num_clips, j;
>>> +struct drm_atomic_helper_damage_iter iter;
>>> +struct drm_rect clip;
>>>
>>> if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
>>> continue;
>>> @@ -1611,8 +1608,6 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>> break;
>>> }
>>>
>>> -num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi);
>>> -
>>> /*
>>> * If visibility or plane moved, mark the whole plane area as
>>> * damaged as it needs to be complete redraw in the new and old
>>> @@ -1633,14 +1628,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>> clip_area_update(&pipe_clip, &damaged_area);
>>> }
>>> continue;
>>> -} else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha ||
>>> - (!num_clips &&
>>> - new_plane_state->uapi.fb != old_plane_state->uapi.fb)) {
>>> -/*
>>> - * If the plane don't have damaged areas but the
>>> - * framebuffer changed or alpha changed, mark the whole
>>> - * plane area as damaged.
>>> - */
>>> +} else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
>>> +/* If alpha changed mark the whole plane area as damaged */
>>> damaged_area.y1 = new_plane_state->uapi.dst.y1;
>>> damaged_area.y2 = new_plane_state->uapi.dst.y2;
>>> clip_area_update(&pipe_clip, &damaged_area);
>>> @@ -1648,15 +1637,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>> }
>>>
>>> drm_rect_fp_to_int(&src, &new_plane_state->uapi.src);
>>> -damaged_clips = drm_plane_get_damage_clips(&new_plane_state->uapi);
>>>
>>> -for (j = 0; j < num_clips; j++) {
>>> -struct drm_rect clip;
>>> -
>>> -clip.x1 = damaged_clips[j].x1;
>>> -clip.y1 = damaged_clips[j].y1;
>>> -clip.x2 = damaged_clips[j].x2;
>>> -clip.y2 = damaged_clips[j].y2;
>>> +drm_atomic_helper_damage_iter_init(&iter,
>>> + &old_plane_state->uapi,
>>> + &new_plane_state->uapi);
>> In the description of the drm_atomic_helper_damage_iter_init() function
>> says, in order to use drm_atomic_helper_damage_iter_init(), the driver
>> requires that the drm_atomic_helper_check_plane_state() helper function
>> should be called in advance.
>> However, in i915, drm_atomic_helper_check_plane_state() helper is not
>> used, and intel_atomic_plane_check_clipping() handles src.
>> And i915 is not using the atomic_check callback of
>> drm_plane_helper_funcs. Is it fine to use
>> drm_atomic_helper_damage_iter_init() in this case as well?
>
> intel_atomic_plane_check_clipping() does the src rect rotation, scale and clipping that drm_atomic_helper_check_plane_state() also do, so we are safe
> here.
>
ok then, the other changes look good to me.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>
>>> +drm_atomic_for_each_plane_damage(&iter, &clip) {
>>> if (drm_rect_intersect(&clip, &src))
>>> clip_area_update(&damaged_area, &clip);
>>> }
>>> @@ -1672,6 +1657,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>> if (full_update)
>>> goto skip_sel_fetch_set_loop;
>>>
>>> +ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
>>> +if (ret)
>>> +return ret;
>>> +
>>> intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
>>>
>>> /*
>>>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2021-09-14 12:43 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-09 23:07 [Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation José Roberto de Souza
2021-09-09 23:07 ` [Intel-gfx] [PATCH 2/5] drm/i915/display/adlp: Add new PSR2 workarounds José Roberto de Souza
2021-09-10 13:38 ` Gwan-gyeong Mun
2021-09-10 16:29 ` Souza, Jose
2021-09-13 16:09 ` Gwan-gyeong Mun
2021-09-13 17:00 ` Souza, Jose
2021-09-14 12:39 ` Gwan-gyeong Mun
2021-09-09 23:07 ` [Intel-gfx] [PATCH 3/5] drm/i915/display: Wait at least 2 frames before selective update José Roberto de Souza
2021-09-10 13:26 ` Gwan-gyeong Mun
2021-09-09 23:07 ` [Intel-gfx] [PATCH 4/5] drm/i915/display/psr: Use drm damage helpers to calculate plane damaged area José Roberto de Souza
2021-09-13 16:03 ` Gwan-gyeong Mun
2021-09-13 16:45 ` Souza, Jose
2021-09-14 12:42 ` Gwan-gyeong Mun
2021-09-09 23:07 ` [Intel-gfx] [PATCH 5/5] drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled José Roberto de Souza
2021-09-10 13:29 ` Gwan-gyeong Mun
2021-09-10 0:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation Patchwork
2021-09-10 0:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-10 2:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-10 13:39 ` [Intel-gfx] [PATCH 1/5] " Gwan-gyeong Mun
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