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(p200300EA8F296000F8E3535FF59FA97F.dip0.t-ipconnect.de. [2003:ea:8f29:6000:f8e3:535f:f59f:a97f]) by smtp.googlemail.com with ESMTPSA id w16sm1187802wrp.8.2020.03.03.11.50.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Mar 2020 11:50:45 -0800 (PST) Subject: Re: [PATCH v1] net: phy: tja11xx: add TJA1102 support To: Marc Kleine-Budde , Oleksij Rempel , Andrew Lunn , Florian Fainelli Cc: Marek Vasut , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Pengutronix Kernel Team , David Jander , "David S. Miller" References: <20200303073715.32301-1-o.rempel@pengutronix.de> <35d02d3d-0fd8-1fce-1f60-90a4a1377c78@pengutronix.de> From: Heiner Kallweit Message-ID: <9dae8f4a-43b0-e379-9b14-5a2a21640044@gmail.com> Date: Tue, 3 Mar 2020 20:50:40 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <35d02d3d-0fd8-1fce-1f60-90a4a1377c78@pengutronix.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03.03.2020 09:56, Marc Kleine-Budde wrote: > On 3/3/20 9:46 AM, Heiner Kallweit wrote: >> On 03.03.2020 08:37, Oleksij Rempel wrote: >>> TJA1102 is an dual T1 PHY chip. Both PHYs are separately addressable. >>> PHY 0 can be identified by PHY ID. PHY 1 has no PHY ID and can be >>> configured in device tree by setting compatible = >>> "ethernet-phy-id0180.dc81". > ^^^^^^^^^^^^^^^^^^^^^^^^ > >> I'm not sure I understand what you're doing here. The two ports of the chip >> are separate PHY's on individual MDIO bus addresses? > > Yes, Port 0 and Port 1 have seperate MFIO bus addresses, but only Port 0 > has a proper phy_id (== PHY_ID_TJA1102), while Port 1 just has 0. > > Currently we register Port 1 via the device tree compatible > "ethernet-phy-id0180.dc81". > Thanks for the explanation. Missed that part, then reading the PHY ID of the chip is skipped. For checking whether we are port 0 or 1 it wouldn't even be needed to read both PHY ID registers. One drawback of the solution might be that it works on DT-configured systems only (not sure how relevant this is). A little bit more detailed comment may be helpful, to avoid misunderstandings like mine. >> Reading the PHY ID registers here seems to repeat what phylib did already >> to populate phydev->phy_id. If port 1 has PHD ID 0 then the driver wouldn't >> bind and tja11xx_probe() would never be called (see phy_bus_match) > > But we "force" it via the DT compatible. Another option would be to make > up a phyid for Port 1 and hope that it doesn't collide with a real phy > id in other or upcoming chips. But that sounds not like a clean solution > either. > > Marc > Heiner