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Tue, 14 Sep 2021 00:31:49 -0700 Received: from bgsmsx602.gar.corp.intel.com (10.109.78.81) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 14 Sep 2021 00:31:48 -0700 Received: from bgsmsx602.gar.corp.intel.com ([10.109.78.81]) by BGSMSX602.gar.corp.intel.com ([10.109.78.81]) with mapi id 15.01.2242.012; Tue, 14 Sep 2021 13:01:46 +0530 From: "Kulkarni, Vandita" To: =?iso-8859-1?Q?Ville_Syrj=E4l=E4?= CC: "intel-gfx@lists.freedesktop.org" , "Nikula, Jani" , "Navare, Manasi D" Thread-Topic: [Intel-gfx] [PATCH] drm/i915/display: Enable second VDSC engine for higher moderates Thread-Index: AQHXqK0inD+P6mZa3kyDbF0BuUUoBquixrYAgABcbgA= Date: Tue, 14 Sep 2021 07:31:46 +0000 Message-ID: <9dd78b35e9bf41f8816a0e7dedf75c64@intel.com> References: <20210913143923.21119-1-vandita.kulkarni@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.200.16 x-originating-ip: [10.223.10.1] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Enable second VDSC engine for higher moderates X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" > -----Original Message----- > From: Ville Syrj=E4l=E4 > Sent: Tuesday, September 14, 2021 12:59 PM > To: Kulkarni, Vandita > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani = ; > Navare, Manasi D > Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Enable second VDSC > engine for higher moderates >=20 > On Mon, Sep 13, 2021 at 08:09:23PM +0530, Vandita Kulkarni wrote: > > Each VDSC operates with 1ppc throughput, hence enable the second VDSC > > engine when moderate is higher that the current cdclk. > > > > Signed-off-by: Vandita Kulkarni > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++-- > > 1 file changed, 10 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index 161c33b2c869..55878f65f724 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -70,6 +70,7 @@ > > #include "intel_tc.h" > > #include "intel_vdsc.h" > > #include "intel_vrr.h" > > +#include "intel_cdclk.h" > > > > #define DP_DPRX_ESI_LEN 14 > > > > @@ -1291,10 +1292,13 @@ static int intel_dp_dsc_compute_config(struct > intel_dp *intel_dp, > > struct drm_connector_state *conn_state, > > struct link_config_limits *limits) { > > + struct intel_cdclk_state *cdclk_state; > > struct intel_digital_port *dig_port =3D dp_to_dig_port(intel_dp); > > struct drm_i915_private *dev_priv =3D to_i915(dig_port- > >base.base.dev); > > const struct drm_display_mode *adjusted_mode =3D > > &pipe_config->hw.adjusted_mode; > > + struct intel_atomic_state *state =3D > > + to_intel_atomic_state(pipe_config- > >uapi.state); > > int pipe_bpp; > > int ret; > > > > @@ -1373,12 +1377,16 @@ static int intel_dp_dsc_compute_config(struct > intel_dp *intel_dp, > > } > > } > > > > + cdclk_state =3D intel_atomic_get_cdclk_state(state); > > + if (IS_ERR(cdclk_state)) > > + return PTR_ERR(cdclk_state); > > + > > /* > > * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate > > - * is greater than the maximum Cdclock and if slice count is even > > + * is greater than the current Cdclock and if slice count is even > > * then we need to use 2 VDSC instances. > > */ > > - if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq || > > + if (adjusted_mode->crtc_clock > cdclk_state->actual.cdclk || >=20 > This is wrong. We compute the cdclk based on the requirements of the > mode/etc., not the other way around. Okay , So you suggest that we set the cd clock to max when we have such req= uirement, than enabling the second engine? >=20 > > pipe_config->bigjoiner) { > > if (pipe_config->dsc.slice_count < 2) { > > drm_dbg_kms(&dev_priv->drm, > > -- > > 2.32.0 >=20 > -- > Ville Syrj=E4l=E4 > Intel