From: "Levente Révész" <levente.revesz@eilabs.com>
To: Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <brgl@bgdev.pl>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Martyn Welch <martyn.welch@collabora.com>,
Haibo Chen <haibo.chen@nxp.com>, Puyou Lu <puyou.lu@gmail.com>,
Justin Chen <justinpopo6@gmail.com>,
Andrey Gusakov <andrey.gusakov@cogentembedded.com>,
Nate Drude <nate.d@variscite.com>
Cc: linux-gpio@vger.kernel.org
Subject: [PATCH v2 5/6] gpio: pca953x: Add interrupt mask support for chips with the standard register set
Date: Wed, 26 Oct 2022 13:25:23 +0200 [thread overview]
Message-ID: <9df1a016-36be-14b7-9674-d18c7df208c7@eilabs.com> (raw)
In-Reply-To: <cc987520-d95b-01b9-5b65-53442ce122f6@eilabs.com>
Some chips in the pca953x family in addition to the standard 4
registers have a fifth interrupt mask register:
0: INPUT
1: OUTPUT
2: POLARITY
3: CONFIGURATION
4: INTERRUPT MASK
Chips with this register:
- pca9505
- pca9506
- pca9698
This register defaults to all interrupts disabled. The driver has to set
the register to use interrupts with these chips.
Add PCA953X_INT_MASK register. Use it as the interrupt register of
(non-pcal) pca953x chips.
Set pca9505 and pca9506 to use this register.
Signed-off-by: Levente Révész <levente.revesz@eilabs.com>
---
Changes in v2:
No changes.
drivers/gpio/gpio-pca953x.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index 2cf9541057a8..1e563d5b77e8 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -28,6 +28,7 @@
#define PCA953X_OUTPUT 0x01
#define PCA953X_INVERT 0x02
#define PCA953X_DIRECTION 0x03
+#define PCA953X_INT_MASK 0x04
#define REG_ADDR_MASK GENMASK(5, 0)
#define REG_ADDR_EXT BIT(6)
@@ -75,8 +76,8 @@
static const struct i2c_device_id pca953x_id[] = {
{ "pca6408", 8 | PCA953X_TYPE | PCA_INT, },
{ "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
- { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
- { "pca9506", 40 | PCA953X_TYPE | PCA_INT, },
+ { "pca9505", 40 | PCA953X_TYPE | PCA_MASKED_INT, },
+ { "pca9506", 40 | PCA953X_TYPE | PCA_MASKED_INT, },
{ "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
{ "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
{ "pca9536", 4 | PCA953X_TYPE, },
@@ -186,6 +187,7 @@ static const struct pca953x_reg_config pca953x_regs = {
.output = PCA953X_OUTPUT,
.input = PCA953X_INPUT,
.invert = PCA953X_INVERT,
+ .int_mask = PCA953X_INT_MASK,
};
static const struct pca953x_reg_config pcal953x_regs = {
@@ -255,6 +257,7 @@ static inline bool pca953x_has_int_mask_reg(const struct pca953x_chip *chip)
#define PCA953x_BANK_OUTPUT BIT(1)
#define PCA953x_BANK_POLARITY BIT(2)
#define PCA953x_BANK_CONFIG BIT(3)
+#define PCA953x_BANK_INT_MASK BIT(4)
#define PCA957x_BANK_INPUT BIT(0)
#define PCA957x_BANK_POLARITY BIT(1)
@@ -276,6 +279,8 @@ static inline bool pca953x_has_int_mask_reg(const struct pca953x_chip *chip)
* Output port 0x00 + 1 * bank_size RW
* Polarity Inversion port 0x00 + 2 * bank_size RW
* Configuration port 0x00 + 3 * bank_size RW
+ * - Some chips have the standard layout with additional interrupt mask:
+ * Interrupt Mask port 0x00 + 4 * bank_size RW
* - PCA957x with mixed up registers
* Input port 0x00 + 0 * bank_size R
* Polarity Inversion port 0x00 + 1 * bank_size RW
@@ -379,6 +384,10 @@ static bool pca953x_readable_register(struct device *dev, unsigned int reg)
case PCA953X_TYPE:
bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
+
+ if (pca953x_has_int_mask(chip))
+ bank |= PCA953x_BANK_INT_MASK;
+
break;
case PCAL953X_TYPE:
case PCAL653X_TYPE:
@@ -407,6 +416,10 @@ static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
case PCA953X_TYPE:
bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
PCA953x_BANK_CONFIG;
+
+ if (pca953x_has_int_mask(chip))
+ bank |= PCA953x_BANK_INT_MASK;
+
break;
case PCAL953X_TYPE:
case PCAL653X_TYPE:
@@ -1374,8 +1387,8 @@ static int pca953x_resume(struct device *dev)
static const struct of_device_id pca953x_dt_ids[] = {
{ .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), },
{ .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
- { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
- { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), },
+ { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_MASKED_INT), },
+ { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_MASKED_INT), },
{ .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
{ .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
{ .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
--
2.37.3
next prev parent reply other threads:[~2022-10-26 11:25 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-26 11:17 [PATCH v2 0/6] gpio: pca953x: Add interrupt mask support for pca953x chips Levente Révész
2022-10-26 11:18 ` [PATCH v2 1/6] gpio: pca953x: Convert PCA_TYPE from bits to number Levente Révész
2022-10-26 17:18 ` Andy Shevchenko
2022-10-26 17:21 ` Andy Shevchenko
2022-10-26 11:21 ` [PATCH v2 2/6] gpio: pca953x: Add PCAL953X as a separate chip type Levente Révész
2022-10-26 17:25 ` Andy Shevchenko
2022-10-26 17:28 ` Andy Shevchenko
2022-10-27 13:36 ` Levente Révész
2022-10-27 13:54 ` Martyn Welch
2022-10-27 17:03 ` Andy Shevchenko
2022-10-28 18:57 ` Levente Révész
2022-11-16 13:51 ` Levente Révész
2022-10-26 11:22 ` [PATCH v2 3/6] gpio: pca953x: Add helper function to check if chip has interrupts Levente Révész
2022-10-26 11:23 ` [PATCH v2 4/6] gpio: pca953x: Generalize interrupt mask register handling Levente Révész
2022-10-26 17:31 ` Andy Shevchenko
2022-10-26 11:25 ` Levente Révész [this message]
2022-10-26 16:49 ` [PATCH v2 5/6] gpio: pca953x: Add interrupt mask support for chips with the standard register set kernel test robot
2022-10-26 17:32 ` Andy Shevchenko
2022-10-26 22:13 ` kernel test robot
2022-10-26 22:13 ` kernel test robot
2022-10-26 11:26 ` [PATCH v2 6/6] gpio: pca953x: Enable interrupt for pca9698 Levente Révész
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