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[83.9.32.53]) by smtp.gmail.com with ESMTPSA id s14-20020a056512314e00b004cc82404ff9sm1946433lfi.7.2023.01.11.13.04.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Jan 2023 13:04:12 -0800 (PST) Message-ID: <9df6fc0f-2980-c20d-ea8f-28eb8fa4b75c@linaro.org> Date: Wed, 11 Jan 2023 22:04:11 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH 07/13] clk: qcom: cpu-8996: setup PLLs before registering clocks Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20230111192004.2509750-1-dmitry.baryshkov@linaro.org> <20230111192004.2509750-8-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: <20230111192004.2509750-8-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 11.01.2023 20:19, Dmitry Baryshkov wrote: > Setup all PLLs before registering clocks in the common clock framework. > This ensures that the clocks are not accessed before being setup in the > known way and that the CCF is in sync with the actual HW programming. > > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Konrad Dybcio Konrad > drivers/clk/qcom/clk-cpu-8996.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c > index ee7e18b37832..e390f4aadff1 100644 > --- a/drivers/clk/qcom/clk-cpu-8996.c > +++ b/drivers/clk/qcom/clk-cpu-8996.c > @@ -430,6 +430,11 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, > { > int i, ret; > > + clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config); > + clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); > + clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); > + clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); > + > for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) { > ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]); > if (ret) > @@ -442,11 +447,6 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, > return ret; > } > > - clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config); > - clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); > - clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); > - clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); > - > /* Enable alt PLLs */ > clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk); > clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk);