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Mon, 08 Aug 2022 11:10:41 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 8 Aug 2022 11:10:39 +0800 Received: from mcddlt001.gcn.mediatek.inc (10.19.240.15) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 8 Aug 2022 11:10:39 +0800 Message-ID: <9e175e3be42b465c010adc15d0e1704b24af14d8.camel@mediatek.com> Subject: Re: [PATCH 25/31] clk: mediatek: add CLK_XTAL support for clock driver From: Weijie Gao To: Simon Glass CC: U-Boot Mailing List , GSS_MTK_Uboot_upstream , Lukasz Majewski , Sean Anderson Date: Mon, 8 Aug 2022 11:10:38 +0800 In-Reply-To: References: <5c31c620ecdaa423c2761a633c7869b4af3fbf89.1659581119.git.weijie.gao@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.1-2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Thu, 2022-08-04 at 07:57 -0600, Simon Glass wrote: > Hi Weijie, > > On Wed, 3 Aug 2022 at 21:40, Weijie Gao > wrote: > > > > This add CLK_XTAL macro and flag to mediatek clock driver common > > part, > > to make thi SoC that has clock directlly connect to XTAL working. > > > > Signed-off-by: Weijie Gao > > --- > > drivers/clk/mediatek/clk-mtk.c | 3 +++ > > drivers/clk/mediatek/clk-mtk.h | 3 ++- > > 2 files changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/clk/mediatek/clk-mtk.c > > b/drivers/clk/mediatek/clk-mtk.c > > index be3846c85b..5a4650d137 100644 > > --- a/drivers/clk/mediatek/clk-mtk.c > > +++ b/drivers/clk/mediatek/clk-mtk.c > > @@ -296,6 +296,7 @@ static ulong > > mtk_topckgen_get_factor_rate(struct clk > > *clk, u32 off) > > rate = mtk_clk_find_parent_rate(clk, fdiv->parent, > > NULL); > > break; > > > > + case CLK_PARENT_XTAL: > > default: > > rate = priv->tree->xtal_rate; > > } > > @@ -314,6 +315,8 @@ static ulong > > mtk_infrasys_get_factor_rate(struct clk > > *clk, u32 off) > > rate = mtk_clk_find_parent_rate(clk, fdiv->parent, > > priv->parent); > > break; > > + case CLK_PARENT_XTAL: > > + rate = priv->tree->xtal_rate; > > Please document the fall-through here, if it is not a bug. This is indeed a bug. I'll fix it. > > > default: > > rate = mtk_clk_find_parent_rate(clk, fdiv->parent, > > NULL); > > } > > diff --git a/drivers/clk/mediatek/clk-mtk.h > > b/drivers/clk/mediatek/clk-mtk.h > > index 8536275671..211356697b 100644 > > --- a/drivers/clk/mediatek/clk-mtk.h > > +++ b/drivers/clk/mediatek/clk-mtk.h > > @@ -26,7 +26,8 @@ > > #define CLK_PARENT_APMIXED BIT(4) > > #define CLK_PARENT_TOPCKGEN BIT(5) > > #define CLK_PARENT_INFRASYS BIT(6) > > -#define CLK_PARENT_MASK GENMASK(6, 4) > > +#define CLK_PARENT_XTAL BIT(7) > > +#define CLK_PARENT_MASK GENMASK(7, 4) > > > > #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34 > > > > -- > > 2.17.1 > > > > REgards, > Simon