[MODERATED] Re: [patch 14/15] SSB updates V17 14

[Tom Lendacky <thomas.lendacky@amd.com>]

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On 05/16/2018 08:51 AM, speck for Thomas Gleixner wrote:

<snip>

> --- a/arch/x86/kernel/cpu/bugs.c
> +++ b/arch/x86/kernel/cpu/bugs.c
> @@ -154,6 +154,36 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl,
>  			wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
>  		}
>  	}
> +
> +	/*
> +	 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
> +	 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
> +	 */
> +	if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
> +	    !static_cpu_has(X86_FEATURE_VIRT_SSBD))
> +		return;
> +
> +	/*
> +	 * If the host has SSBD mitigation enabled, force it in the host's
> +	 * virtual MSR value. If its not permanently enabled, evaluate
> +	 * current's TIF_SSBD thread flag.
> +	 */
> +	if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
> +		hostsval = SPEC_CTRL_SSBD;

hostsval => hostval

Thanks,
Tom

> +	else
> +		hostval = ssbd_tif_to_spec_ctrl(ti->flags);
> +
> +	/* Sanitize the guest value */
> +	guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
> +
> +	if (hostval != guestval) {
> +		unsigned long tif;
> +
> +		tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
> +				 ssbd_spec_ctrl_to_tif(hostval);
> +
> +		speculative_store_bypass_update(tif);
> +	}
>  }
>  EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
>  
>