* [PATCH v3 0/4] Add base device tree files for QDU1000/QRU1000
@ 2022-10-26 20:04 Melody Olvera
2022-10-26 20:04 ` [PATCH v3 1/4] dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes Melody Olvera
` (4 more replies)
0 siblings, 5 replies; 21+ messages in thread
From: Melody Olvera @ 2022-10-26 20:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
This series adds the base device tree files and DTS support for the
Qualcomm QDU1000 and QRU1000 IDP SoCs, including the clocks, tlmm, smmu,
regulators, mmc, interconnects, cpufreq, and qup.
This patchset is based off of [1] which adds support for the PMIC arb used
on these SoCs. It also requires the dt-bindings from [2], [3], [4], [5],
and [6].
The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit
1000 are new SoCs meant for enabling Open RAN solutions. See more at
https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf
[1] https://lore.kernel.org/all/20220914165212.3705892-3-vkoul@kernel.org/
[2] https://lore.kernel.org/all/20221026190441.4002212-1-quic_molvera@quicinc.com/
[3] https://lore.kernel.org/all/20221026190457.4003037-1-quic_molvera@quicinc.com/
[4] https://lore.kernel.org/all/20221026190520.4004264-1-quic_molvera@quicinc.com/
[5] https://lore.kernel.org/all/20221026190534.4004945-1-quic_molvera@quicinc.com/
[6] https://lore.kernel.org/all/20221026190549.4005703-1-quic_molvera@quicinc.com/
Changes from v2:
- Revised device nodes to match updated dt-bindings
- Revised rpmh-rsc bindings to allow for generic regulator nodes
- Updated soc ordering
- Moved clock node to DTS files
- Updated regulator nodes to be generic
- Removed some unnecessary whitespace
Melody Olvera (4):
dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes
dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards
arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs
.../devicetree/bindings/arm/qcom.yaml | 16 +
.../bindings/soc/qcom/qcom,rpmh-rsc.yaml | 2 +-
arch/arm64/boot/dts/qcom/Makefile | 2 +
arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 245 +++
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++
arch/arm64/boot/dts/qcom/qru1000-idp.dts | 245 +++
arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 +
7 files changed, 1942 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
base-commit: 60eac8672b5b6061ec07499c0f1b79f6d94311ce
prerequisite-patch-id: 01437f10d7e0ca6365e82de7d3097110e5f5015b
prerequisite-patch-id: 2b59bb9d152bd8f3094e2a4e16d62191a40da67f
prerequisite-patch-id: c39bef976384eacd3ff0c28168bca355e3c1609d
prerequisite-patch-id: 116279180e6d97fbbdcc6738627daad393680a58
prerequisite-patch-id: 58dc60e65b348ec703dba9327f51656d4ac81717
prerequisite-patch-id: b67d749c7d2e3f6639c547f7908911c5dfb92ba4
prerequisite-patch-id: 93c63c6cdcc2acb525ea4a958b1c6443e6fe3580
prerequisite-patch-id: bc93c707c0fdbd6b25b0c595e6e121038ab89af4
prerequisite-patch-id: 5e7a02607aecd3f5346a2f450982601cf6935e54
--
2.25.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 1/4] dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes
2022-10-26 20:04 [PATCH v3 0/4] Add base device tree files for QDU1000/QRU1000 Melody Olvera
@ 2022-10-26 20:04 ` Melody Olvera
2022-10-27 15:08 ` Krzysztof Kozlowski
2022-10-26 20:04 ` [PATCH v3 2/4] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards Melody Olvera
` (3 subsequent siblings)
4 siblings, 1 reply; 21+ messages in thread
From: Melody Olvera @ 2022-10-26 20:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Update the bindings to allow for generic regulator nodes instead of
device-specific node names.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
index 4a50f1d27724..0e7e07975f3a 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
@@ -109,7 +109,7 @@ properties:
$ref: /schemas/power/qcom,rpmpd.yaml#
patternProperties:
- '-regulators$':
+ 'regulators$':
$ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
required:
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 2/4] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards
2022-10-26 20:04 [PATCH v3 0/4] Add base device tree files for QDU1000/QRU1000 Melody Olvera
2022-10-26 20:04 ` [PATCH v3 1/4] dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes Melody Olvera
@ 2022-10-26 20:04 ` Melody Olvera
2022-10-27 15:15 ` Krzysztof Kozlowski
2022-10-26 20:04 ` [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera
` (2 subsequent siblings)
4 siblings, 1 reply; 21+ messages in thread
From: Melody Olvera @ 2022-10-26 20:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Document the QDU1000 and QRU1000 SoC bindings and the boards that use
them.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 207e28260206..410df0bbae70 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -40,6 +40,8 @@ description: |
msm8996
msm8998
qcs404
+ qdu1000
+ qru1000
sa8155p
sa8540p
sc7180
@@ -76,6 +78,7 @@ description: |
mtp
qrd
sbc
+ x100
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
@@ -271,6 +274,19 @@ properties:
- qcom,ipq8074-hk10-c2
- const: qcom,ipq8074
+ - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
+ items:
+ - enum:
+ - qcom,qdu1000-idp
+ - qcom,qdu1000-x100
+ - const: qcom,qdu1000
+
+ - description: Qualcomm Technologies, Inc. Radio Unit 1000 platform
+ items:
+ - enum:
+ - qcom,qru1000-idp
+ - const: qcom,qru1000
+
- description: Qualcomm Technologies, Inc. SC7180 IDP
items:
- enum:
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-10-26 20:04 [PATCH v3 0/4] Add base device tree files for QDU1000/QRU1000 Melody Olvera
2022-10-26 20:04 ` [PATCH v3 1/4] dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes Melody Olvera
2022-10-26 20:04 ` [PATCH v3 2/4] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards Melody Olvera
@ 2022-10-26 20:04 ` Melody Olvera
2022-10-27 15:21 ` Krzysztof Kozlowski
2022-10-26 20:04 ` [PATCH v3 4/4] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera
2022-11-08 1:27 ` (subset) [PATCH v3 0/4] Add base device tree files for QDU1000/QRU1000 Bjorn Andersson
4 siblings, 1 reply; 21+ messages in thread
From: Melody Olvera @ 2022-10-26 20:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller
to boot to shell with console on these SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 +
2 files changed, 1433 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
new file mode 100644
index 000000000000..76474106e931
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -0,0 +1,1406 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-qdu1000.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,qdu1000.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen: chosen { };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ power-domain-names = "psci";
+ power-domains = <&CPU_PD0>;
+ qcom,freq-domains = <&cpufreq_hw 0>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
+ qcom,freq-domains = <&cpufreq_hw 0>;
+ next-level-cache = <&L2_100>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD2>;
+ power-domain-names = "psci";
+ qcom,freq-domains = <&cpufreq_hw 0>;
+ next-level-cache = <&L2_200>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD3>;
+ power-domain-names = "psci";
+ qcom,freq-domains = <&cpufreq_hw 0>;
+ next-level-cache = <&L2_300>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_OFF: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ entry-latency-us = <274>;
+ exit-latency-us = <480>;
+ min-residency-us = <3934>;
+ arm,psci-suspend-param = <0x40000004>;
+ local-timer-stop;
+ };
+ };
+
+ domain-idle-states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ entry-latency-us = <584>;
+ exit-latency-us = <2332>;
+ min-residency-us = <6118>;
+ arm,psci-suspend-param = <0x41000044>;
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "domain-idle-state";
+ entry-latency-us = <2893>;
+ exit-latency-us = <4023>;
+ min-residency-us = <9987>;
+ arm,psci-suspend-param = <0x41003344>;
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-qdu1000", "qcom,scm";
+ #reset-cells = <1>;
+ };
+ };
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,qdu1000-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-1 {
+ compatible = "qcom,qdu1000-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ CPU_PD0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&CPU_OFF>;
+ };
+
+ CPU_PD1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&CPU_OFF>;
+ };
+
+ CPU_PD2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&CPU_OFF>;
+ };
+
+ CPU_PD3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&CPU_OFF>;
+ };
+
+ CLUSTER_PD: power-domain-cluster {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>;
+ };
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: memory@80000000 {
+ no-map;
+ reg = <0x0 0x80000000 0x0 0x600000>;
+ };
+
+ xbl_dt_log_mem: memory@80600000 {
+ no-map;
+ reg = <0x0 0x80600000 0x0 0x40000>;
+ };
+
+ xbl_ramdump_mem: memory@80640000 {
+ no-map;
+ reg = <0x0 0x80640000 0x0 0x1c0000>;
+ };
+
+ aop_image_mem: memory@80800000 {
+ no-map;
+ reg = <0x0 0x80800000 0x0 0x60000>;
+ };
+
+ aop_cmd_db_mem: memory@80860000 {
+ compatible = "qcom,cmd-db";
+ no-map;
+ reg = <0x0 0x80860000 0x0 0x20000>;
+ };
+
+ aop_config_mem: memory@80880000 {
+ no-map;
+ reg = <0x0 0x80880000 0x0 0x20000>;
+ };
+
+ tme_crash_dump_mem: memory@808a0000 {
+ no-map;
+ reg = <0x0 0x808a0000 0x0 0x40000>;
+ };
+
+ tme_log_mem: memory@808e0000 {
+ no-map;
+ reg = <0x0 0x808e0000 0x0 0x4000>;
+ };
+
+ uefi_log_mem: memory@808e4000 {
+ no-map;
+ reg = <0x0 0x808e4000 0x0 0x10000>;
+ };
+
+ /* secdata region can be reused by apps */
+
+ smem_mem: memory@80900000 {
+ compatible = "qcom,smem";
+ no-map;
+ reg = <0x0 0x80900000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ cpucp_fw_mem: memory@80b00000 {
+ no-map;
+ reg = <0x0 0x80b00000 0x0 0x100000>;
+ };
+
+ xbl_sc_mem: memory@80c00000 {
+ no-map;
+ reg = <0x0 0x80c00000 0x0 0x40000>;
+ };
+
+ /* uefi region can be reused by apps */
+
+ tz_stat_mem: memory@81d00000 {
+ no-map;
+ reg = <0x0 0x81d00000 0x0 0x100000>;
+ };
+
+ tags_mem: memory@81e00000 {
+ no-map;
+ reg = <0x0 0x81e00000 0x0 0x500000>;
+ };
+
+ qtee_mem: memory@82300000 {
+ no-map;
+ reg = <0x0 0x82300000 0x0 0x500000>;
+ };
+
+ ta_mem: memory@82800000 {
+ no-map;
+ reg = <0x0 0x82800000 0x0 0xa00000>;
+ };
+
+ fs1_mem: memory@83200000 {
+ no-map;
+ reg = <0x0 0x83200000 0x0 0x400000>;
+ };
+
+ fs2_mem: memory@83600000 {
+ no-map;
+ reg = <0x0 0x83600000 0x0 0x400000>;
+ };
+
+ fs3_mem: memory@83a00000 {
+ no-map;
+ reg = <0x0 0x83a00000 0x0 0x400000>;
+ };
+
+ /* Linux kernel image is loaded at 0x83e00000 */
+
+ ipa_fw_mem: memory@8be00000 {
+ no-map;
+ reg = <0x0 0x8be00000 0x0 0x10000>;
+ };
+
+ ipa_gsi_mem: memory@8be10000 {
+ no-map;
+ reg = <0x0 0x8be10000 0x0 0x14000>;
+ };
+
+ mpss_mem: memory@8c000000 {
+ no-map;
+ reg = <0x0 0x8c000000 0x0 0x12c00000>;
+ };
+
+ q6_mpss_dtb_mem: memory@9ec00000 {
+ no-map;
+ reg = <0x0 0x9ec00000 0x0 0x80000>;
+ };
+
+ tenx_mem: memory@a0000000 {
+ no-map;
+ reg = <0x0 0xa0000000 0x0 0x19600000>;
+ };
+
+ oem_tenx_mem: memory@b9600000 {
+ no-map;
+ reg = <0x0 0xb9600000 0x0 0x6a00000>;
+ };
+
+ tenx_q6_buffer_mem: memory@c0000000 {
+ no-map;
+ reg = <0x0 0xc0000000 0x0 0x3200000>;
+ };
+
+ ipa_buffer_mem: memory@c3200000 {
+ no-map;
+ reg = <0x0 0xc3200000 0x0 0x12c00000>;
+ };
+ };
+
+ soc: soc@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@80000 {
+ compatible = "qcom,gcc-qdu1000", "syscon";
+ reg = <0x0 0x80000 0x0 0x1f4200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
+ clock-names = "bi_tcxo", "sleep_clk";
+ };
+
+ gpi_dma0: dma-controller@900000 {
+ compatible = "qcom,sm6350-gpi-dma";
+ #dma-cells = <3>;
+ reg = <0x0 0x900000 0x0 0x60000>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <12>;
+ dma-channel-mask = <0x3f>;
+ iommus = <&apps_smmu 0xf6 0x0>;
+ };
+
+ qupv3_id_0: geniqup@9c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x9c0000 0x0 0x2000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ clock-names = "m-ahb", "s-ahb";
+ iommus = <&apps_smmu 0xe3 0x0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0
+ &clk_virt SLAVE_QUP_CORE_0 0>;
+ interconnect-names = "qup-core";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ uart0: serial@980000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x980000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart0_default>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@984000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x984000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@984000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x984000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@988000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x988000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@988000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x988000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@98c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x98c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi3: spi@98c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x98c000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@990000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x990000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi4: spi@990000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x990000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@994000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x994000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi5: spi@994000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x994000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@998000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x998000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi6: spi@998000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x998000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ status = "disabled";
+ };
+
+ uart7: serial@99c000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x99c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,sm6350-gpi-dma";
+ #dma-cells = <3>;
+ reg = <0x0 0xa00000 0x0 0x60000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <12>;
+ dma-channel-mask = <0x3f>;
+ iommus = <&apps_smmu 0x116 0x0>;
+ };
+
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0xac0000 0x0 0x2000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ clock-names = "m-ahb", "s-ahb";
+ iommus = <&apps_smmu 0x103 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges;
+ status = "disabled";
+
+ uart8: serial@a80000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0xa80000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart8_default>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0xa84000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi9: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa84000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+ status = "disabled";
+ };
+
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0xa88000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c10_data_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi10: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa88000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+ status = "disabled";
+ };
+
+ i2c11: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0xa8c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c11_data_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi11: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa8c000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+ status = "disabled";
+ };
+
+ i2c12: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0xa90000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c12_data_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi12: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa90000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
+ status = "disabled";
+ };
+
+ i2c13: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0xa94000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart13: serial@a94000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0xa94000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart13_default>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi13: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa94000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
+ status = "disabled";
+ };
+
+ i2c14: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0xa98000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c14_data_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi14: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa98000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
+ status = "disabled";
+ };
+
+ i2c15: i2c@a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0xa9c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&qup_i2c15_data_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi15: spi@a9c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa9c000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
+ status = "disabled";
+ };
+ };
+
+ system_noc: interconnect@1640000 {
+ reg = <0x0 0x1640000 0x0 0x45080>;
+ compatible = "qcom,qdu1000-system-noc";
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x1f40000 0x0 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,qdu1000-pdc", "qcom,pdc";
+ reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
+ qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
+ <94 609 31>, <125 63 1>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ spmi_bus: spmi@c400000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0 0xc400000 0x0 0x3000>,
+ <0x0 0xc500000 0x0 0x400000>,
+ <0x0 0xc440000 0x0 0x80000>,
+ <0x0 0xc4c0000 0x0 0x10000>,
+ <0x0 0xc42d000 0x0 0x4000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
+ tlmm: pinctrl@f000000 {
+ compatible = "qcom,qdu1000-tlmm";
+ reg = <0x0 0xf000000 0x0 0x1000000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 151>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart0_default: qup-uart0-default-state {
+ pins = "gpio6", "gpio7", "gpio8", "gpio9";
+ function = "qup00";
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ pins = "gpio10", "gpio11";
+ function = "qup01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi1_data_clk: qup-spi1-data-clk-state {
+ pins = "gpio10", "gpio11", "gpio12";
+ function = "qup01";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi1_cs: qup-spi1-cs-state {
+ pins = "gpio13";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ pins = "gpio12", "gpio13";
+ function = "qup02";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ pins = "gpio12", "gpio13", "gpio10";
+ function = "qup02";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ pins = "gpio11";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ pins = "gpio14", "gpio15";
+ function = "qup03";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk-state {
+ pins = "gpio14", "gpio15", "gpio16";
+ function = "qup03";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_cs: qup-spi3-cs-state {
+ pins = "gpio17";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+ pins = "gpio16", "gpio17";
+ function = "qup04";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk-state {
+ pins = "gpio16", "gpio17", "gpio14";
+ function = "qup04";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_cs: qup-spi4-cs-state {
+ pins = "gpio15";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ pins = "gpio130", "gpio131";
+ function = "qup05";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
+ pins = "gpio130", "gpio131", "gpio132";
+ function = "qup05";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio133";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ pins = "gpio132", "gpio133";
+ function = "qup06";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ pins = "gpio132", "gpio133", "gpio130";
+ function = "qup06";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio131";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart7_rx: qup-uart7-rx-state {
+ pins = "gpio135";
+ function = "qup07";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart7_tx: qup-uart7-tx-state {
+ pins = "gpio134";
+ function = "qup07";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart8_default: qup-uart8-default-state {
+ pins = "gpio18", "gpio19", "gpio20", "gpio21";
+ function = "qup10";
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+ pins = "gpio22", "gpio23";
+ function = "qup11";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk-state {
+ pins = "gpio22", "gpio23", "gpio24";
+ function = "qup11";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_cs: qup-spi9-cs-state {
+ pins = "gpio25";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+ pins = "gpio24", "gpio25";
+ function = "qup12";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk-state {
+ pins = "gpio24", "gpio25", "gpio22";
+ function = "qup12";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_cs: qup-spi10-cs-state {
+ pins = "gpio23";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+ pins = "gpio26", "gpio27";
+ function = "qup13";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk-state {
+ pins = "gpio26", "gpio27", "gpio28";
+ function = "qup13";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_cs: qup-spi11-cs-state {
+ pins = "gpio29";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c12_data_clk: qup-i2c12-data-clk-state {
+ pins = "gpio28", "gpio29";
+ function = "qup14";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi12_data_clk: qup-spi12-data-clk-state {
+ pins = "gpio28", "gpio29", "gpio26";
+ function = "qup14";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi12_cs: qup-spi12-cs-state {
+ pins = "gpio27";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c13_data_clk: qup-i2c13-data-clk-state {
+ pins = "gpio30", "gpio31";
+ function = "qup15";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi13_data_clk: qup-spi13-data-clk-state {
+ pins = "gpio30", "gpio31", "gpio32";
+ function = "qup15";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi13_cs: qup-spi13-cs-state {
+ pins = "gpio33";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart13_default: qup-uart13-default-state {
+ pins = "gpio30", "gpio31", "gpio32", "gpio33";
+ function = "qup15";
+ };
+
+ qup_i2c14_data_clk: qup-i2c14-data-clk-state {
+ pins = "gpio34", "gpio35";
+ function = "qup16";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi14_data_clk: qup-spi14-data-clk-state {
+ pins = "gpio34", "gpio35", "gpio36";
+ function = "qup16";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi14_cs: qup-spi14-cs-state {
+ pins = "gpio37", "gpio38";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c15_data_clk: qup-i2c15-data-clk-state {
+ pins = "gpio40", "gpio41";
+ function = "qup17";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi15_data_clk: qup-spi15-data-clk-state {
+ pins = "gpio40", "gpio41", "gpio30";
+ function = "qup17";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi15_cs: qup-spi15-cs-state {
+ pins = "gpio31";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,qdu1000-smmu-500", "arm,mmu-500";
+ reg = <0x0 0x15000000 0x0 0x100000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ intc: interrupt-controller@17200000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
+ <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ timer@17420000 {
+ compatible = "arm,armv7-timer-mem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = <0x0 0x17420000 0x0 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@17421000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17421000 0x1000>,
+ <0x17422000 0x1000>;
+ };
+
+ frame@17423000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17423000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17425000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17425000 0x1000>,
+ <0x17426000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17427000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17427000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17429000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17429000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@1742b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x1742b000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@1742d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x1742d000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@17a00000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x17a00000 0x0 0x10000>,
+ <0x0 0x17a10000 0x0 0x10000>,
+ <0x0 0x17a20000 0x0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
+ <WAKE_TCS 3>, <CONTROL_TCS 0>;
+ label = "apps_rsc";
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,qdu1000-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,qdu1000-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp10 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+ };
+
+ cpufreq_hw: cpufreq@17d90000 {
+ compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
+ reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #freq-domain-cells = <1>;
+ };
+
+ gem_noc: interconnect@19100000 {
+ reg = <0x0 0x19100000 0x0 0xB8080>;
+ compatible = "qcom,qdu1000-gem-noc";
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+ };
+
+ arch_timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <19200000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi
new file mode 100644
index 000000000000..074fe126e85e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "qdu1000.dtsi"
+
+&reserved_memory {
+ /delete-node/ memory@a0000000;
+ /delete-node/ memory@b9600000;
+ /delete-node/ memory@c0000000;
+
+ oem_tenx_mem: memory@a0000000 {
+ no-map;
+ reg = <0x0 0xa0000000 0x0 0x6400000>;
+ };
+
+ mpss_diag_buffer_mem: memory@aea00000 {
+ no-map;
+ reg = <0x0 0xaea00000 0x0 0x6400000>;
+ };
+
+ tenx_q6_buffer_mem: memory@b4e00000 {
+ no-map;
+ reg = <0x0 0xb4e00000 0x0 0x3200000>;
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 4/4] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs
2022-10-26 20:04 [PATCH v3 0/4] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (2 preceding siblings ...)
2022-10-26 20:04 ` [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera
@ 2022-10-26 20:04 ` Melody Olvera
2022-10-27 15:23 ` Krzysztof Kozlowski
2022-11-08 1:27 ` (subset) [PATCH v3 0/4] Add base device tree files for QDU1000/QRU1000 Bjorn Andersson
4 siblings, 1 reply; 21+ messages in thread
From: Melody Olvera @ 2022-10-26 20:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000
SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/Makefile | 2 +
arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 245 +++++++++++++++++++++++
arch/arm64/boot/dts/qcom/qru1000-idp.dts | 245 +++++++++++++++++++++++
3 files changed, 492 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index b0558d3389e5..8ee949a58ce7 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -51,7 +51,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
new file mode 100644
index 000000000000..e4fd6e2b656b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qdu1000.dtsi"
+#include "pm8150.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QDU1000 IDP";
+ compatible = "qcom,qdu1000-idp", "qcom,qdu1000";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ clock-output-names = "xo_board";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ ppvar_sys: ppvar-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "ppvar_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&ppvar_sys>;
+ };
+};
+
+&apps_rsc {
+ regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
+ vdd-l2-l10-supply = <&vph_pwr>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>;
+ vdd-l6-l9-supply = <&vreg_s6a_0p9>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>;
+ vdd-l13-l16-l17-supply = <&vph_pwr>;
+
+ vreg_s2a_0p5: smps2 {
+ regulator-name = "vreg_s2a_0p5";
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <570000>;
+ };
+
+ vreg_s3a_1p05: smps3 {
+ regulator-name = "vreg_s3a_1p05";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1170000>;
+ };
+
+ vreg_s4a_1p8: smps4 {
+ regulator-name = "vreg_s4a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_s5a_2p0: smps5 {
+ regulator-name = "vreg_s5a_2p0";
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6a_0p9: smps6 {
+ regulator-name = "vreg_s6a_0p9";
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vreg_s7a_1p2: smps7 {
+ regulator-name = "vreg_s7a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_s8a_1p3: smps8 {
+ regulator-name = "vreg_s8a_1p3";
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_l1a_0p91: ldo1 {
+ regulator-name = "vreg_l1a_0p91";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l2a_2p3: ldo2 {
+ regulator-name = "vreg_l2a_2p3";
+ regulator-min-microvolt = <2970000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l3a_1p2: ldo3 {
+ regulator-name = "vreg_l3a_1p2";
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l5a_0p8: ldo5 {
+ regulator-name = "vreg_l5a_0p8";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l6a_0p91: ldo6 {
+ regulator-name = "vreg_l6a_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-name = "vreg_l7a_1p8";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+
+ };
+
+ vreg_l8a_0p91: ldo8 {
+ regulator-name = "vreg_l8a_0p91";
+ regulator-min-microvolt = <888000>;
+ regulator-max-microvolt = <925000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l9a_0p91: ldo9 {
+ regulator-name = "vreg_l8a_0p91";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l10a_2p95: ldo10 {
+ regulator-name = "vreg_l10a_2p95";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l11a_0p91: ldo11 {
+ regulator-name = "vreg_l11a_0p91";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-name = "vreg_l14a_1p8";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l15a_1p8: ldo15 {
+ regulator-name = "vreg_l15a_1p8";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l16a_1p8: ldo16 {
+ regulator-name = "vreg_l16a_1p8";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1890000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l17a_3p3: ldo17 {
+ regulator-name = "vreg_l17a_3p3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l18a_1p2: ldo18 {
+ regulator-name = "vreg_l18a_1p2";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&uart7 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
new file mode 100644
index 000000000000..445124e84485
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qru1000.dtsi"
+#include "pm8150.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QRU1000 IDP";
+ compatible = "qcom,qru1000-idp", "qcom,qru1000";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ clock-output-names = "xo_board";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ ppvar_sys: ppvar-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "ppvar_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&ppvar_sys>;
+ };
+};
+
+&apps_rsc {
+ regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
+ vdd-l2-l10-supply = <&vph_pwr>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>;
+ vdd-l6-l9-supply = <&vreg_s6a_0p9>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>;
+ vdd-l13-l16-l17-supply = <&vph_pwr>;
+
+ vreg_s2a_0p5: smps2 {
+ regulator-name = "vreg_s2a_0p5";
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <570000>;
+ };
+
+ vreg_s3a_1p05: smps3 {
+ regulator-name = "vreg_s3a_1p05";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1170000>;
+ };
+
+ vreg_s4a_1p8: smps4 {
+ regulator-name = "vreg_s4a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_s5a_2p0: smps5 {
+ regulator-name = "vreg_s5a_2p0";
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6a_0p9: smps6 {
+ regulator-name = "vreg_s6a_0p9";
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vreg_s7a_1p2: smps7 {
+ regulator-name = "vreg_s7a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_s8a_1p3: smps8 {
+ regulator-name = "vreg_s8a_1p3";
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_l1a_0p91: ldo1 {
+ regulator-name = "vreg_l1a_0p91";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l2a_2p3: ldo2 {
+ regulator-name = "vreg_l2a_2p3";
+ regulator-min-microvolt = <2970000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l3a_1p2: ldo3 {
+ regulator-name = "vreg_l3a_1p2";
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l5a_0p8: ldo5 {
+ regulator-name = "vreg_l5a_0p8";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l6a_0p91: ldo6 {
+ regulator-name = "vreg_l6a_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-name = "vreg_l7a_1p8";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+
+ };
+
+ vreg_l8a_0p91: ldo8 {
+ regulator-name = "vreg_l8a_0p91";
+ regulator-min-microvolt = <888000>;
+ regulator-max-microvolt = <925000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l9a_0p91: ldo9 {
+ regulator-name = "vreg_l8a_0p91";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l10a_2p95: ldo10 {
+ regulator-name = "vreg_l10a_2p95";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l11a_0p91: ldo11 {
+ regulator-name = "vreg_l11a_0p91";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-name = "vreg_l14a_1p8";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l15a_1p8: ldo15 {
+ regulator-name = "vreg_l15a_1p8";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l16a_1p8: ldo16 {
+ regulator-name = "vreg_l16a_1p8";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1890000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l17a_3p3: ldo17 {
+ regulator-name = "vreg_l17a_3p3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l18a_1p2: ldo18 {
+ regulator-name = "vreg_l18a_1p2";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&uart7 {
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes
2022-10-26 20:04 ` [PATCH v3 1/4] dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes Melody Olvera
@ 2022-10-27 15:08 ` Krzysztof Kozlowski
2022-11-08 21:34 ` Melody Olvera
0 siblings, 1 reply; 21+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-27 15:08 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 26/10/2022 16:04, Melody Olvera wrote:
> Update the bindings to allow for generic regulator nodes instead of
> device-specific node names.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
> index 4a50f1d27724..0e7e07975f3a 100644
> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
> @@ -109,7 +109,7 @@ properties:
> $ref: /schemas/power/qcom,rpmpd.yaml#
>
> patternProperties:
> - '-regulators$':
> + 'regulators$':
This should be rather fixed like:
https://lore.kernel.org/linux-devicetree/20220926092104.111449-1-krzysztof.kozlowski@linaro.org/
I don't know why there is such a popularity of adding specific model
names as device node names...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/4] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards
2022-10-26 20:04 ` [PATCH v3 2/4] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards Melody Olvera
@ 2022-10-27 15:15 ` Krzysztof Kozlowski
0 siblings, 0 replies; 21+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-27 15:15 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 26/10/2022 16:04, Melody Olvera wrote:
> Document the QDU1000 and QRU1000 SoC bindings and the boards that use
> them.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-10-26 20:04 ` [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera
@ 2022-10-27 15:21 ` Krzysztof Kozlowski
2022-10-31 21:49 ` Melody Olvera
0 siblings, 1 reply; 21+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-27 15:21 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 26/10/2022 16:04, Melody Olvera wrote:
> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller
> to boot to shell with console on these SoCs.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++++++++++
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.
> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 +
> 2 files changed, 1433 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> new file mode 100644
> index 000000000000..76474106e931
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> @@ -0,0 +1,1406 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
(...)
> +
> + soc: soc@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0 0x10 0>;
> + dma-ranges = <0 0 0 0 0x10 0>;
> + compatible = "simple-bus";
> +
> + gcc: clock-controller@80000 {
> + compatible = "qcom,gcc-qdu1000", "syscon";
> + reg = <0x0 0x80000 0x0 0x1f4200>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
> + clock-names = "bi_tcxo", "sleep_clk";
> + };
> +
> + gpi_dma0: dma-controller@900000 {
> + compatible = "qcom,sm6350-gpi-dma";
You should add here a specific compatible as well. Same in other places.
All places. I had impression we talked about this few times, so I don't
know what is missing on your side.
This must be:
"qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"
> + #dma-cells = <3>;
> + reg = <0x0 0x900000 0x0 0x60000>;
> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
> + dma-channels = <12>;
> + dma-channel-mask = <0x3f>;
> + iommus = <&apps_smmu 0xf6 0x0>;
> + };
> +
(...)
> +
> + tlmm: pinctrl@f000000 {
> + compatible = "qcom,qdu1000-tlmm";
> + reg = <0x0 0xf000000 0x0 0x1000000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 151>;
> + wakeup-parent = <&pdc>;
> +
> + qup_uart0_default: qup-uart0-default-state {
> + pins = "gpio6", "gpio7", "gpio8", "gpio9";
> + function = "qup00";
> + };
> +
> + qup_i2c1_data_clk: qup-i2c1-data-clk-state {
> + pins = "gpio10", "gpio11";
> + function = "qup01";
> + drive-strength = <2>;
Can we have some generic agreement where to put drive-strengths and bias?
See also:
https://lore.kernel.org/linux-devicetree/20221026200357.391635-2-krzysztof.kozlowski@linaro.org/
https://lore.kernel.org/lkml/CAD=FV=VUL4GmjaibAMhKNdpEso_Hg_R=XeMaqah1LSj_9-Ce4Q@mail.gmail.com/
> + bias-pull-up;
> + };
(...)
> + };
> +
> + cpufreq_hw: cpufreq@17d90000 {
> + compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
This is not sm8250...
> + reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>;
> + reg-names = "freq-domain0", "freq-domain1";
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> + clock-names = "xo", "alternate";
> + #freq-domain-cells = <1>;
> + };
> +
> + gem_noc: interconnect@19100000 {
> + reg = <0x0 0x19100000 0x0 0xB8080>;
> + compatible = "qcom,qdu1000-gem-noc";
> + #interconnect-cells = <1>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> + };
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 4/4] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs
2022-10-26 20:04 ` [PATCH v3 4/4] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera
@ 2022-10-27 15:23 ` Krzysztof Kozlowski
0 siblings, 0 replies; 21+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-27 15:23 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 26/10/2022 16:04, Melody Olvera wrote:
> Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000
> SoCs.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 2 +
> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 245 +++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qru1000-idp.dts | 245 +++++++++++++++++++++++
> 3 files changed, 492 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index b0558d3389e5..8ee949a58ce7 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -51,7 +51,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> new file mode 100644
> index 000000000000..e4fd6e2b656b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> @@ -0,0 +1,245 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include "qdu1000.dtsi"
> +#include "pm8150.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. QDU1000 IDP";
> + compatible = "qcom,qdu1000-idp", "qcom,qdu1000";
> +
> + aliases {
> + serial0 = &uart7;
> + };
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + clock-frequency = <19200000>;
> + clock-output-names = "xo_board";
> + #clock-cells = <0>;
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + #clock-cells = <0>;
> + };
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + ppvar_sys: ppvar-sys-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "ppvar_sys";
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vph_pwr: vph-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&ppvar_sys>;
> + };
> +};
> +
> +&apps_rsc {
> + regulators {
> + compatible = "qcom,pm8150-rpmh-regulators";
> + qcom,pmic-id = "a";
> +
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-supply = <&vph_pwr>;
> + vdd-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> + vdd-s6-supply = <&vph_pwr>;
> + vdd-s7-supply = <&vph_pwr>;
> + vdd-s8-supply = <&vph_pwr>;
> + vdd-s9-supply = <&vph_pwr>;
> + vdd-s10-supply = <&vph_pwr>;
> +
> + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
> + vdd-l2-l10-supply = <&vph_pwr>;
> + vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>;
> + vdd-l6-l9-supply = <&vreg_s6a_0p9>;
> + vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>;
> + vdd-l13-l16-l17-supply = <&vph_pwr>;
> +
> + vreg_s2a_0p5: smps2 {
> + regulator-name = "vreg_s2a_0p5";
> + regulator-min-microvolt = <320000>;
> + regulator-max-microvolt = <570000>;
> + };
> +
> + vreg_s3a_1p05: smps3 {
> + regulator-name = "vreg_s3a_1p05";
> + regulator-min-microvolt = <950000>;
> + regulator-max-microvolt = <1170000>;
> + };
> +
> + vreg_s4a_1p8: smps4 {
> + regulator-name = "vreg_s4a_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + vreg_s5a_2p0: smps5 {
> + regulator-name = "vreg_s5a_2p0";
> + regulator-min-microvolt = <1904000>;
> + regulator-max-microvolt = <2000000>;
> + };
> +
> + vreg_s6a_0p9: smps6 {
> + regulator-name = "vreg_s6a_0p9";
> + regulator-min-microvolt = <920000>;
> + regulator-max-microvolt = <1128000>;
> + };
> +
> + vreg_s7a_1p2: smps7 {
> + regulator-name = "vreg_s7a_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + vreg_s8a_1p3: smps8 {
> + regulator-name = "vreg_s8a_1p3";
> + regulator-min-microvolt = <1352000>;
> + regulator-max-microvolt = <1352000>;
> + };
> +
> + vreg_l1a_0p91: ldo1 {
> + regulator-name = "vreg_l1a_0p91";
> + regulator-min-microvolt = <312000>;
> + regulator-max-microvolt = <1304000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l2a_2p3: ldo2 {
> + regulator-name = "vreg_l2a_2p3";
> + regulator-min-microvolt = <2970000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l3a_1p2: ldo3 {
> + regulator-name = "vreg_l3a_1p2";
> + regulator-min-microvolt = <920000>;
> + regulator-max-microvolt = <1260000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l5a_0p8: ldo5 {
> + regulator-name = "vreg_l5a_0p8";
> + regulator-min-microvolt = <312000>;
> + regulator-max-microvolt = <1304000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l6a_0p91: ldo6 {
> + regulator-name = "vreg_l6a_0p91";
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <950000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l7a_1p8: ldo7 {
> + regulator-name = "vreg_l7a_1p8";
> + regulator-min-microvolt = <1650000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> +
> + };
> +
> + vreg_l8a_0p91: ldo8 {
> + regulator-name = "vreg_l8a_0p91";
> + regulator-min-microvolt = <888000>;
> + regulator-max-microvolt = <925000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l9a_0p91: ldo9 {
> + regulator-name = "vreg_l8a_0p91";
> + regulator-min-microvolt = <312000>;
> + regulator-max-microvolt = <1304000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l10a_2p95: ldo10 {
> + regulator-name = "vreg_l10a_2p95";
> + regulator-min-microvolt = <2700000>;
> + regulator-max-microvolt = <3544000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l11a_0p91: ldo11 {
> + regulator-name = "vreg_l11a_0p91";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l12a_1p8: ldo12 {
> + regulator-name = "vreg_l12a_1p8";
> + regulator-min-microvolt = <1504000>;
> + regulator-max-microvolt = <1504000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l14a_1p8: ldo14 {
> + regulator-name = "vreg_l14a_1p8";
> + regulator-min-microvolt = <1650000>;
> + regulator-max-microvolt = <1950000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l15a_1p8: ldo15 {
> + regulator-name = "vreg_l15a_1p8";
> + regulator-min-microvolt = <1504000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l16a_1p8: ldo16 {
> + regulator-name = "vreg_l16a_1p8";
> + regulator-min-microvolt = <1710000>;
> + regulator-max-microvolt = <1890000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l17a_3p3: ldo17 {
> + regulator-name = "vreg_l17a_3p3";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3544000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l18a_1p2: ldo18 {
> + regulator-name = "vreg_l18a_1p2";
> + regulator-min-microvolt = <312000>;
> + regulator-max-microvolt = <1304000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> + };
> +};
> +
> +&qupv3_id_0 {
> + status = "okay";
> +};
> +
> +&uart7 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
> new file mode 100644
> index 000000000000..445124e84485
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
> @@ -0,0 +1,245 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include "qru1000.dtsi"
> +#include "pm8150.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. QRU1000 IDP";
> + compatible = "qcom,qru1000-idp", "qcom,qru1000";
> +
> + aliases {
> + serial0 = &uart7;
> + };
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + clock-frequency = <19200000>;
> + clock-output-names = "xo_board";
> + #clock-cells = <0>;
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + #clock-cells = <0>;
> + };
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + ppvar_sys: ppvar-sys-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "ppvar_sys";
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vph_pwr: vph-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&ppvar_sys>;
> + };
> +};
> +
> +&apps_rsc {
> + regulators {
> + compatible = "qcom,pm8150-rpmh-regulators";
> + qcom,pmic-id = "a";
> +
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-supply = <&vph_pwr>;
> + vdd-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> + vdd-s6-supply = <&vph_pwr>;
> + vdd-s7-supply = <&vph_pwr>;
> + vdd-s8-supply = <&vph_pwr>;
> + vdd-s9-supply = <&vph_pwr>;
> + vdd-s10-supply = <&vph_pwr>;
> +
> + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
> + vdd-l2-l10-supply = <&vph_pwr>;
> + vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>;
> + vdd-l6-l9-supply = <&vreg_s6a_0p9>;
> + vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>;
> + vdd-l13-l16-l17-supply = <&vph_pwr>;
> +
> + vreg_s2a_0p5: smps2 {
> + regulator-name = "vreg_s2a_0p5";
> + regulator-min-microvolt = <320000>;
> + regulator-max-microvolt = <570000>;
> + };
> +
> + vreg_s3a_1p05: smps3 {
> + regulator-name = "vreg_s3a_1p05";
> + regulator-min-microvolt = <950000>;
> + regulator-max-microvolt = <1170000>;
> + };
> +
> + vreg_s4a_1p8: smps4 {
> + regulator-name = "vreg_s4a_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + vreg_s5a_2p0: smps5 {
> + regulator-name = "vreg_s5a_2p0";
> + regulator-min-microvolt = <1904000>;
> + regulator-max-microvolt = <2000000>;
> + };
> +
> + vreg_s6a_0p9: smps6 {
> + regulator-name = "vreg_s6a_0p9";
> + regulator-min-microvolt = <920000>;
> + regulator-max-microvolt = <1128000>;
> + };
> +
> + vreg_s7a_1p2: smps7 {
> + regulator-name = "vreg_s7a_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + vreg_s8a_1p3: smps8 {
> + regulator-name = "vreg_s8a_1p3";
> + regulator-min-microvolt = <1352000>;
> + regulator-max-microvolt = <1352000>;
> + };
> +
> + vreg_l1a_0p91: ldo1 {
> + regulator-name = "vreg_l1a_0p91";
> + regulator-min-microvolt = <312000>;
> + regulator-max-microvolt = <1304000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l2a_2p3: ldo2 {
> + regulator-name = "vreg_l2a_2p3";
> + regulator-min-microvolt = <2970000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l3a_1p2: ldo3 {
> + regulator-name = "vreg_l3a_1p2";
> + regulator-min-microvolt = <920000>;
> + regulator-max-microvolt = <1260000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l5a_0p8: ldo5 {
> + regulator-name = "vreg_l5a_0p8";
> + regulator-min-microvolt = <312000>;
> + regulator-max-microvolt = <1304000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l6a_0p91: ldo6 {
> + regulator-name = "vreg_l6a_0p91";
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <950000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l7a_1p8: ldo7 {
> + regulator-name = "vreg_l7a_1p8";
> + regulator-min-microvolt = <1650000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> +
> + };
> +
> + vreg_l8a_0p91: ldo8 {
> + regulator-name = "vreg_l8a_0p91";
> + regulator-min-microvolt = <888000>;
> + regulator-max-microvolt = <925000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l9a_0p91: ldo9 {
> + regulator-name = "vreg_l8a_0p91";
> + regulator-min-microvolt = <312000>;
> + regulator-max-microvolt = <1304000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l10a_2p95: ldo10 {
> + regulator-name = "vreg_l10a_2p95";
> + regulator-min-microvolt = <2700000>;
> + regulator-max-microvolt = <3544000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l11a_0p91: ldo11 {
> + regulator-name = "vreg_l11a_0p91";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l12a_1p8: ldo12 {
> + regulator-name = "vreg_l12a_1p8";
> + regulator-min-microvolt = <1504000>;
> + regulator-max-microvolt = <1504000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l14a_1p8: ldo14 {
> + regulator-name = "vreg_l14a_1p8";
> + regulator-min-microvolt = <1650000>;
> + regulator-max-microvolt = <1950000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l15a_1p8: ldo15 {
> + regulator-name = "vreg_l15a_1p8";
> + regulator-min-microvolt = <1504000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l16a_1p8: ldo16 {
> + regulator-name = "vreg_l16a_1p8";
> + regulator-min-microvolt = <1710000>;
> + regulator-max-microvolt = <1890000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l17a_3p3: ldo17 {
> + regulator-name = "vreg_l17a_3p3";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3544000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> +
> + vreg_l18a_1p2: ldo18 {
> + regulator-name = "vreg_l18a_1p2";
> + regulator-min-microvolt = <312000>;
> + regulator-max-microvolt = <1304000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + };
> + };
> +};
> +
> +&qupv3_id_0 {
> + status = "okay";
> +};
> +
> +&uart7 {
> + status = "okay";
> +};
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-10-27 15:21 ` Krzysztof Kozlowski
@ 2022-10-31 21:49 ` Melody Olvera
2022-10-31 23:25 ` Melody Olvera
2022-11-02 16:24 ` Krzysztof Kozlowski
0 siblings, 2 replies; 21+ messages in thread
From: Melody Olvera @ 2022-10-31 21:49 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/27/2022 8:21 AM, Krzysztof Kozlowski wrote:
> On 26/10/2022 16:04, Melody Olvera wrote:
>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller
>> to boot to shell with console on these SoCs.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++++++++++
> Please use scripts/get_maintainers.pl to get a list of necessary people
> and lists to CC. It might happen, that command when run on an older
> kernel, gives you outdated entries. Therefore please be sure you base
> your patches on recent Linux kernel.
Sure thing; we talked about this on a different patch.
>
>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 +
>> 2 files changed, 1433 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> new file mode 100644
>> index 000000000000..76474106e931
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> @@ -0,0 +1,1406 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
> (...)
>
>> +
>> + soc: soc@0 {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0 0 0 0 0x10 0>;
>> + dma-ranges = <0 0 0 0 0x10 0>;
>> + compatible = "simple-bus";
>> +
>> + gcc: clock-controller@80000 {
>> + compatible = "qcom,gcc-qdu1000", "syscon";
>> + reg = <0x0 0x80000 0x0 0x1f4200>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
>> + clock-names = "bi_tcxo", "sleep_clk";
>> + };
>> +
>> + gpi_dma0: dma-controller@900000 {
>> + compatible = "qcom,sm6350-gpi-dma";
> You should add here a specific compatible as well. Same in other places.
> All places. I had impression we talked about this few times, so I don't
> know what is missing on your side.
>
> This must be:
> "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"
Got it. I talked to Stephan and he said either your suggestion or just using
preexisting compatibles would be ok. I thought it might be cleaner to not
have the qdu compats, but I'm fine either way.
>
>> + #dma-cells = <3>;
>> + reg = <0x0 0x900000 0x0 0x60000>;
>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-channels = <12>;
>> + dma-channel-mask = <0x3f>;
>> + iommus = <&apps_smmu 0xf6 0x0>;
>> + };
>> +
> (...)
>
>
>> +
>> + tlmm: pinctrl@f000000 {
>> + compatible = "qcom,qdu1000-tlmm";
>> + reg = <0x0 0xf000000 0x0 0x1000000>;
>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + gpio-ranges = <&tlmm 0 0 151>;
>> + wakeup-parent = <&pdc>;
>> +
>> + qup_uart0_default: qup-uart0-default-state {
>> + pins = "gpio6", "gpio7", "gpio8", "gpio9";
>> + function = "qup00";
>> + };
>> +
>> + qup_i2c1_data_clk: qup-i2c1-data-clk-state {
>> + pins = "gpio10", "gpio11";
>> + function = "qup01";
>> + drive-strength = <2>;
> Can we have some generic agreement where to put drive-strengths and bias?
>
> See also:
> https://lore.kernel.org/linux-devicetree/20221026200357.391635-2-krzysztof.kozlowski@linaro.org/
>
> https://lore.kernel.org/lkml/CAD=FV=VUL4GmjaibAMhKNdpEso_Hg_R=XeMaqah1LSj_9-Ce4Q@mail.gmail.com/
Not sure how much two-sense I have for the conversation at large, but generally I agree with Doug's
point in the first paragraph. Pulls for this soc are consistent across boards so I don't think it makes
sense to move them to the board files here. I vote that these stay here.
>
>> + bias-pull-up;
>> + };
> (...)
>
>> + };
>> +
>> + cpufreq_hw: cpufreq@17d90000 {
>> + compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
> This is not sm8250...
Ack.
>
>> + reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>;
>> + reg-names = "freq-domain0", "freq-domain1";
>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
>> + clock-names = "xo", "alternate";
>> + #freq-domain-cells = <1>;
>> + };
>> +
>> + gem_noc: interconnect@19100000 {
>> + reg = <0x0 0x19100000 0x0 0xB8080>;
>> + compatible = "qcom,qdu1000-gem-noc";
>> + #interconnect-cells = <1>;
>> + qcom,bcm-voters = <&apps_bcm_voter>;
>> + };
>> + };
Thanks,
Melody
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-10-31 21:49 ` Melody Olvera
@ 2022-10-31 23:25 ` Melody Olvera
2022-11-02 16:25 ` Krzysztof Kozlowski
2022-11-02 16:24 ` Krzysztof Kozlowski
1 sibling, 1 reply; 21+ messages in thread
From: Melody Olvera @ 2022-10-31 23:25 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/31/2022 2:49 PM, Melody Olvera wrote:
>
> On 10/27/2022 8:21 AM, Krzysztof Kozlowski wrote:
>> On 26/10/2022 16:04, Melody Olvera wrote:
>>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
>>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller
>>> to boot to shell with console on these SoCs.
>>>
>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++++++++++
>> Please use scripts/get_maintainers.pl to get a list of necessary people
>> and lists to CC. It might happen, that command when run on an older
>> kernel, gives you outdated entries. Therefore please be sure you base
>> your patches on recent Linux kernel.
> Sure thing; we talked about this on a different patch.
>>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 +
>>> 2 files changed, 1433 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>> new file mode 100644
>>> index 000000000000..76474106e931
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>> @@ -0,0 +1,1406 @@
>>> +// SPDX-License-Identifier: BSD-3-Clause
>>> +/*
>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>>> + */
>> (...)
>>
>>> +
>>> + soc: soc@0 {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + ranges = <0 0 0 0 0x10 0>;
>>> + dma-ranges = <0 0 0 0 0x10 0>;
>>> + compatible = "simple-bus";
>>> +
>>> + gcc: clock-controller@80000 {
>>> + compatible = "qcom,gcc-qdu1000", "syscon";
>>> + reg = <0x0 0x80000 0x0 0x1f4200>;
>>> + #clock-cells = <1>;
>>> + #reset-cells = <1>;
>>> + #power-domain-cells = <1>;
>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
>>> + clock-names = "bi_tcxo", "sleep_clk";
>>> + };
>>> +
>>> + gpi_dma0: dma-controller@900000 {
>>> + compatible = "qcom,sm6350-gpi-dma";
>> You should add here a specific compatible as well. Same in other places.
>> All places. I had impression we talked about this few times, so I don't
>> know what is missing on your side.
>>
>> This must be:
>> "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"
> Got it. I talked to Stephan and he said either your suggestion or just using
> preexisting compatibles would be ok. I thought it might be cleaner to not
> have the qdu compats, but I'm fine either way.
Coming back to this, it looks like this will fail dtb_check since compatible field is too long.
Is there an adjustment to the binding which needs to be made here?
>>> + #dma-cells = <3>;
>>> + reg = <0x0 0x900000 0x0 0x60000>;
>>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
>>> + dma-channels = <12>;
>>> + dma-channel-mask = <0x3f>;
>>> + iommus = <&apps_smmu 0xf6 0x0>;
>>> + };
>>> +
>> (...)
>>
>>
>>> +
>>> + tlmm: pinctrl@f000000 {
>>> + compatible = "qcom,qdu1000-tlmm";
>>> + reg = <0x0 0xf000000 0x0 0x1000000>;
>>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>> + gpio-controller;
>>> + #gpio-cells = <2>;
>>> + interrupt-controller;
>>> + #interrupt-cells = <2>;
>>> + gpio-ranges = <&tlmm 0 0 151>;
>>> + wakeup-parent = <&pdc>;
>>> +
>>> + qup_uart0_default: qup-uart0-default-state {
>>> + pins = "gpio6", "gpio7", "gpio8", "gpio9";
>>> + function = "qup00";
>>> + };
>>> +
>>> + qup_i2c1_data_clk: qup-i2c1-data-clk-state {
>>> + pins = "gpio10", "gpio11";
>>> + function = "qup01";
>>> + drive-strength = <2>;
>> Can we have some generic agreement where to put drive-strengths and bias?
>>
>> See also:
>> https://lore.kernel.org/linux-devicetree/20221026200357.391635-2-krzysztof.kozlowski@linaro.org/
>>
>> https://lore.kernel.org/lkml/CAD=FV=VUL4GmjaibAMhKNdpEso_Hg_R=XeMaqah1LSj_9-Ce4Q@mail.gmail.com/
> Not sure how much two-sense I have for the conversation at large, but generally I agree with Doug's
> point in the first paragraph. Pulls for this soc are consistent across boards so I don't think it makes
> sense to move them to the board files here. I vote that these stay here.
>>> + bias-pull-up;
>>> + };
>> (...)
>>
>>> + };
>>> +
>>> + cpufreq_hw: cpufreq@17d90000 {
>>> + compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
>> This is not sm8250...
> Ack.
>>> + reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>;
>>> + reg-names = "freq-domain0", "freq-domain1";
>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
>>> + clock-names = "xo", "alternate";
>>> + #freq-domain-cells = <1>;
>>> + };
>>> +
>>> + gem_noc: interconnect@19100000 {
>>> + reg = <0x0 0x19100000 0x0 0xB8080>;
>>> + compatible = "qcom,qdu1000-gem-noc";
>>> + #interconnect-cells = <1>;
>>> + qcom,bcm-voters = <&apps_bcm_voter>;
>>> + };
>>> + };
>>>
Thanks,
Melody
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-10-31 21:49 ` Melody Olvera
2022-10-31 23:25 ` Melody Olvera
@ 2022-11-02 16:24 ` Krzysztof Kozlowski
2022-11-03 21:13 ` Melody Olvera
1 sibling, 1 reply; 21+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 16:24 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 31/10/2022 17:49, Melody Olvera wrote:
>
>
> On 10/27/2022 8:21 AM, Krzysztof Kozlowski wrote:
>> On 26/10/2022 16:04, Melody Olvera wrote:
>>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
>>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller
>>> to boot to shell with console on these SoCs.
>>>
>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++++++++++
>> Please use scripts/get_maintainers.pl to get a list of necessary people
>> and lists to CC. It might happen, that command when run on an older
>> kernel, gives you outdated entries. Therefore please be sure you base
>> your patches on recent Linux kernel.
> Sure thing; we talked about this on a different patch.
>>
>>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 +
>>> 2 files changed, 1433 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>> new file mode 100644
>>> index 000000000000..76474106e931
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>> @@ -0,0 +1,1406 @@
>>> +// SPDX-License-Identifier: BSD-3-Clause
>>> +/*
>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>>> + */
>> (...)
>>
>>> +
>>> + soc: soc@0 {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + ranges = <0 0 0 0 0x10 0>;
>>> + dma-ranges = <0 0 0 0 0x10 0>;
>>> + compatible = "simple-bus";
>>> +
>>> + gcc: clock-controller@80000 {
>>> + compatible = "qcom,gcc-qdu1000", "syscon";
>>> + reg = <0x0 0x80000 0x0 0x1f4200>;
>>> + #clock-cells = <1>;
>>> + #reset-cells = <1>;
>>> + #power-domain-cells = <1>;
>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
>>> + clock-names = "bi_tcxo", "sleep_clk";
>>> + };
>>> +
>>> + gpi_dma0: dma-controller@900000 {
>>> + compatible = "qcom,sm6350-gpi-dma";
>> You should add here a specific compatible as well. Same in other places.
>> All places. I had impression we talked about this few times, so I don't
>> know what is missing on your side.
>>
>> This must be:
>> "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"
> Got it. I talked to Stephan and he said either your suggestion or just using
> preexisting compatibles would be ok. I thought it might be cleaner to not
> have the qdu compats, but I'm fine either way.
>>
>>> + #dma-cells = <3>;
>>> + reg = <0x0 0x900000 0x0 0x60000>;
>>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
>>> + dma-channels = <12>;
>>> + dma-channel-mask = <0x3f>;
>>> + iommus = <&apps_smmu 0xf6 0x0>;
>>> + };
>>> +
>> (...)
>>
>>
>>> +
>>> + tlmm: pinctrl@f000000 {
>>> + compatible = "qcom,qdu1000-tlmm";
>>> + reg = <0x0 0xf000000 0x0 0x1000000>;
>>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>> + gpio-controller;
>>> + #gpio-cells = <2>;
>>> + interrupt-controller;
>>> + #interrupt-cells = <2>;
>>> + gpio-ranges = <&tlmm 0 0 151>;
>>> + wakeup-parent = <&pdc>;
>>> +
>>> + qup_uart0_default: qup-uart0-default-state {
>>> + pins = "gpio6", "gpio7", "gpio8", "gpio9";
>>> + function = "qup00";
>>> + };
>>> +
>>> + qup_i2c1_data_clk: qup-i2c1-data-clk-state {
>>> + pins = "gpio10", "gpio11";
>>> + function = "qup01";
>>> + drive-strength = <2>;
>> Can we have some generic agreement where to put drive-strengths and bias?
>>
>> See also:
>> https://lore.kernel.org/linux-devicetree/20221026200357.391635-2-krzysztof.kozlowski@linaro.org/
>>
>> https://lore.kernel.org/lkml/CAD=FV=VUL4GmjaibAMhKNdpEso_Hg_R=XeMaqah1LSj_9-Ce4Q@mail.gmail.com/
> Not sure how much two-sense I have for the conversation at large, but generally I agree with Doug's
> point in the first paragraph. Pulls for this soc are consistent across boards so I don't think it makes
> sense to move them to the board files here. I vote that these stay here.
>>
I would be great if Konrad and Bjorn shared their opinion on this... but
wait, you did not Cc all maintainers... Eh.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-10-31 23:25 ` Melody Olvera
@ 2022-11-02 16:25 ` Krzysztof Kozlowski
0 siblings, 0 replies; 21+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 16:25 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 31/10/2022 19:25, Melody Olvera wrote:
>
>
> On 10/31/2022 2:49 PM, Melody Olvera wrote:
>>
>> On 10/27/2022 8:21 AM, Krzysztof Kozlowski wrote:
>>> On 26/10/2022 16:04, Melody Olvera wrote:
>>>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
>>>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller
>>>> to boot to shell with console on these SoCs.
>>>>
>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++++++++++
>>> Please use scripts/get_maintainers.pl to get a list of necessary people
>>> and lists to CC. It might happen, that command when run on an older
>>> kernel, gives you outdated entries. Therefore please be sure you base
>>> your patches on recent Linux kernel.
>> Sure thing; we talked about this on a different patch.
>>>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 +
>>>> 2 files changed, 1433 insertions(+)
>>>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>> new file mode 100644
>>>> index 000000000000..76474106e931
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>> @@ -0,0 +1,1406 @@
>>>> +// SPDX-License-Identifier: BSD-3-Clause
>>>> +/*
>>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>>>> + */
>>> (...)
>>>
>>>> +
>>>> + soc: soc@0 {
>>>> + #address-cells = <2>;
>>>> + #size-cells = <2>;
>>>> + ranges = <0 0 0 0 0x10 0>;
>>>> + dma-ranges = <0 0 0 0 0x10 0>;
>>>> + compatible = "simple-bus";
>>>> +
>>>> + gcc: clock-controller@80000 {
>>>> + compatible = "qcom,gcc-qdu1000", "syscon";
>>>> + reg = <0x0 0x80000 0x0 0x1f4200>;
>>>> + #clock-cells = <1>;
>>>> + #reset-cells = <1>;
>>>> + #power-domain-cells = <1>;
>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
>>>> + clock-names = "bi_tcxo", "sleep_clk";
>>>> + };
>>>> +
>>>> + gpi_dma0: dma-controller@900000 {
>>>> + compatible = "qcom,sm6350-gpi-dma";
>>> You should add here a specific compatible as well. Same in other places.
>>> All places. I had impression we talked about this few times, so I don't
>>> know what is missing on your side.
>>>
>>> This must be:
>>> "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"
>> Got it. I talked to Stephan and he said either your suggestion or just using
>> preexisting compatibles would be ok. I thought it might be cleaner to not
>> have the qdu compats, but I'm fine either way.
> Coming back to this, it looks like this will fail dtb_check since compatible field is too long.
> Is there an adjustment to the binding which needs to be made here?
Every compatible must be documented, so yes, bindings needs changes.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-11-02 16:24 ` Krzysztof Kozlowski
@ 2022-11-03 21:13 ` Melody Olvera
2022-11-04 4:05 ` Trilok Soni
0 siblings, 1 reply; 21+ messages in thread
From: Melody Olvera @ 2022-11-03 21:13 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 11/2/2022 9:24 AM, Krzysztof Kozlowski wrote:
> On 31/10/2022 17:49, Melody Olvera wrote:
>>
>> On 10/27/2022 8:21 AM, Krzysztof Kozlowski wrote:
>>> On 26/10/2022 16:04, Melody Olvera wrote:
>>>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
>>>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller
>>>> to boot to shell with console on these SoCs.
>>>>
>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++++++++++
>>> Please use scripts/get_maintainers.pl to get a list of necessary people
>>> and lists to CC. It might happen, that command when run on an older
>>> kernel, gives you outdated entries. Therefore please be sure you base
>>> your patches on recent Linux kernel.
>> Sure thing; we talked about this on a different patch.
>>>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 +
>>>> 2 files changed, 1433 insertions(+)
>>>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>> new file mode 100644
>>>> index 000000000000..76474106e931
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>> @@ -0,0 +1,1406 @@
>>>> +// SPDX-License-Identifier: BSD-3-Clause
>>>> +/*
>>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>>>> + */
>>> (...)
>>>
>>>> +
>>>> + soc: soc@0 {
>>>> + #address-cells = <2>;
>>>> + #size-cells = <2>;
>>>> + ranges = <0 0 0 0 0x10 0>;
>>>> + dma-ranges = <0 0 0 0 0x10 0>;
>>>> + compatible = "simple-bus";
>>>> +
>>>> + gcc: clock-controller@80000 {
>>>> + compatible = "qcom,gcc-qdu1000", "syscon";
>>>> + reg = <0x0 0x80000 0x0 0x1f4200>;
>>>> + #clock-cells = <1>;
>>>> + #reset-cells = <1>;
>>>> + #power-domain-cells = <1>;
>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
>>>> + clock-names = "bi_tcxo", "sleep_clk";
>>>> + };
>>>> +
>>>> + gpi_dma0: dma-controller@900000 {
>>>> + compatible = "qcom,sm6350-gpi-dma";
>>> You should add here a specific compatible as well. Same in other places.
>>> All places. I had impression we talked about this few times, so I don't
>>> know what is missing on your side.
>>>
>>> This must be:
>>> "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"
>> Got it. I talked to Stephan and he said either your suggestion or just using
>> preexisting compatibles would be ok. I thought it might be cleaner to not
>> have the qdu compats, but I'm fine either way.
>>>> + #dma-cells = <3>;
>>>> + reg = <0x0 0x900000 0x0 0x60000>;
>>>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
>>>> + dma-channels = <12>;
>>>> + dma-channel-mask = <0x3f>;
>>>> + iommus = <&apps_smmu 0xf6 0x0>;
>>>> + };
>>>> +
>>> (...)
>>>
>>>
>>>> +
>>>> + tlmm: pinctrl@f000000 {
>>>> + compatible = "qcom,qdu1000-tlmm";
>>>> + reg = <0x0 0xf000000 0x0 0x1000000>;
>>>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>>> + gpio-controller;
>>>> + #gpio-cells = <2>;
>>>> + interrupt-controller;
>>>> + #interrupt-cells = <2>;
>>>> + gpio-ranges = <&tlmm 0 0 151>;
>>>> + wakeup-parent = <&pdc>;
>>>> +
>>>> + qup_uart0_default: qup-uart0-default-state {
>>>> + pins = "gpio6", "gpio7", "gpio8", "gpio9";
>>>> + function = "qup00";
>>>> + };
>>>> +
>>>> + qup_i2c1_data_clk: qup-i2c1-data-clk-state {
>>>> + pins = "gpio10", "gpio11";
>>>> + function = "qup01";
>>>> + drive-strength = <2>;
>>> Can we have some generic agreement where to put drive-strengths and bias?
>>>
>>> See also:
>>> https://lore.kernel.org/linux-devicetree/20221026200357.391635-2-krzysztof.kozlowski@linaro.org/
>>>
>>> https://lore.kernel.org/lkml/CAD=FV=VUL4GmjaibAMhKNdpEso_Hg_R=XeMaqah1LSj_9-Ce4Q@mail.gmail.com/
>> Not sure how much two-sense I have for the conversation at large, but generally I agree with Doug's
>> point in the first paragraph. Pulls for this soc are consistent across boards so I don't think it makes
>> sense to move them to the board files here. I vote that these stay here.
> I would be great if Konrad and Bjorn shared their opinion on this... but
> wait, you did not Cc all maintainers... Eh.
I'm not sure why this is being brought up again; we've already discussed this here
https://lore.kernel.org/all/9707bf67-1b22-8a77-7193-fc909b4f49de@quicinc.com/
Would you like to discuss this issue here, on the next version, or not at all?
On a side note, I'm uncomfortable with how our continued interactions are going
and do not believe this to be conductive to continued collaboration. I would ask that
we keep our correspondence polite and professional moving forward.
Thanks,
Melody
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-11-03 21:13 ` Melody Olvera
@ 2022-11-04 4:05 ` Trilok Soni
2022-11-04 9:32 ` Konrad Dybcio
0 siblings, 1 reply; 21+ messages in thread
From: Trilok Soni @ 2022-11-04 4:05 UTC (permalink / raw)
To: Melody Olvera, Krzysztof Kozlowski, Andy Gross, Bjorn Andersson,
Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Konrad Dybcio
+ Adding Konrad, Bjorn is already there in this email
On 11/3/2022 2:13 PM, Melody Olvera wrote:
>
>
> On 11/2/2022 9:24 AM, Krzysztof Kozlowski wrote:
>> On 31/10/2022 17:49, Melody Olvera wrote:
>>>
>>> On 10/27/2022 8:21 AM, Krzysztof Kozlowski wrote:
>>>> On 26/10/2022 16:04, Melody Olvera wrote:
>>>>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
>>>>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller
>>>>> to boot to shell with console on these SoCs.
>>>>>
>>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>>> ---
>>>>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++++++++++
>>>> Please use scripts/get_maintainers.pl to get a list of necessary people
>>>> and lists to CC. It might happen, that command when run on an older
>>>> kernel, gives you outdated entries. Therefore please be sure you base
>>>> your patches on recent Linux kernel.
>>> Sure thing; we talked about this on a different patch.
>>>>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 +
>>>>> 2 files changed, 1433 insertions(+)
>>>>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>>> new file mode 100644
>>>>> index 000000000000..76474106e931
>>>>> --- /dev/null
>>>>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>>> @@ -0,0 +1,1406 @@
>>>>> +// SPDX-License-Identifier: BSD-3-Clause
>>>>> +/*
>>>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>>>>> + */
>>>> (...)
>>>>
>>>>> +
>>>>> + soc: soc@0 {
>>>>> + #address-cells = <2>;
>>>>> + #size-cells = <2>;
>>>>> + ranges = <0 0 0 0 0x10 0>;
>>>>> + dma-ranges = <0 0 0 0 0x10 0>;
>>>>> + compatible = "simple-bus";
>>>>> +
>>>>> + gcc: clock-controller@80000 {
>>>>> + compatible = "qcom,gcc-qdu1000", "syscon";
>>>>> + reg = <0x0 0x80000 0x0 0x1f4200>;
>>>>> + #clock-cells = <1>;
>>>>> + #reset-cells = <1>;
>>>>> + #power-domain-cells = <1>;
>>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
>>>>> + clock-names = "bi_tcxo", "sleep_clk";
>>>>> + };
>>>>> +
>>>>> + gpi_dma0: dma-controller@900000 {
>>>>> + compatible = "qcom,sm6350-gpi-dma";
>>>> You should add here a specific compatible as well. Same in other places.
>>>> All places. I had impression we talked about this few times, so I don't
>>>> know what is missing on your side.
>>>>
>>>> This must be:
>>>> "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"
>>> Got it. I talked to Stephan and he said either your suggestion or just using
>>> preexisting compatibles would be ok. I thought it might be cleaner to not
>>> have the qdu compats, but I'm fine either way.
>>>>> + #dma-cells = <3>;
>>>>> + reg = <0x0 0x900000 0x0 0x60000>;
>>>>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
>>>>> + dma-channels = <12>;
>>>>> + dma-channel-mask = <0x3f>;
>>>>> + iommus = <&apps_smmu 0xf6 0x0>;
>>>>> + };
>>>>> +
>>>> (...)
>>>>
>>>>
>>>>> +
>>>>> + tlmm: pinctrl@f000000 {
>>>>> + compatible = "qcom,qdu1000-tlmm";
>>>>> + reg = <0x0 0xf000000 0x0 0x1000000>;
>>>>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>>>> + gpio-controller;
>>>>> + #gpio-cells = <2>;
>>>>> + interrupt-controller;
>>>>> + #interrupt-cells = <2>;
>>>>> + gpio-ranges = <&tlmm 0 0 151>;
>>>>> + wakeup-parent = <&pdc>;
>>>>> +
>>>>> + qup_uart0_default: qup-uart0-default-state {
>>>>> + pins = "gpio6", "gpio7", "gpio8", "gpio9";
>>>>> + function = "qup00";
>>>>> + };
>>>>> +
>>>>> + qup_i2c1_data_clk: qup-i2c1-data-clk-state {
>>>>> + pins = "gpio10", "gpio11";
>>>>> + function = "qup01";
>>>>> + drive-strength = <2>;
>>>> Can we have some generic agreement where to put drive-strengths and bias?
>>>>
>>>> See also:
>>>> https://lore.kernel.org/linux-devicetree/20221026200357.391635-2-krzysztof.kozlowski@linaro.org/
>>>>
>>>> https://lore.kernel.org/lkml/CAD=FV=VUL4GmjaibAMhKNdpEso_Hg_R=XeMaqah1LSj_9-Ce4Q@mail.gmail.com/
>>> Not sure how much two-sense I have for the conversation at large, but generally I agree with Doug's
>>> point in the first paragraph. Pulls for this soc are consistent across boards so I don't think it makes
>>> sense to move them to the board files here. I vote that these stay here.
>> I would be great if Konrad and Bjorn shared their opinion on this... but
>> wait, you did not Cc all maintainers... Eh.
> I'm not sure why this is being brought up again; we've already discussed this here
> https://lore.kernel.org/all/9707bf67-1b22-8a77-7193-fc909b4f49de@quicinc.com/
> Would you like to discuss this issue here, on the next version, or not at all?
>
> On a side note, I'm uncomfortable with how our continued interactions are going
> and do not believe this to be conductive to continued collaboration. I would ask that
> we keep our correspondence polite and professional moving forward.
I have added Konrad and Bjorn is already there on the thread. Our
understanding is that CCing maintainers comment is for next patch series
after this one.
Bjorn, please check and comment on above? If requires we should start
writing the guidelines for MSM boards since lot of comments are based on
the experience or knowledge in the community Vs caught by tools - so it
is easy to be missed by developers submitting new boards. Thoughts?
---Trilok Soni
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-11-04 4:05 ` Trilok Soni
@ 2022-11-04 9:32 ` Konrad Dybcio
2022-11-04 15:34 ` Rob Herring
2022-11-09 18:19 ` Melody Olvera
0 siblings, 2 replies; 21+ messages in thread
From: Konrad Dybcio @ 2022-11-04 9:32 UTC (permalink / raw)
To: Trilok Soni, Melody Olvera, Krzysztof Kozlowski, Andy Gross,
Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 04/11/2022 05:05, Trilok Soni wrote:
> + Adding Konrad, Bjorn is already there in this email
>
> On 11/3/2022 2:13 PM, Melody Olvera wrote:
>>
>>
>> On 11/2/2022 9:24 AM, Krzysztof Kozlowski wrote:
>>> On 31/10/2022 17:49, Melody Olvera wrote:
>>>>
>>>> On 10/27/2022 8:21 AM, Krzysztof Kozlowski wrote:
>>>>> On 26/10/2022 16:04, Melody Olvera wrote:
>>>>>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
>>>>>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and
>>>>>> interrupt-controller
>>>>>> to boot to shell with console on these SoCs.
>>>>>>
>>>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>>>> ---
>>>>>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406
>>>>>> +++++++++++++++++++++++++
>>>>> Please use scripts/get_maintainers.pl to get a list of necessary
>>>>> people
>>>>> and lists to CC. It might happen, that command when run on an older
>>>>> kernel, gives you outdated entries. Therefore please be sure you
>>>>> base
>>>>> your patches on recent Linux kernel.
>>>> Sure thing; we talked about this on a different patch.
>>>>>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 +
>>>>>> 2 files changed, 1433 insertions(+)
>>>>>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>>>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>>>> b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>>>> new file mode 100644
>>>>>> index 000000000000..76474106e931
>>>>>> --- /dev/null
>>>>>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>>>> @@ -0,0 +1,1406 @@
>>>>>> +// SPDX-License-Identifier: BSD-3-Clause
>>>>>> +/*
>>>>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All
>>>>>> rights reserved.
>>>>>> + */
>>>>> (...)
>>>>>
>>>>>> +
>>>>>> + soc: soc@0 {
>>>>>> + #address-cells = <2>;
>>>>>> + #size-cells = <2>;
>>>>>> + ranges = <0 0 0 0 0x10 0>;
>>>>>> + dma-ranges = <0 0 0 0 0x10 0>;
>>>>>> + compatible = "simple-bus";
>>>>>> +
>>>>>> + gcc: clock-controller@80000 {
>>>>>> + compatible = "qcom,gcc-qdu1000", "syscon";
>>>>>> + reg = <0x0 0x80000 0x0 0x1f4200>;
>>>>>> + #clock-cells = <1>;
>>>>>> + #reset-cells = <1>;
>>>>>> + #power-domain-cells = <1>;
>>>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
>>>>>> + clock-names = "bi_tcxo", "sleep_clk";
>>>>>> + };
>>>>>> +
>>>>>> + gpi_dma0: dma-controller@900000 {
>>>>>> + compatible = "qcom,sm6350-gpi-dma";
>>>>> You should add here a specific compatible as well. Same in other
>>>>> places.
>>>>> All places. I had impression we talked about this few times, so I
>>>>> don't
>>>>> know what is missing on your side.
>>>>>
>>>>> This must be:
>>>>> "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"
>>>> Got it. I talked to Stephan and he said either your suggestion or
>>>> just using
>>>> preexisting compatibles would be ok. I thought it might be cleaner
>>>> to not
>>>> have the qdu compats, but I'm fine either way.
We use specific compats so that if it turns out this specific SoC (or
rather the
bundled firmware) has some peculiar bugs, we can retroactively only
apply them
to that specific SoC by adding the compatible somewhere in .c code if
need be.
>>>>>> + #dma-cells = <3>;
>>>>>> + reg = <0x0 0x900000 0x0 0x60000>;
>>>>>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> + dma-channels = <12>;
>>>>>> + dma-channel-mask = <0x3f>;
>>>>>> + iommus = <&apps_smmu 0xf6 0x0>;
>>>>>> + };
>>>>>> +
>>>>> (...)
>>>>>
>>>>>
>>>>>> +
>>>>>> + tlmm: pinctrl@f000000 {
>>>>>> + compatible = "qcom,qdu1000-tlmm";
>>>>>> + reg = <0x0 0xf000000 0x0 0x1000000>;
>>>>>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> + gpio-controller;
>>>>>> + #gpio-cells = <2>;
>>>>>> + interrupt-controller;
>>>>>> + #interrupt-cells = <2>;
>>>>>> + gpio-ranges = <&tlmm 0 0 151>;
>>>>>> + wakeup-parent = <&pdc>;
>>>>>> +
>>>>>> + qup_uart0_default: qup-uart0-default-state {
>>>>>> + pins = "gpio6", "gpio7", "gpio8", "gpio9";
>>>>>> + function = "qup00";
>>>>>> + };
>>>>>> +
>>>>>> + qup_i2c1_data_clk: qup-i2c1-data-clk-state {
>>>>>> + pins = "gpio10", "gpio11";
>>>>>> + function = "qup01";
>>>>>> + drive-strength = <2>;
>>>>> Can we have some generic agreement where to put drive-strengths
>>>>> and bias?
>>>>>
>>>>> See also:
>>>>> https://lore.kernel.org/linux-devicetree/20221026200357.391635-2-krzysztof.kozlowski@linaro.org/
>>>>>
>>>>>
>>>>> https://lore.kernel.org/lkml/CAD=FV=VUL4GmjaibAMhKNdpEso_Hg_R=XeMaqah1LSj_9-Ce4Q@mail.gmail.com/
>>>>>
I agree with Doug on having 'generic' drive-strength. Moreover, maybe
even adding some property like
bias-type = <NONE/PULL_DOWN/...> would be cool to make it more flexible
so that we could trim off
A LOT of repeated lines (remember, most boards are more or less copies
of the reference design for a
given platform like QRD or CRD) going forward.
>>>> Not sure how much two-sense I have for the conversation at large,
>>>> but generally I agree with Doug's
>>>> point in the first paragraph. Pulls for this soc are consistent
>>>> across boards so I don't think it makes
>>>> sense to move them to the board files here. I vote that these stay
>>>> here.
>>> I would be great if Konrad and Bjorn shared their opinion on this...
>>> but
>>> wait, you did not Cc all maintainers... Eh.
>> I'm not sure why this is being brought up again; we've already
>> discussed this here
>> https://lore.kernel.org/all/9707bf67-1b22-8a77-7193-fc909b4f49de@quicinc.com/
>>
>> Would you like to discuss this issue here, on the next version, or
>> not at all?
>>
>> On a side note, I'm uncomfortable with how our continued interactions
>> are going
>> and do not believe this to be conductive to continued collaboration.
>> I would ask that
>> we keep our correspondence polite and professional moving forward.
>
> I have added Konrad and Bjorn is already there on the thread. Our
> understanding is that CCing maintainers comment is for next patch
> series after this one.
BTW: you can feed git send-email with
--cc-cmd='./scripts/get_maintainer.pl --norolestats' and
it'll pick the right people for you (most of the time, anyway).
>
> Bjorn, please check and comment on above? If requires we should start
> writing the guidelines for MSM boards since lot of comments are based
> on the experience or knowledge in the community Vs caught by tools -
> so it is easy to be missed by developers submitting new boards. Thoughts?
Big yes! Some of the points should probably even be raised wrt the DT
spec itself, such as property order.
Konrad
>
> ---Trilok Soni
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-11-04 9:32 ` Konrad Dybcio
@ 2022-11-04 15:34 ` Rob Herring
2022-11-09 18:19 ` Melody Olvera
1 sibling, 0 replies; 21+ messages in thread
From: Rob Herring @ 2022-11-04 15:34 UTC (permalink / raw)
To: Konrad Dybcio, Trilok Soni, Melody Olvera
Cc: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson,
Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel
On Fri, Nov 4, 2022 at 4:32 AM Konrad Dybcio
<konrad.dybcio@somainline.org> wrote:
> On 04/11/2022 05:05, Trilok Soni wrote:
> > + Adding Konrad, Bjorn is already there in this email
> >
> > On 11/3/2022 2:13 PM, Melody Olvera wrote:
> >>
> >>
> >> On 11/2/2022 9:24 AM, Krzysztof Kozlowski wrote:
> >>> On 31/10/2022 17:49, Melody Olvera wrote:
> >>>>
> >>>> On 10/27/2022 8:21 AM, Krzysztof Kozlowski wrote:
> >>>>> On 26/10/2022 16:04, Melody Olvera wrote:
> >>>>>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
> >>>>>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and
> >>>>>> interrupt-controller
> >>>>>> to boot to shell with console on these SoCs.
[...]
> >>>> Not sure how much two-sense I have for the conversation at large,
> >>>> but generally I agree with Doug's
> >>>> point in the first paragraph. Pulls for this soc are consistent
> >>>> across boards so I don't think it makes
> >>>> sense to move them to the board files here. I vote that these stay
> >>>> here.
> >>> I would be great if Konrad and Bjorn shared their opinion on this...
> >>> but
> >>> wait, you did not Cc all maintainers... Eh.
> >> I'm not sure why this is being brought up again; we've already
> >> discussed this here
> >> https://lore.kernel.org/all/9707bf67-1b22-8a77-7193-fc909b4f49de@quicinc.com/
A bit excessive, yes. If it's just a discussion and the issue has
already been raised, add the people and move on. OTOH, imagine having
to mention the same things multiple times a day in reviews. It is
tiring.
> >> Would you like to discuss this issue here, on the next version, or
> >> not at all?
> >>
> >> On a side note, I'm uncomfortable with how our continued interactions
> >> are going
> >> and do not believe this to be conductive to continued collaboration.
> >> I would ask that
> >> we keep our correspondence polite and professional moving forward.
> >
> > I have added Konrad and Bjorn is already there on the thread. Our
> > understanding is that CCing maintainers comment is for next patch
> > series after this one.
>
> BTW: you can feed git send-email with
> --cc-cmd='./scripts/get_maintainer.pl --norolestats' and
>
> it'll pick the right people for you (most of the time, anyway).
That uses git history which doesn't really work well IMO being on the
receiving end of those. I would suggest something like this in your
.gitconfig:
[sendemail.linux]
tocmd =" scripts/get_maintainer.pl --nogit --nogit-fallback --nol"
cccmd ="scripts/get_maintainer.pl --nogit --nogit-fallback --nom"
confirm = always
Then you do just 'git send-email --identity=linux ...'
Or use b4 as it does the above and works better for series.
> > Bjorn, please check and comment on above? If requires we should start
> > writing the guidelines for MSM boards since lot of comments are based
> > on the experience or knowledge in the community Vs caught by tools -
> > so it is easy to be missed by developers submitting new boards. Thoughts?
Some internal review or training for new contributors is needed IMO.
Some companies are required to have an known/experienced kernel
developer signoff on patches before they are submitted. I don't think
you want to get to that point.
> Big yes! Some of the points should probably even be raised wrt the DT
> spec itself, such as property order.
Ideally, we should only be providing comments that can be referenced
to documentation (if the tooling can't address it). In this case, I
don't think the DT spec would be the right place property order. It's
just a convention for the schema format. However, often the
documentation we do have already isn't followed, so I'm not too
motivated to add more.
Rob
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: (subset) [PATCH v3 0/4] Add base device tree files for QDU1000/QRU1000
2022-10-26 20:04 [PATCH v3 0/4] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (3 preceding siblings ...)
2022-10-26 20:04 ` [PATCH v3 4/4] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera
@ 2022-11-08 1:27 ` Bjorn Andersson
4 siblings, 0 replies; 21+ messages in thread
From: Bjorn Andersson @ 2022-11-08 1:27 UTC (permalink / raw)
To: robh+dt, quic_molvera, krzysztof.kozlowski+dt, agross
Cc: linux-arm-msm, devicetree, linux-kernel
On Wed, 26 Oct 2022 13:04:25 -0700, Melody Olvera wrote:
> This series adds the base device tree files and DTS support for the
> Qualcomm QDU1000 and QRU1000 IDP SoCs, including the clocks, tlmm, smmu,
> regulators, mmc, interconnects, cpufreq, and qup.
>
> This patchset is based off of [1] which adds support for the PMIC arb used
> on these SoCs. It also requires the dt-bindings from [2], [3], [4], [5],
> and [6].
>
> [...]
Applied, thanks!
[2/4] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards
commit: cc677f9006c4277bd25881c6713e5ef79bddd79a
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes
2022-10-27 15:08 ` Krzysztof Kozlowski
@ 2022-11-08 21:34 ` Melody Olvera
0 siblings, 0 replies; 21+ messages in thread
From: Melody Olvera @ 2022-11-08 21:34 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/27/2022 8:08 AM, Krzysztof Kozlowski wrote:
> On 26/10/2022 16:04, Melody Olvera wrote:
>> Update the bindings to allow for generic regulator nodes instead of
>> device-specific node names.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
>> index 4a50f1d27724..0e7e07975f3a 100644
>> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
>> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
>> @@ -109,7 +109,7 @@ properties:
>> $ref: /schemas/power/qcom,rpmpd.yaml#
>>
>> patternProperties:
>> - '-regulators$':
>> + 'regulators$':
> This should be rather fixed like:
> https://lore.kernel.org/linux-devicetree/20220926092104.111449-1-krzysztof.kozlowski@linaro.org/
Got it.
Thanks,
Melody
>
> I don't know why there is such a popularity of adding specific model
> names as device node names...
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-11-04 9:32 ` Konrad Dybcio
2022-11-04 15:34 ` Rob Herring
@ 2022-11-09 18:19 ` Melody Olvera
2022-11-16 17:34 ` Melody Olvera
1 sibling, 1 reply; 21+ messages in thread
From: Melody Olvera @ 2022-11-09 18:19 UTC (permalink / raw)
To: Konrad Dybcio, Trilok Soni, Krzysztof Kozlowski, Andy Gross,
Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 11/4/2022 2:32 AM, Konrad Dybcio wrote:
>
> On 04/11/2022 05:05, Trilok Soni wrote:
>> + Adding Konrad, Bjorn is already there in this email
>>
>> On 11/3/2022 2:13 PM, Melody Olvera wrote:
>>>
>>>
>>> On 11/2/2022 9:24 AM, Krzysztof Kozlowski wrote:
>>>> On 31/10/2022 17:49, Melody Olvera wrote:
>>>>>
>>>>> On 10/27/2022 8:21 AM, Krzysztof Kozlowski wrote:
>>>>>> On 26/10/2022 16:04, Melody Olvera wrote:
>>>>>>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
>>>>>>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller
>>>>>>> to boot to shell with console on these SoCs.
>>>>>>>
>>>>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>>>>> ---
>>>>>>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++++++++++
>>>>>> Please use scripts/get_maintainers.pl to get a list of necessary people
>>>>>> and lists to CC. It might happen, that command when run on an older
>>>>>> kernel, gives you outdated entries. Therefore please be sure you base
>>>>>> your patches on recent Linux kernel.
>>>>> Sure thing; we talked about this on a different patch.
>>>>>>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 +
>>>>>>> 2 files changed, 1433 insertions(+)
>>>>>>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>>>>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>>>>>>>
>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>>>>> new file mode 100644
>>>>>>> index 000000000000..76474106e931
>>>>>>> --- /dev/null
>>>>>>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>>>>> @@ -0,0 +1,1406 @@
>>>>>>> +// SPDX-License-Identifier: BSD-3-Clause
>>>>>>> +/*
>>>>>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>>>>>>> + */
>>>>>> (...)
>>>>>>
>>>>>>> +
>>>>>>> + soc: soc@0 {
>>>>>>> + #address-cells = <2>;
>>>>>>> + #size-cells = <2>;
>>>>>>> + ranges = <0 0 0 0 0x10 0>;
>>>>>>> + dma-ranges = <0 0 0 0 0x10 0>;
>>>>>>> + compatible = "simple-bus";
>>>>>>> +
>>>>>>> + gcc: clock-controller@80000 {
>>>>>>> + compatible = "qcom,gcc-qdu1000", "syscon";
>>>>>>> + reg = <0x0 0x80000 0x0 0x1f4200>;
>>>>>>> + #clock-cells = <1>;
>>>>>>> + #reset-cells = <1>;
>>>>>>> + #power-domain-cells = <1>;
>>>>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
>>>>>>> + clock-names = "bi_tcxo", "sleep_clk";
>>>>>>> + };
>>>>>>> +
>>>>>>> + gpi_dma0: dma-controller@900000 {
>>>>>>> + compatible = "qcom,sm6350-gpi-dma";
>>>>>> You should add here a specific compatible as well. Same in other places.
>>>>>> All places. I had impression we talked about this few times, so I don't
>>>>>> know what is missing on your side.
>>>>>>
>>>>>> This must be:
>>>>>> "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"
>>>>> Got it. I talked to Stephan and he said either your suggestion or just using
>>>>> preexisting compatibles would be ok. I thought it might be cleaner to not
>>>>> have the qdu compats, but I'm fine either way.
>
> We use specific compats so that if it turns out this specific SoC (or rather the
>
> bundled firmware) has some peculiar bugs, we can retroactively only apply them
>
> to that specific SoC by adding the compatible somewhere in .c code if need be.
Ah that makes plenty sense.
>
>
>>>>>>> + #dma-cells = <3>;
>>>>>>> + reg = <0x0 0x900000 0x0 0x60000>;
>>>>>>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> + dma-channels = <12>;
>>>>>>> + dma-channel-mask = <0x3f>;
>>>>>>> + iommus = <&apps_smmu 0xf6 0x0>;
>>>>>>> + };
>>>>>>> +
>>>>>> (...)
>>>>>>
>>>>>>
>>>>>>> +
>>>>>>> + tlmm: pinctrl@f000000 {
>>>>>>> + compatible = "qcom,qdu1000-tlmm";
>>>>>>> + reg = <0x0 0xf000000 0x0 0x1000000>;
>>>>>>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> + gpio-controller;
>>>>>>> + #gpio-cells = <2>;
>>>>>>> + interrupt-controller;
>>>>>>> + #interrupt-cells = <2>;
>>>>>>> + gpio-ranges = <&tlmm 0 0 151>;
>>>>>>> + wakeup-parent = <&pdc>;
>>>>>>> +
>>>>>>> + qup_uart0_default: qup-uart0-default-state {
>>>>>>> + pins = "gpio6", "gpio7", "gpio8", "gpio9";
>>>>>>> + function = "qup00";
>>>>>>> + };
>>>>>>> +
>>>>>>> + qup_i2c1_data_clk: qup-i2c1-data-clk-state {
>>>>>>> + pins = "gpio10", "gpio11";
>>>>>>> + function = "qup01";
>>>>>>> + drive-strength = <2>;
>>>>>> Can we have some generic agreement where to put drive-strengths and bias?
>>>>>>
>>>>>> See also:
>>>>>> https://lore.kernel.org/linux-devicetree/20221026200357.391635-2-krzysztof.kozlowski@linaro.org/
>>>>>>
>>>>>> https://lore.kernel.org/lkml/CAD=FV=VUL4GmjaibAMhKNdpEso_Hg_R=XeMaqah1LSj_9-Ce4Q@mail.gmail.com/
>
> I agree with Doug on having 'generic' drive-strength. Moreover, maybe even adding some property like
>
> bias-type = <NONE/PULL_DOWN/...> would be cool to make it more flexible so that we could trim off
>
> A LOT of repeated lines (remember, most boards are more or less copies of the reference design for a
>
> given platform like QRD or CRD) going forward.
Huh so if I understand this correctly, like a generic QRD/CRD file which has the bias for specific pins?
That's a neat idea.
I will say it kinda seems like this is a larger conversation happening here. Does it make sense to submit
a next version with these pins as they are or wait until this larger conversation concludes?
>
>
>>>>> Not sure how much two-sense I have for the conversation at large, but generally I agree with Doug's
>>>>> point in the first paragraph. Pulls for this soc are consistent across boards so I don't think it makes
>>>>> sense to move them to the board files here. I vote that these stay here.
>>>> I would be great if Konrad and Bjorn shared their opinion on this... but
>>>> wait, you did not Cc all maintainers... Eh.
>>> I'm not sure why this is being brought up again; we've already discussed this here
>>> https://lore.kernel.org/all/9707bf67-1b22-8a77-7193-fc909b4f49de@quicinc.com/
>>> Would you like to discuss this issue here, on the next version, or not at all?
>>>
>>> On a side note, I'm uncomfortable with how our continued interactions are going
>>> and do not believe this to be conductive to continued collaboration. I would ask that
>>> we keep our correspondence polite and professional moving forward.
>>
>> I have added Konrad and Bjorn is already there on the thread. Our understanding is that CCing maintainers comment is for next patch series after this one.
>
> BTW: you can feed git send-email with --cc-cmd='./scripts/get_maintainer.pl --norolestats' and
>
> it'll pick the right people for you (most of the time, anyway).
Sounds good; thanks for the help!
Thanks,
Melody
>
>
>>
>> Bjorn, please check and comment on above? If requires we should start writing the guidelines for MSM boards since lot of comments are based on the experience or knowledge in the community Vs caught by tools - so it is easy to be missed by developers submitting new boards. Thoughts?
>
> Big yes! Some of the points should probably even be raised wrt the DT spec itself, such as property order.
>
>
> Konrad
>
>>
>> ---Trilok Soni
>>
>>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-11-09 18:19 ` Melody Olvera
@ 2022-11-16 17:34 ` Melody Olvera
0 siblings, 0 replies; 21+ messages in thread
From: Melody Olvera @ 2022-11-16 17:34 UTC (permalink / raw)
To: Konrad Dybcio, Trilok Soni, Krzysztof Kozlowski, Andy Gross,
Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 11/9/2022 12:19 PM, Melody Olvera wrote:
>
> On 11/4/2022 2:32 AM, Konrad Dybcio wrote:
>> On 04/11/2022 05:05, Trilok Soni wrote:
>>> + Adding Konrad, Bjorn is already there in this email
>>>
>>> On 11/3/2022 2:13 PM, Melody Olvera wrote:
>>>>
>>>> On 11/2/2022 9:24 AM, Krzysztof Kozlowski wrote:
>>>>> On 31/10/2022 17:49, Melody Olvera wrote:
>>>>>> On 10/27/2022 8:21 AM, Krzysztof Kozlowski wrote:
>>>>>>> On 26/10/2022 16:04, Melody Olvera wrote:
>>>>>>>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
>>>>>>>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller
>>>>>>>> to boot to shell with console on these SoCs.
>>>>>>>>
>>>>>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>>>>>> ---
>>>>>>>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++++++++++
>>>>>>> Please use scripts/get_maintainers.pl to get a list of necessary people
>>>>>>> and lists to CC. It might happen, that command when run on an older
>>>>>>> kernel, gives you outdated entries. Therefore please be sure you base
>>>>>>> your patches on recent Linux kernel.
>>>>>> Sure thing; we talked about this on a different patch.
>>>>>>>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 +
>>>>>>>> 2 files changed, 1433 insertions(+)
>>>>>>>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>>>>>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>>>>>> new file mode 100644
>>>>>>>> index 000000000000..76474106e931
>>>>>>>> --- /dev/null
>>>>>>>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>>>>>>>> @@ -0,0 +1,1406 @@
>>>>>>>> +// SPDX-License-Identifier: BSD-3-Clause
>>>>>>>> +/*
>>>>>>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>>>>>>>> + */
>>>>>>> (...)
>>>>>>>
>>>>>>>> +
>>>>>>>> + soc: soc@0 {
>>>>>>>> + #address-cells = <2>;
>>>>>>>> + #size-cells = <2>;
>>>>>>>> + ranges = <0 0 0 0 0x10 0>;
>>>>>>>> + dma-ranges = <0 0 0 0 0x10 0>;
>>>>>>>> + compatible = "simple-bus";
>>>>>>>> +
>>>>>>>> + gcc: clock-controller@80000 {
>>>>>>>> + compatible = "qcom,gcc-qdu1000", "syscon";
>>>>>>>> + reg = <0x0 0x80000 0x0 0x1f4200>;
>>>>>>>> + #clock-cells = <1>;
>>>>>>>> + #reset-cells = <1>;
>>>>>>>> + #power-domain-cells = <1>;
>>>>>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
>>>>>>>> + clock-names = "bi_tcxo", "sleep_clk";
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + gpi_dma0: dma-controller@900000 {
>>>>>>>> + compatible = "qcom,sm6350-gpi-dma";
>>>>>>> You should add here a specific compatible as well. Same in other places.
>>>>>>> All places. I had impression we talked about this few times, so I don't
>>>>>>> know what is missing on your side.
>>>>>>>
>>>>>>> This must be:
>>>>>>> "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"
>>>>>> Got it. I talked to Stephan and he said either your suggestion or just using
>>>>>> preexisting compatibles would be ok. I thought it might be cleaner to not
>>>>>> have the qdu compats, but I'm fine either way.
>> We use specific compats so that if it turns out this specific SoC (or rather the
>>
>> bundled firmware) has some peculiar bugs, we can retroactively only apply them
>>
>> to that specific SoC by adding the compatible somewhere in .c code if need be.
> Ah that makes plenty sense.
>
>>
>>>>>>>> + #dma-cells = <3>;
>>>>>>>> + reg = <0x0 0x900000 0x0 0x60000>;
>>>>>>>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>>> + dma-channels = <12>;
>>>>>>>> + dma-channel-mask = <0x3f>;
>>>>>>>> + iommus = <&apps_smmu 0xf6 0x0>;
>>>>>>>> + };
>>>>>>>> +
>>>>>>> (...)
>>>>>>>
>>>>>>>
>>>>>>>> +
>>>>>>>> + tlmm: pinctrl@f000000 {
>>>>>>>> + compatible = "qcom,qdu1000-tlmm";
>>>>>>>> + reg = <0x0 0xf000000 0x0 0x1000000>;
>>>>>>>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>>> + gpio-controller;
>>>>>>>> + #gpio-cells = <2>;
>>>>>>>> + interrupt-controller;
>>>>>>>> + #interrupt-cells = <2>;
>>>>>>>> + gpio-ranges = <&tlmm 0 0 151>;
>>>>>>>> + wakeup-parent = <&pdc>;
>>>>>>>> +
>>>>>>>> + qup_uart0_default: qup-uart0-default-state {
>>>>>>>> + pins = "gpio6", "gpio7", "gpio8", "gpio9";
>>>>>>>> + function = "qup00";
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + qup_i2c1_data_clk: qup-i2c1-data-clk-state {
>>>>>>>> + pins = "gpio10", "gpio11";
>>>>>>>> + function = "qup01";
>>>>>>>> + drive-strength = <2>;
>>>>>>> Can we have some generic agreement where to put drive-strengths and bias?
>>>>>>>
>>>>>>> See also:
>>>>>>> https://lore.kernel.org/linux-devicetree/20221026200357.391635-2-krzysztof.kozlowski@linaro.org/
>>>>>>>
>>>>>>> https://lore.kernel.org/lkml/CAD=FV=VUL4GmjaibAMhKNdpEso_Hg_R=XeMaqah1LSj_9-Ce4Q@mail.gmail.com/
>> I agree with Doug on having 'generic' drive-strength. Moreover, maybe even adding some property like
>>
>> bias-type = <NONE/PULL_DOWN/...> would be cool to make it more flexible so that we could trim off
>>
>> A LOT of repeated lines (remember, most boards are more or less copies of the reference design for a
>>
>> given platform like QRD or CRD) going forward.
> Huh so if I understand this correctly, like a generic QRD/CRD file which has the bias for specific pins?
> That's a neat idea.
>
> I will say it kinda seems like this is a larger conversation happening here. Does it make sense to submit
> a next version with these pins as they are or wait until this larger conversation concludes?
Ok, this conversation seems to have stalled for now. Will submit v4 with changes except for this;
we'll see where this conversation lands.
Thanks,
Melody
>
>>
>>>>>> Not sure how much two-sense I have for the conversation at large, but generally I agree with Doug's
>>>>>> point in the first paragraph. Pulls for this soc are consistent across boards so I don't think it makes
>>>>>> sense to move them to the board files here. I vote that these stay here.
>>>>> I would be great if Konrad and Bjorn shared their opinion on this... but
>>>>> wait, you did not Cc all maintainers... Eh.
>>>> I'm not sure why this is being brought up again; we've already discussed this here
>>>> https://lore.kernel.org/all/9707bf67-1b22-8a77-7193-fc909b4f49de@quicinc.com/
>>>> Would you like to discuss this issue here, on the next version, or not at all?
>>>>
>>>> On a side note, I'm uncomfortable with how our continued interactions are going
>>>> and do not believe this to be conductive to continued collaboration. I would ask that
>>>> we keep our correspondence polite and professional moving forward.
>>> I have added Konrad and Bjorn is already there on the thread. Our understanding is that CCing maintainers comment is for next patch series after this one.
>> BTW: you can feed git send-email with --cc-cmd='./scripts/get_maintainer.pl --norolestats' and
>>
>> it'll pick the right people for you (most of the time, anyway).
> Sounds good; thanks for the help!
>
> Thanks,
> Melody
>
>>
>>> Bjorn, please check and comment on above? If requires we should start writing the guidelines for MSM boards since lot of comments are based on the experience or knowledge in the community Vs caught by tools - so it is easy to be missed by developers submitting new boards. Thoughts?
>> Big yes! Some of the points should probably even be raised wrt the DT spec itself, such as property order.
>>
>>
>> Konrad
>>
>>> ---Trilok Soni
>>>
>>>
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2022-11-16 17:35 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-26 20:04 [PATCH v3 0/4] Add base device tree files for QDU1000/QRU1000 Melody Olvera
2022-10-26 20:04 ` [PATCH v3 1/4] dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes Melody Olvera
2022-10-27 15:08 ` Krzysztof Kozlowski
2022-11-08 21:34 ` Melody Olvera
2022-10-26 20:04 ` [PATCH v3 2/4] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards Melody Olvera
2022-10-27 15:15 ` Krzysztof Kozlowski
2022-10-26 20:04 ` [PATCH v3 3/4] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera
2022-10-27 15:21 ` Krzysztof Kozlowski
2022-10-31 21:49 ` Melody Olvera
2022-10-31 23:25 ` Melody Olvera
2022-11-02 16:25 ` Krzysztof Kozlowski
2022-11-02 16:24 ` Krzysztof Kozlowski
2022-11-03 21:13 ` Melody Olvera
2022-11-04 4:05 ` Trilok Soni
2022-11-04 9:32 ` Konrad Dybcio
2022-11-04 15:34 ` Rob Herring
2022-11-09 18:19 ` Melody Olvera
2022-11-16 17:34 ` Melody Olvera
2022-10-26 20:04 ` [PATCH v3 4/4] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera
2022-10-27 15:23 ` Krzysztof Kozlowski
2022-11-08 1:27 ` (subset) [PATCH v3 0/4] Add base device tree files for QDU1000/QRU1000 Bjorn Andersson
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