From mboxrd@z Thu Jan 1 00:00:00 1970 From: Patrice CHOTARD Date: Wed, 18 Mar 2020 09:46:14 +0000 Subject: [PATCH 7/9] ram: stm32mp1_ddr: fix self refresh disable during DQS training In-Reply-To: <20200306111355.7.I0f31274f26e4299269ef3c7d5a581d2abe96aad2@changeid> References: <20200306101412.15376-1-patrick.delaunay@st.com> <20200306111355.7.I0f31274f26e4299269ef3c7d5a581d2abe96aad2@changeid> Message-ID: <9ed0f904-bb30-b5a2-864d-d74129949451@st.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 3/6/20 11:14 AM, Patrick Delaunay wrote: > DDRCTRL_PWRCTL.SELFREF_EN needs to be reset before DQS training step, not > to enter in self refresh mode during the execution of this phase. > Depending on settings, it can be set after the DQS training. > > Signed-off-by: Patrick Delaunay > --- > > drivers/ram/stm32mp1/stm32mp1_ddr.c | 5 ++++- > drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 1 + > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c > index a87914f2d5..b9300dd6d1 100644 > --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c > +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c > @@ -639,7 +639,8 @@ void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl) > start_sw_done(ctl); > /* quasi-dynamic register update*/ > setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); > - clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN); > + clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN | > + DDRCTRL_PWRCTL_SELFREF_EN); > clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); > wait_sw_done_ack(ctl); > } > @@ -652,6 +653,8 @@ void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, > clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); > if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN) > setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN); > + if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_EN)) > + setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN); > setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); > wait_sw_done_ack(ctl); > } > diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h > index 9d33186b3a..afd93c518e 100644 > --- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h > +++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h > @@ -260,6 +260,7 @@ struct stm32mp1_ddrphy { > > #define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0) > > +#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) > #define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) > #define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) > Acked-by: Patrice Chotard Thanks Patrice Acked-by: Patrice Chotard Thanks Patrice