* [PATCH v6 0/3] irqchip: vf610-mscm: add MSCM interrupt router driver
@ 2015-03-01 22:41 ` Stefan Agner
0 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-01 22:41 UTC (permalink / raw)
To: tglx, jason, mark.rutland
Cc: marc.zyngier, u.kleine-koenig, shawn.guo, kernel, arnd, robh+dt,
pawel.moll, ijc+devicetree, galak, pebolle, linux, devicetree,
linux-arm-kernel, linux-kernel, stefan
So far the MSCM interrupt router was initialized by the boot loader
and configured all interrupts for the Cortex-A5 CPU. There are two
use cases where a proper driver is necessary:
- To run Linux on the Cortex-M4. When the kernel is running on the
non-preconfigured CPU, the interrupt router need to be configured
properly.
- To support deeper sleep modes: LPSTOP clears the interrupt router
configuration, hence a driver needs to restore the configuration
on resume.
Due to the concernes of using "syscon" for the interrupt router
this 4th version uses device tree bindings which split the MSCM
module into sub-modules.
In detail, the registers inside the MSCM module are grouped:
- 0x40001000-0x4000105C: Processor information e.g. CPU ID
- 0x40001800-0x40001820: CPU2CPU directed interrupt registers
- 0x40001880-0x4000195E: The interrupt router registers
- 0x40001C00-0x40001DDC: ACTZS TrustZone registers
This version of the patchset defines bindings for the first submodule
and combines the second and third submodule into one block. However,
the driver currently does not support the CPU2CPU interrupts. The
fourth submodule is completely left out for now.
Due to this and the better documentation the patchset grew by ~40
lines. I think this bindings honer the quite individual functionality
inside the MSCM better.
Still looking for an ack by device tree folks...
Changes since v5
- Remove seperate Kconfig symbol since this driver is presumably only
used on Vybrid
- Warn only if IRQ is already in use by another CPU (avoids spurious
warnings on older boot loaders)
- Rebased on v4.0-rc1
Changes since v4
- Fix config selection in SOC_VF610 (VF610_MSCM => VF610_MSCM_IR)
Changes since v3
- Splitted MSCM bindings: MSCM CPU configuration and interrupt router
- Use syscon to access the CPU configuration registers
- Renamed the driver (irq-vf610-mscm => irq-vf610-mscm-ir)
- Extended general and property description of the bindings
- Rebased on v3.19-rc6
Changes since v2
- Use two cell layout for MSCM interrupt router
- Move peripheral interrupt properties to base device tree vfxxx.dtsi
- Use generic two cell xlate (irq_domain_xlate_twocell)
- Add syscon to compatible string
- Remove some line breaks for better readability
Changes since v1 (part of Vybrid Cortex-M4 support)
- Rewrite with irqdomain hierarchy
- Implemented as proper irqchip and move to driver/irqchip/
- Doesn't work on Cortex-M4 anymore (NVIC as parent is not yet
implemented)
Stefan Agner (3):
irqchip: vf610-mscm-ir: add support for MSCM interrupt router
irqchip: vf610-mscm: dt-bindings: add MSCM bindings
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
.../arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 ++
.../bindings/arm/freescale/fsl,vf610-mscm-ir.txt | 33 ++++
arch/arm/boot/dts/vf500.dtsi | 137 +------------
arch/arm/boot/dts/vfxxx.dtsi | 49 +++++
arch/arm/mach-imx/Kconfig | 1 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-vf610-mscm-ir.c | 212 +++++++++++++++++++++
7 files changed, 314 insertions(+), 133 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
create mode 100644 drivers/irqchip/irq-vf610-mscm-ir.c
--
2.3.0
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v6 0/3] irqchip: vf610-mscm: add MSCM interrupt router driver
@ 2015-03-01 22:41 ` Stefan Agner
0 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-01 22:41 UTC (permalink / raw)
To: linux-arm-kernel
So far the MSCM interrupt router was initialized by the boot loader
and configured all interrupts for the Cortex-A5 CPU. There are two
use cases where a proper driver is necessary:
- To run Linux on the Cortex-M4. When the kernel is running on the
non-preconfigured CPU, the interrupt router need to be configured
properly.
- To support deeper sleep modes: LPSTOP clears the interrupt router
configuration, hence a driver needs to restore the configuration
on resume.
Due to the concernes of using "syscon" for the interrupt router
this 4th version uses device tree bindings which split the MSCM
module into sub-modules.
In detail, the registers inside the MSCM module are grouped:
- 0x40001000-0x4000105C: Processor information e.g. CPU ID
- 0x40001800-0x40001820: CPU2CPU directed interrupt registers
- 0x40001880-0x4000195E: The interrupt router registers
- 0x40001C00-0x40001DDC: ACTZS TrustZone registers
This version of the patchset defines bindings for the first submodule
and combines the second and third submodule into one block. However,
the driver currently does not support the CPU2CPU interrupts. The
fourth submodule is completely left out for now.
Due to this and the better documentation the patchset grew by ~40
lines. I think this bindings honer the quite individual functionality
inside the MSCM better.
Still looking for an ack by device tree folks...
Changes since v5
- Remove seperate Kconfig symbol since this driver is presumably only
used on Vybrid
- Warn only if IRQ is already in use by another CPU (avoids spurious
warnings on older boot loaders)
- Rebased on v4.0-rc1
Changes since v4
- Fix config selection in SOC_VF610 (VF610_MSCM => VF610_MSCM_IR)
Changes since v3
- Splitted MSCM bindings: MSCM CPU configuration and interrupt router
- Use syscon to access the CPU configuration registers
- Renamed the driver (irq-vf610-mscm => irq-vf610-mscm-ir)
- Extended general and property description of the bindings
- Rebased on v3.19-rc6
Changes since v2
- Use two cell layout for MSCM interrupt router
- Move peripheral interrupt properties to base device tree vfxxx.dtsi
- Use generic two cell xlate (irq_domain_xlate_twocell)
- Add syscon to compatible string
- Remove some line breaks for better readability
Changes since v1 (part of Vybrid Cortex-M4 support)
- Rewrite with irqdomain hierarchy
- Implemented as proper irqchip and move to driver/irqchip/
- Doesn't work on Cortex-M4 anymore (NVIC as parent is not yet
implemented)
Stefan Agner (3):
irqchip: vf610-mscm-ir: add support for MSCM interrupt router
irqchip: vf610-mscm: dt-bindings: add MSCM bindings
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
.../arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 ++
.../bindings/arm/freescale/fsl,vf610-mscm-ir.txt | 33 ++++
arch/arm/boot/dts/vf500.dtsi | 137 +------------
arch/arm/boot/dts/vfxxx.dtsi | 49 +++++
arch/arm/mach-imx/Kconfig | 1 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-vf610-mscm-ir.c | 212 +++++++++++++++++++++
7 files changed, 314 insertions(+), 133 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
create mode 100644 drivers/irqchip/irq-vf610-mscm-ir.c
--
2.3.0
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v6 1/3] irqchip: vf610-mscm-ir: add support for MSCM interrupt router
@ 2015-03-01 22:41 ` Stefan Agner
0 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-01 22:41 UTC (permalink / raw)
To: tglx, jason, mark.rutland
Cc: marc.zyngier, u.kleine-koenig, shawn.guo, kernel, arnd, robh+dt,
pawel.moll, ijc+devicetree, galak, pebolle, linux, devicetree,
linux-arm-kernel, linux-kernel, stefan
This adds support for Vybrid's interrupt router. On VF6xx models,
almost all peripherals can be used by either of the two CPU's,
the Cortex-A5 or the Cortex-M4. The interrupt router routes the
peripheral interrupts to the configured CPU.
This IRQ chip driver configures the interrupt router to route
the requested interrupt to the CPU the kernel is running on.
The driver makes use of the irqdomain hierarchy support. The
parent is given by the device tree. This should be one of the
two possible parents either ARM GIC or the ARM NVIC interrupt
controller. The latter is currently not yet supported.
Note that there is no resource control mechnism implemented to
avoid concurrent access of the same peripheral. The user needs
to make sure to use device trees which assign the peripherals
orthogonally. However, this driver warns the user in case the
interrupt is already configured for the other CPU. This provides
a poor man's resource controller.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm/mach-imx/Kconfig | 1 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-vf610-mscm-ir.c | 212 ++++++++++++++++++++++++++++++++++++
3 files changed, 214 insertions(+)
create mode 100644 drivers/irqchip/irq-vf610-mscm-ir.c
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e8627e0..c8dffce 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -631,6 +631,7 @@ config SOC_IMX6SX
config SOC_VF610
bool "Vybrid Family VF610 support"
+ select IRQ_DOMAIN_HIERARCHY
select ARM_GIC
select PINCTRL_VF610
select PL310_ERRATA_769419 if CACHE_L2X0
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 42965d2..9176c76 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o
obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
+obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o
obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
diff --git a/drivers/irqchip/irq-vf610-mscm-ir.c b/drivers/irqchip/irq-vf610-mscm-ir.c
new file mode 100644
index 0000000..9521057
--- /dev/null
+++ b/drivers/irqchip/irq-vf610-mscm-ir.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) 2014-2015 Toradex AG
+ * Author: Stefan Agner <stefan@agner.ch>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ * IRQ chip driver for MSCM interrupt router available on Vybrid SoC's.
+ * The interrupt router is between the CPU's interrupt controller and the
+ * peripheral. The router allows to route the peripheral interrupts to
+ * one of the two available CPU's on Vybrid VF6xx SoC's (Cortex-A5 or
+ * Cortex-M4). The router will be configured transparently on a IRQ
+ * request.
+ *
+ * o All peripheral interrupts of the Vybrid SoC can be routed to
+ * CPU 0, CPU 1 or both. The routing is useful for dual-core
+ * variants of Vybrid SoC such as VF6xx. This driver routes the
+ * requested interrupt to the CPU currently running on.
+ *
+ * o It is required to setup the interrupt router even on single-core
+ * variants of Vybrid.
+ */
+
+#include <linux/cpu_pm.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/mfd/syscon.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/regmap.h>
+
+#include "irqchip.h"
+
+#define MSCM_CPxNUM 0x4
+
+#define MSCM_IRSPRC(n) (0x80 + 2 * (n))
+#define MSCM_IRSPRC_CPEN_MASK 0x3
+
+#define MSCM_IRSPRC_NUM 112
+
+struct vf610_mscm_ir_chip_data {
+ void __iomem *mscm_ir_base;
+ u16 cpu_mask;
+ u16 saved_irsprc[MSCM_IRSPRC_NUM];
+};
+
+static struct vf610_mscm_ir_chip_data *mscm_ir_data;
+
+static inline void vf610_mscm_ir_save(struct vf610_mscm_ir_chip_data *data)
+{
+ int i;
+
+ for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+ data->saved_irsprc[i] = readw_relaxed(data->mscm_ir_base + MSCM_IRSPRC(i));
+}
+
+static inline void vf610_mscm_ir_restore(struct vf610_mscm_ir_chip_data *data)
+{
+ int i;
+
+ for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+ writew_relaxed(data->saved_irsprc[i], data->mscm_ir_base + MSCM_IRSPRC(i));
+}
+
+static int vf610_mscm_ir_notifier(struct notifier_block *self,
+ unsigned long cmd, void *v)
+{
+ switch (cmd) {
+ case CPU_CLUSTER_PM_ENTER:
+ vf610_mscm_ir_save(mscm_ir_data);
+ break;
+ case CPU_CLUSTER_PM_ENTER_FAILED:
+ case CPU_CLUSTER_PM_EXIT:
+ vf610_mscm_ir_restore(mscm_ir_data);
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block mscm_ir_notifier_block = {
+ .notifier_call = vf610_mscm_ir_notifier,
+};
+
+static void vf610_mscm_ir_enable(struct irq_data *data)
+{
+ irq_hw_number_t hwirq = data->hwirq;
+ struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
+ u16 irsprc;
+
+ irsprc = readw_relaxed(chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
+ irsprc &= MSCM_IRSPRC_CPEN_MASK;
+
+ WARN_ON(irsprc & ~chip_data->cpu_mask);
+
+ writew_relaxed(chip_data->cpu_mask,
+ chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
+
+ irq_chip_unmask_parent(data);
+}
+
+static void vf610_mscm_ir_disable(struct irq_data *data)
+{
+ irq_hw_number_t hwirq = data->hwirq;
+ struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
+
+ writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
+
+ irq_chip_mask_parent(data);
+}
+
+static struct irq_chip vf610_mscm_ir_irq_chip = {
+ .name = "mscm-ir",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_enable = vf610_mscm_ir_enable,
+ .irq_disable = vf610_mscm_ir_disable,
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+};
+
+static int vf610_mscm_ir_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *arg)
+{
+ int i;
+ irq_hw_number_t hwirq;
+ struct of_phandle_args *irq_data = arg;
+ struct of_phandle_args gic_data;
+
+ if (irq_data->args_count != 2)
+ return -EINVAL;
+
+ hwirq = irq_data->args[0];
+ for (i = 0; i < nr_irqs; i++)
+ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
+ &vf610_mscm_ir_irq_chip,
+ domain->host_data);
+
+ gic_data.np = domain->parent->of_node;
+ gic_data.args_count = 3;
+ gic_data.args[0] = GIC_SPI;
+ gic_data.args[1] = irq_data->args[0];
+ gic_data.args[2] = irq_data->args[1];
+ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
+}
+
+static const struct irq_domain_ops mscm_irq_domain_ops = {
+ .xlate = irq_domain_xlate_twocell,
+ .alloc = vf610_mscm_ir_domain_alloc,
+ .free = irq_domain_free_irqs_common,
+};
+
+static int __init vf610_mscm_ir_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_domain *domain, *domain_parent;
+ struct regmap *mscm_cp_regmap;
+ int ret, cpuid;
+
+ domain_parent = irq_find_host(parent);
+ if (!domain_parent) {
+ pr_err("vf610_mscm_ir: interrupt-parent not found\n");
+ return -EINVAL;
+ }
+
+ mscm_ir_data = kzalloc(sizeof(*mscm_ir_data), GFP_KERNEL);
+ if (!mscm_ir_data)
+ return -ENOMEM;
+
+ mscm_ir_data->mscm_ir_base = of_io_request_and_map(node, 0, "mscm-ir");
+
+ if (!mscm_ir_data->mscm_ir_base) {
+ pr_err("vf610_mscm_ir: unable to map mscm register\n");
+ ret = -ENOMEM;
+ goto out_free;
+ }
+
+ mscm_cp_regmap = syscon_regmap_lookup_by_phandle(node, "fsl,cpucfg");
+ if (IS_ERR(mscm_cp_regmap)) {
+ ret = PTR_ERR(mscm_cp_regmap);
+ pr_err("vf610_mscm_ir: regmap lookup for cpucfg failed\n");
+ goto out_unmap;
+ }
+
+ regmap_read(mscm_cp_regmap, MSCM_CPxNUM, &cpuid);
+ mscm_ir_data->cpu_mask = 0x1 << cpuid;
+
+ domain = irq_domain_add_hierarchy(domain_parent, 0,
+ MSCM_IRSPRC_NUM, node,
+ &mscm_irq_domain_ops, mscm_ir_data);
+ if (!domain) {
+ ret = -ENOMEM;
+ goto out_unmap;
+ }
+
+ cpu_pm_register_notifier(&mscm_ir_notifier_block);
+
+ return 0;
+
+out_unmap:
+ iounmap(mscm_ir_data->mscm_ir_base);
+out_free:
+ kfree(mscm_ir_data);
+ return ret;
+}
+IRQCHIP_DECLARE(vf610_mscm_ir, "fsl,vf610-mscm-ir", vf610_mscm_ir_of_init);
--
2.3.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v6 1/3] irqchip: vf610-mscm-ir: add support for MSCM interrupt router
@ 2015-03-01 22:41 ` Stefan Agner
0 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-01 22:41 UTC (permalink / raw)
To: tglx-hfZtesqFncYOwBW4kG4KsQ, jason-NLaQJdtUoK4Be96aLqz0jA,
mark.rutland-5wv7dgnIgG8
Cc: marc.zyngier-5wv7dgnIgG8, u.kleine-koenig-bIcnvbaLZ9MEGnE8C9+IrQ,
shawn.guo-QSEj5FYQhm4dnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
arnd-r2nGTMty4D4, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
pawel.moll-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, pebolle-IWqWACnzNjzz+pZb47iToQ,
linux-lFZ/pmaqli7XmaaqVzeoHQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, stefan-XLVq0VzYD2Y
This adds support for Vybrid's interrupt router. On VF6xx models,
almost all peripherals can be used by either of the two CPU's,
the Cortex-A5 or the Cortex-M4. The interrupt router routes the
peripheral interrupts to the configured CPU.
This IRQ chip driver configures the interrupt router to route
the requested interrupt to the CPU the kernel is running on.
The driver makes use of the irqdomain hierarchy support. The
parent is given by the device tree. This should be one of the
two possible parents either ARM GIC or the ARM NVIC interrupt
controller. The latter is currently not yet supported.
Note that there is no resource control mechnism implemented to
avoid concurrent access of the same peripheral. The user needs
to make sure to use device trees which assign the peripherals
orthogonally. However, this driver warns the user in case the
interrupt is already configured for the other CPU. This provides
a poor man's resource controller.
Acked-by: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
Signed-off-by: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org>
---
arch/arm/mach-imx/Kconfig | 1 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-vf610-mscm-ir.c | 212 ++++++++++++++++++++++++++++++++++++
3 files changed, 214 insertions(+)
create mode 100644 drivers/irqchip/irq-vf610-mscm-ir.c
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e8627e0..c8dffce 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -631,6 +631,7 @@ config SOC_IMX6SX
config SOC_VF610
bool "Vybrid Family VF610 support"
+ select IRQ_DOMAIN_HIERARCHY
select ARM_GIC
select PINCTRL_VF610
select PL310_ERRATA_769419 if CACHE_L2X0
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 42965d2..9176c76 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o
obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
+obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o
obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
diff --git a/drivers/irqchip/irq-vf610-mscm-ir.c b/drivers/irqchip/irq-vf610-mscm-ir.c
new file mode 100644
index 0000000..9521057
--- /dev/null
+++ b/drivers/irqchip/irq-vf610-mscm-ir.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) 2014-2015 Toradex AG
+ * Author: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ * IRQ chip driver for MSCM interrupt router available on Vybrid SoC's.
+ * The interrupt router is between the CPU's interrupt controller and the
+ * peripheral. The router allows to route the peripheral interrupts to
+ * one of the two available CPU's on Vybrid VF6xx SoC's (Cortex-A5 or
+ * Cortex-M4). The router will be configured transparently on a IRQ
+ * request.
+ *
+ * o All peripheral interrupts of the Vybrid SoC can be routed to
+ * CPU 0, CPU 1 or both. The routing is useful for dual-core
+ * variants of Vybrid SoC such as VF6xx. This driver routes the
+ * requested interrupt to the CPU currently running on.
+ *
+ * o It is required to setup the interrupt router even on single-core
+ * variants of Vybrid.
+ */
+
+#include <linux/cpu_pm.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/mfd/syscon.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/regmap.h>
+
+#include "irqchip.h"
+
+#define MSCM_CPxNUM 0x4
+
+#define MSCM_IRSPRC(n) (0x80 + 2 * (n))
+#define MSCM_IRSPRC_CPEN_MASK 0x3
+
+#define MSCM_IRSPRC_NUM 112
+
+struct vf610_mscm_ir_chip_data {
+ void __iomem *mscm_ir_base;
+ u16 cpu_mask;
+ u16 saved_irsprc[MSCM_IRSPRC_NUM];
+};
+
+static struct vf610_mscm_ir_chip_data *mscm_ir_data;
+
+static inline void vf610_mscm_ir_save(struct vf610_mscm_ir_chip_data *data)
+{
+ int i;
+
+ for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+ data->saved_irsprc[i] = readw_relaxed(data->mscm_ir_base + MSCM_IRSPRC(i));
+}
+
+static inline void vf610_mscm_ir_restore(struct vf610_mscm_ir_chip_data *data)
+{
+ int i;
+
+ for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+ writew_relaxed(data->saved_irsprc[i], data->mscm_ir_base + MSCM_IRSPRC(i));
+}
+
+static int vf610_mscm_ir_notifier(struct notifier_block *self,
+ unsigned long cmd, void *v)
+{
+ switch (cmd) {
+ case CPU_CLUSTER_PM_ENTER:
+ vf610_mscm_ir_save(mscm_ir_data);
+ break;
+ case CPU_CLUSTER_PM_ENTER_FAILED:
+ case CPU_CLUSTER_PM_EXIT:
+ vf610_mscm_ir_restore(mscm_ir_data);
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block mscm_ir_notifier_block = {
+ .notifier_call = vf610_mscm_ir_notifier,
+};
+
+static void vf610_mscm_ir_enable(struct irq_data *data)
+{
+ irq_hw_number_t hwirq = data->hwirq;
+ struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
+ u16 irsprc;
+
+ irsprc = readw_relaxed(chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
+ irsprc &= MSCM_IRSPRC_CPEN_MASK;
+
+ WARN_ON(irsprc & ~chip_data->cpu_mask);
+
+ writew_relaxed(chip_data->cpu_mask,
+ chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
+
+ irq_chip_unmask_parent(data);
+}
+
+static void vf610_mscm_ir_disable(struct irq_data *data)
+{
+ irq_hw_number_t hwirq = data->hwirq;
+ struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
+
+ writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
+
+ irq_chip_mask_parent(data);
+}
+
+static struct irq_chip vf610_mscm_ir_irq_chip = {
+ .name = "mscm-ir",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_enable = vf610_mscm_ir_enable,
+ .irq_disable = vf610_mscm_ir_disable,
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+};
+
+static int vf610_mscm_ir_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *arg)
+{
+ int i;
+ irq_hw_number_t hwirq;
+ struct of_phandle_args *irq_data = arg;
+ struct of_phandle_args gic_data;
+
+ if (irq_data->args_count != 2)
+ return -EINVAL;
+
+ hwirq = irq_data->args[0];
+ for (i = 0; i < nr_irqs; i++)
+ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
+ &vf610_mscm_ir_irq_chip,
+ domain->host_data);
+
+ gic_data.np = domain->parent->of_node;
+ gic_data.args_count = 3;
+ gic_data.args[0] = GIC_SPI;
+ gic_data.args[1] = irq_data->args[0];
+ gic_data.args[2] = irq_data->args[1];
+ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
+}
+
+static const struct irq_domain_ops mscm_irq_domain_ops = {
+ .xlate = irq_domain_xlate_twocell,
+ .alloc = vf610_mscm_ir_domain_alloc,
+ .free = irq_domain_free_irqs_common,
+};
+
+static int __init vf610_mscm_ir_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_domain *domain, *domain_parent;
+ struct regmap *mscm_cp_regmap;
+ int ret, cpuid;
+
+ domain_parent = irq_find_host(parent);
+ if (!domain_parent) {
+ pr_err("vf610_mscm_ir: interrupt-parent not found\n");
+ return -EINVAL;
+ }
+
+ mscm_ir_data = kzalloc(sizeof(*mscm_ir_data), GFP_KERNEL);
+ if (!mscm_ir_data)
+ return -ENOMEM;
+
+ mscm_ir_data->mscm_ir_base = of_io_request_and_map(node, 0, "mscm-ir");
+
+ if (!mscm_ir_data->mscm_ir_base) {
+ pr_err("vf610_mscm_ir: unable to map mscm register\n");
+ ret = -ENOMEM;
+ goto out_free;
+ }
+
+ mscm_cp_regmap = syscon_regmap_lookup_by_phandle(node, "fsl,cpucfg");
+ if (IS_ERR(mscm_cp_regmap)) {
+ ret = PTR_ERR(mscm_cp_regmap);
+ pr_err("vf610_mscm_ir: regmap lookup for cpucfg failed\n");
+ goto out_unmap;
+ }
+
+ regmap_read(mscm_cp_regmap, MSCM_CPxNUM, &cpuid);
+ mscm_ir_data->cpu_mask = 0x1 << cpuid;
+
+ domain = irq_domain_add_hierarchy(domain_parent, 0,
+ MSCM_IRSPRC_NUM, node,
+ &mscm_irq_domain_ops, mscm_ir_data);
+ if (!domain) {
+ ret = -ENOMEM;
+ goto out_unmap;
+ }
+
+ cpu_pm_register_notifier(&mscm_ir_notifier_block);
+
+ return 0;
+
+out_unmap:
+ iounmap(mscm_ir_data->mscm_ir_base);
+out_free:
+ kfree(mscm_ir_data);
+ return ret;
+}
+IRQCHIP_DECLARE(vf610_mscm_ir, "fsl,vf610-mscm-ir", vf610_mscm_ir_of_init);
--
2.3.0
--
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^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v6 1/3] irqchip: vf610-mscm-ir: add support for MSCM interrupt router
@ 2015-03-01 22:41 ` Stefan Agner
0 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-01 22:41 UTC (permalink / raw)
To: linux-arm-kernel
This adds support for Vybrid's interrupt router. On VF6xx models,
almost all peripherals can be used by either of the two CPU's,
the Cortex-A5 or the Cortex-M4. The interrupt router routes the
peripheral interrupts to the configured CPU.
This IRQ chip driver configures the interrupt router to route
the requested interrupt to the CPU the kernel is running on.
The driver makes use of the irqdomain hierarchy support. The
parent is given by the device tree. This should be one of the
two possible parents either ARM GIC or the ARM NVIC interrupt
controller. The latter is currently not yet supported.
Note that there is no resource control mechnism implemented to
avoid concurrent access of the same peripheral. The user needs
to make sure to use device trees which assign the peripherals
orthogonally. However, this driver warns the user in case the
interrupt is already configured for the other CPU. This provides
a poor man's resource controller.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm/mach-imx/Kconfig | 1 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-vf610-mscm-ir.c | 212 ++++++++++++++++++++++++++++++++++++
3 files changed, 214 insertions(+)
create mode 100644 drivers/irqchip/irq-vf610-mscm-ir.c
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e8627e0..c8dffce 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -631,6 +631,7 @@ config SOC_IMX6SX
config SOC_VF610
bool "Vybrid Family VF610 support"
+ select IRQ_DOMAIN_HIERARCHY
select ARM_GIC
select PINCTRL_VF610
select PL310_ERRATA_769419 if CACHE_L2X0
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 42965d2..9176c76 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o
obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
+obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o
obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
diff --git a/drivers/irqchip/irq-vf610-mscm-ir.c b/drivers/irqchip/irq-vf610-mscm-ir.c
new file mode 100644
index 0000000..9521057
--- /dev/null
+++ b/drivers/irqchip/irq-vf610-mscm-ir.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) 2014-2015 Toradex AG
+ * Author: Stefan Agner <stefan@agner.ch>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ * IRQ chip driver for MSCM interrupt router available on Vybrid SoC's.
+ * The interrupt router is between the CPU's interrupt controller and the
+ * peripheral. The router allows to route the peripheral interrupts to
+ * one of the two available CPU's on Vybrid VF6xx SoC's (Cortex-A5 or
+ * Cortex-M4). The router will be configured transparently on a IRQ
+ * request.
+ *
+ * o All peripheral interrupts of the Vybrid SoC can be routed to
+ * CPU 0, CPU 1 or both. The routing is useful for dual-core
+ * variants of Vybrid SoC such as VF6xx. This driver routes the
+ * requested interrupt to the CPU currently running on.
+ *
+ * o It is required to setup the interrupt router even on single-core
+ * variants of Vybrid.
+ */
+
+#include <linux/cpu_pm.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/mfd/syscon.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/regmap.h>
+
+#include "irqchip.h"
+
+#define MSCM_CPxNUM 0x4
+
+#define MSCM_IRSPRC(n) (0x80 + 2 * (n))
+#define MSCM_IRSPRC_CPEN_MASK 0x3
+
+#define MSCM_IRSPRC_NUM 112
+
+struct vf610_mscm_ir_chip_data {
+ void __iomem *mscm_ir_base;
+ u16 cpu_mask;
+ u16 saved_irsprc[MSCM_IRSPRC_NUM];
+};
+
+static struct vf610_mscm_ir_chip_data *mscm_ir_data;
+
+static inline void vf610_mscm_ir_save(struct vf610_mscm_ir_chip_data *data)
+{
+ int i;
+
+ for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+ data->saved_irsprc[i] = readw_relaxed(data->mscm_ir_base + MSCM_IRSPRC(i));
+}
+
+static inline void vf610_mscm_ir_restore(struct vf610_mscm_ir_chip_data *data)
+{
+ int i;
+
+ for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+ writew_relaxed(data->saved_irsprc[i], data->mscm_ir_base + MSCM_IRSPRC(i));
+}
+
+static int vf610_mscm_ir_notifier(struct notifier_block *self,
+ unsigned long cmd, void *v)
+{
+ switch (cmd) {
+ case CPU_CLUSTER_PM_ENTER:
+ vf610_mscm_ir_save(mscm_ir_data);
+ break;
+ case CPU_CLUSTER_PM_ENTER_FAILED:
+ case CPU_CLUSTER_PM_EXIT:
+ vf610_mscm_ir_restore(mscm_ir_data);
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block mscm_ir_notifier_block = {
+ .notifier_call = vf610_mscm_ir_notifier,
+};
+
+static void vf610_mscm_ir_enable(struct irq_data *data)
+{
+ irq_hw_number_t hwirq = data->hwirq;
+ struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
+ u16 irsprc;
+
+ irsprc = readw_relaxed(chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
+ irsprc &= MSCM_IRSPRC_CPEN_MASK;
+
+ WARN_ON(irsprc & ~chip_data->cpu_mask);
+
+ writew_relaxed(chip_data->cpu_mask,
+ chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
+
+ irq_chip_unmask_parent(data);
+}
+
+static void vf610_mscm_ir_disable(struct irq_data *data)
+{
+ irq_hw_number_t hwirq = data->hwirq;
+ struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
+
+ writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
+
+ irq_chip_mask_parent(data);
+}
+
+static struct irq_chip vf610_mscm_ir_irq_chip = {
+ .name = "mscm-ir",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_enable = vf610_mscm_ir_enable,
+ .irq_disable = vf610_mscm_ir_disable,
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+};
+
+static int vf610_mscm_ir_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *arg)
+{
+ int i;
+ irq_hw_number_t hwirq;
+ struct of_phandle_args *irq_data = arg;
+ struct of_phandle_args gic_data;
+
+ if (irq_data->args_count != 2)
+ return -EINVAL;
+
+ hwirq = irq_data->args[0];
+ for (i = 0; i < nr_irqs; i++)
+ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
+ &vf610_mscm_ir_irq_chip,
+ domain->host_data);
+
+ gic_data.np = domain->parent->of_node;
+ gic_data.args_count = 3;
+ gic_data.args[0] = GIC_SPI;
+ gic_data.args[1] = irq_data->args[0];
+ gic_data.args[2] = irq_data->args[1];
+ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
+}
+
+static const struct irq_domain_ops mscm_irq_domain_ops = {
+ .xlate = irq_domain_xlate_twocell,
+ .alloc = vf610_mscm_ir_domain_alloc,
+ .free = irq_domain_free_irqs_common,
+};
+
+static int __init vf610_mscm_ir_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_domain *domain, *domain_parent;
+ struct regmap *mscm_cp_regmap;
+ int ret, cpuid;
+
+ domain_parent = irq_find_host(parent);
+ if (!domain_parent) {
+ pr_err("vf610_mscm_ir: interrupt-parent not found\n");
+ return -EINVAL;
+ }
+
+ mscm_ir_data = kzalloc(sizeof(*mscm_ir_data), GFP_KERNEL);
+ if (!mscm_ir_data)
+ return -ENOMEM;
+
+ mscm_ir_data->mscm_ir_base = of_io_request_and_map(node, 0, "mscm-ir");
+
+ if (!mscm_ir_data->mscm_ir_base) {
+ pr_err("vf610_mscm_ir: unable to map mscm register\n");
+ ret = -ENOMEM;
+ goto out_free;
+ }
+
+ mscm_cp_regmap = syscon_regmap_lookup_by_phandle(node, "fsl,cpucfg");
+ if (IS_ERR(mscm_cp_regmap)) {
+ ret = PTR_ERR(mscm_cp_regmap);
+ pr_err("vf610_mscm_ir: regmap lookup for cpucfg failed\n");
+ goto out_unmap;
+ }
+
+ regmap_read(mscm_cp_regmap, MSCM_CPxNUM, &cpuid);
+ mscm_ir_data->cpu_mask = 0x1 << cpuid;
+
+ domain = irq_domain_add_hierarchy(domain_parent, 0,
+ MSCM_IRSPRC_NUM, node,
+ &mscm_irq_domain_ops, mscm_ir_data);
+ if (!domain) {
+ ret = -ENOMEM;
+ goto out_unmap;
+ }
+
+ cpu_pm_register_notifier(&mscm_ir_notifier_block);
+
+ return 0;
+
+out_unmap:
+ iounmap(mscm_ir_data->mscm_ir_base);
+out_free:
+ kfree(mscm_ir_data);
+ return ret;
+}
+IRQCHIP_DECLARE(vf610_mscm_ir, "fsl,vf610-mscm-ir", vf610_mscm_ir_of_init);
--
2.3.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v6 2/3] irqchip: vf610-mscm: dt-bindings: add MSCM bindings
2015-03-01 22:41 ` Stefan Agner
@ 2015-03-01 22:41 ` Stefan Agner
-1 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-01 22:41 UTC (permalink / raw)
To: tglx, jason, mark.rutland
Cc: marc.zyngier, u.kleine-koenig, shawn.guo, kernel, arnd, robh+dt,
pawel.moll, ijc+devicetree, galak, pebolle, linux, devicetree,
linux-arm-kernel, linux-kernel, stefan
Add binding documentation for CPU configuration and interrupt router
submodule of the Miscellaneous System Control Module. The MSCM is
used in all variants of Freescale Vybrid SoC's.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
.../arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 +++++++++
.../bindings/arm/freescale/fsl,vf610-mscm-ir.txt | 33 ++++++++++++++++++++++
2 files changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
new file mode 100644
index 0000000..44aa3c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
@@ -0,0 +1,14 @@
+Freescale Vybrid Miscellaneous System Control - CPU Configuration
+
+The MSCM IP contains multiple sub modules, this binding describes the first
+block of registers which contains CPU configuration information.
+
+Required properties:
+- compatible: "fsl,vf610-mscm-cpucfg", "syscon"
+- reg: the register range of the MSCM CPU configuration registers
+
+Example:
+ mscm_cpucfg: cpucfg@40001000 {
+ compatible = "fsl,vf610-mscm-cpucfg", "syscon";
+ reg = <0x40001000 0x800>;
+ }
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
new file mode 100644
index 0000000..669808b2a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
@@ -0,0 +1,33 @@
+Freescale Vybrid Miscellaneous System Control - Interrupt Router
+
+The MSCM IP contains multiple sub modules, this binding describes the second
+block of registers which control the interrupt router. The interrupt router
+allows to configure the recipient of each peripheral interrupt. Furthermore
+it controls the directed processor interrupts. The module is available in all
+Vybrid SoC's but is only really useful in dual core configurations (VF6xx
+which comes with a Cortex-A5/Cortex-M4 combination).
+
+Required properties:
+- compatible: "fsl,vf610-mscm-ir"
+- reg: the register range of the MSCM Interrupt Router
+- fsl,cpucfg: The handle to the MSCM CPU configuration node, required
+ to get the current CPU ID
+- interrupt-controller: Identifies the node as an interrupt controller
+- #interrupt-cells: Two cells, interrupt number and cells.
+ The hardware interrupt number according to interrupt
+ assignment of the interrupt router is required.
+ Flags get passed only when using GIC as parent. Flags
+ encoding as documented by the GIC bindings.
+- interrupt-parent: Should be the phandle for the interrupt controller of
+ the CPU the device tree is intended to be used on. This
+ is either the node of the GIC or NVIC controller.
+
+Example:
+ mscm_ir: interrupt-controller@40001800 {
+ compatible = "fsl,vf610-mscm-ir";
+ reg = <0x40001800 0x400>;
+ fsl,cpucfg = <&mscm_cpucfg>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ }
--
2.3.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v6 2/3] irqchip: vf610-mscm: dt-bindings: add MSCM bindings
@ 2015-03-01 22:41 ` Stefan Agner
0 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-01 22:41 UTC (permalink / raw)
To: linux-arm-kernel
Add binding documentation for CPU configuration and interrupt router
submodule of the Miscellaneous System Control Module. The MSCM is
used in all variants of Freescale Vybrid SoC's.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
.../arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 +++++++++
.../bindings/arm/freescale/fsl,vf610-mscm-ir.txt | 33 ++++++++++++++++++++++
2 files changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
new file mode 100644
index 0000000..44aa3c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
@@ -0,0 +1,14 @@
+Freescale Vybrid Miscellaneous System Control - CPU Configuration
+
+The MSCM IP contains multiple sub modules, this binding describes the first
+block of registers which contains CPU configuration information.
+
+Required properties:
+- compatible: "fsl,vf610-mscm-cpucfg", "syscon"
+- reg: the register range of the MSCM CPU configuration registers
+
+Example:
+ mscm_cpucfg: cpucfg at 40001000 {
+ compatible = "fsl,vf610-mscm-cpucfg", "syscon";
+ reg = <0x40001000 0x800>;
+ }
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
new file mode 100644
index 0000000..669808b2a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
@@ -0,0 +1,33 @@
+Freescale Vybrid Miscellaneous System Control - Interrupt Router
+
+The MSCM IP contains multiple sub modules, this binding describes the second
+block of registers which control the interrupt router. The interrupt router
+allows to configure the recipient of each peripheral interrupt. Furthermore
+it controls the directed processor interrupts. The module is available in all
+Vybrid SoC's but is only really useful in dual core configurations (VF6xx
+which comes with a Cortex-A5/Cortex-M4 combination).
+
+Required properties:
+- compatible: "fsl,vf610-mscm-ir"
+- reg: the register range of the MSCM Interrupt Router
+- fsl,cpucfg: The handle to the MSCM CPU configuration node, required
+ to get the current CPU ID
+- interrupt-controller: Identifies the node as an interrupt controller
+- #interrupt-cells: Two cells, interrupt number and cells.
+ The hardware interrupt number according to interrupt
+ assignment of the interrupt router is required.
+ Flags get passed only when using GIC as parent. Flags
+ encoding as documented by the GIC bindings.
+- interrupt-parent: Should be the phandle for the interrupt controller of
+ the CPU the device tree is intended to be used on. This
+ is either the node of the GIC or NVIC controller.
+
+Example:
+ mscm_ir: interrupt-controller at 40001800 {
+ compatible = "fsl,vf610-mscm-ir";
+ reg = <0x40001800 0x400>;
+ fsl,cpucfg = <&mscm_cpucfg>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ }
--
2.3.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
@ 2015-03-01 22:41 ` Stefan Agner
0 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-01 22:41 UTC (permalink / raw)
To: tglx, jason, mark.rutland
Cc: marc.zyngier, u.kleine-koenig, shawn.guo, kernel, arnd, robh+dt,
pawel.moll, ijc+devicetree, galak, pebolle, linux, devicetree,
linux-arm-kernel, linux-kernel, stefan
Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoC's. This module contains registers
to get information of the individual and current (accessing)
CPU. In a second block, there is an interrupt router, which
handles the routing of the interrupts between the two CPU cores
on VF6xx variants of the SoC. However, also on single core
variants the interrupt router needs to be configured in order
to receive interrupts on the CPU's interrupt controller. Almost
all peripheral interrupts are routed through the router, hence
the MSCM module is the default interrupt parent for this SoC.
In a earlier commit the interrupt nodes were moved out of the
peripheral nodes and specified in the CPU specific vf500.dtsi
device tree. This allowed to use the base device tree vfxxx.dtsi
also for a Cortex-M4 specific device tree, which uses different
interrupt nodes due to the NVIC interrupt controller. However,
since the interrupt parent for peripherals is the MSCM module
independently which CPU the device tree is used for, we can move
the interrupt nodes into the base device tree vfxxx.dtsi again.
Depending on which CPU this base device tree will be used with,
the correct parent interrupt controller has to be assigned to
the MSCM-IR node (GIC or NVIC). The driver takes care of the
parent interrupt controller specific needs (interrupt-cells).
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm/boot/dts/vf500.dtsi | 137 ++-----------------------------------------
arch/arm/boot/dts/vfxxx.dtsi | 49 ++++++++++++++++
2 files changed, 53 insertions(+), 133 deletions(-)
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index 1dbf8d2..e976d2f 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -24,14 +24,13 @@
};
soc {
- interrupt-parent = <&intc>;
-
aips-bus@40000000 {
intc: interrupt-controller@40002000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
+ interrupt-parent = <&intc>;
reg = <0x40003000 0x1000>,
<0x40002100 0x100>;
};
@@ -40,145 +39,17 @@
compatible = "arm,cortex-a9-global-timer";
reg = <0x40002200 0x20>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
clocks = <&clks VF610_CLK_PLATFORM_BUS>;
};
};
};
};
-&adc0 {
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&adc1 {
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&can0 {
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&can1 {
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&dspi0 {
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&edma0 {
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma-tx", "edma-err";
-};
-
-&edma1 {
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma-tx", "edma-err";
-};
-
-&esdhc1 {
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&fec0 {
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&fec1 {
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&ftm {
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio0 {
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio1 {
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio2 {
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio3 {
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio4 {
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&i2c0 {
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&pit {
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&qspi0 {
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&sai2 {
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&snvsrtc {
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&src {
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart0 {
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart1 {
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart2 {
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart3 {
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart4 {
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart5 {
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbdev0 {
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbh1 {
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbphy0 {
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbphy1 {
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+&mscm_ir {
+ interrupt-parent = <&intc>;
};
&wdoga5 {
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index a29c7ce..32de809 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -54,6 +54,7 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
+ interrupt-parent = <&mscm_ir>;
ranges;
aips0: aips-bus@40000000 {
@@ -62,6 +63,19 @@
#size-cells = <1>;
ranges;
+ mscm_cpucfg: cpucfg@40001000 {
+ compatible = "fsl,vf610-mscm-cpucfg", "syscon";
+ reg = <0x40001000 0x800>;
+ };
+
+ mscm_ir: interrupt-controller@40001800 {
+ compatible = "fsl,vf610-mscm-ir";
+ reg = <0x40001800 0x400>;
+ fsl,cpucfg = <&mscm_cpucfg>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
edma0: dma-controller@40018000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
@@ -69,6 +83,9 @@
<0x40024000 0x1000>,
<0x40025000 0x1000>;
dma-channels = <32>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
+ <9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX0>,
<&clks VF610_CLK_DMAMUX1>;
@@ -78,6 +95,7 @@
can0: flexcan@40020000 {
compatible = "fsl,vf610-flexcan";
reg = <0x40020000 0x4000>;
+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_FLEXCAN0>,
<&clks VF610_CLK_FLEXCAN0>;
clock-names = "ipg", "per";
@@ -87,6 +105,7 @@
uart0: serial@40027000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40027000 0x1000>;
+ interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART0>;
clock-names = "ipg";
dmas = <&edma0 0 2>,
@@ -98,6 +117,7 @@
uart1: serial@40028000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40028000 0x1000>;
+ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART1>;
clock-names = "ipg";
dmas = <&edma0 0 4>,
@@ -109,6 +129,7 @@
uart2: serial@40029000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40029000 0x1000>;
+ interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART2>;
clock-names = "ipg";
dmas = <&edma0 0 6>,
@@ -120,6 +141,7 @@
uart3: serial@4002a000 {
compatible = "fsl,vf610-lpuart";
reg = <0x4002a000 0x1000>;
+ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART3>;
clock-names = "ipg";
dmas = <&edma0 0 8>,
@@ -133,6 +155,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002c000 0x1000>;
+ interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DSPI0>;
clock-names = "dspi";
spi-num-chipselects = <5>;
@@ -142,6 +165,7 @@
sai2: sai@40031000 {
compatible = "fsl,vf610-sai";
reg = <0x40031000 0x1000>;
+ interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SAI2>;
clock-names = "sai";
dma-names = "tx", "rx";
@@ -153,6 +177,7 @@
pit: pit@40037000 {
compatible = "fsl,vf610-pit";
reg = <0x40037000 0x1000>;
+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_PIT>;
clock-names = "pit";
};
@@ -186,6 +211,7 @@
adc0: adc@4003b000 {
compatible = "fsl,vf610-adc";
reg = <0x4003b000 0x1000>;
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ADC0>;
clock-names = "adc";
status = "disabled";
@@ -194,6 +220,7 @@
wdoga5: wdog@4003e000 {
compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
reg = <0x4003e000 0x1000>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_WDT>;
clock-names = "wdog";
status = "disabled";
@@ -204,6 +231,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
reg = <0x40044000 0x1000>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_QSPI0_EN>,
<&clks VF610_CLK_QSPI0>;
clock-names = "qspi_en", "qspi";
@@ -221,6 +249,7 @@
reg = <0x40049000 0x1000 0x400ff000 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 0 32>;
@@ -231,6 +260,7 @@
reg = <0x4004a000 0x1000 0x400ff040 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 32 32>;
@@ -241,6 +271,7 @@
reg = <0x4004b000 0x1000 0x400ff080 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 64 32>;
@@ -251,6 +282,7 @@
reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 96 32>;
@@ -261,6 +293,7 @@
reg = <0x4004d000 0x1000 0x400ff100 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 128 7>;
@@ -274,6 +307,7 @@
usbphy0: usbphy@40050800 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050800 0x400>;
+ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBPHY0>;
fsl,anatop = <&anatop>;
status = "disabled";
@@ -282,6 +316,7 @@
usbphy1: usbphy@40050c00 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050c00 0x400>;
+ interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBPHY1>;
fsl,anatop = <&anatop>;
status = "disabled";
@@ -292,6 +327,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
+ interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_I2C0>;
clock-names = "ipg";
dmas = <&edma0 0 50>,
@@ -311,6 +347,7 @@
usbdev0: usb@40034000 {
compatible = "fsl,vf610-usb", "fsl,imx27-usb";
reg = <0x40034000 0x800>;
+ interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBC0>;
fsl,usbphy = <&usbphy0>;
fsl,usbmisc = <&usbmisc0 0>;
@@ -345,6 +382,9 @@
<0x400a1000 0x1000>,
<0x400a2000 0x1000>;
dma-channels = <32>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
+ <11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX2>,
<&clks VF610_CLK_DMAMUX3>;
@@ -368,6 +408,7 @@
uart4: serial@400a9000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400a9000 0x1000>;
+ interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART4>;
clock-names = "ipg";
status = "disabled";
@@ -376,6 +417,7 @@
uart5: serial@400aa000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400aa000 0x1000>;
+ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART5>;
clock-names = "ipg";
status = "disabled";
@@ -384,6 +426,7 @@
adc1: adc@400bb000 {
compatible = "fsl,vf610-adc";
reg = <0x400bb000 0x1000>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ADC1>;
clock-names = "adc";
status = "disabled";
@@ -392,6 +435,7 @@
esdhc1: esdhc@400b2000 {
compatible = "fsl,imx53-esdhc";
reg = <0x400b2000 0x1000>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_IPG_BUS>,
<&clks VF610_CLK_PLATFORM_BUS>,
<&clks VF610_CLK_ESDHC1>;
@@ -402,6 +446,7 @@
usbh1: usb@400b4000 {
compatible = "fsl,vf610-usb", "fsl,imx27-usb";
reg = <0x400b4000 0x800>;
+ interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBC1>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
@@ -420,6 +465,7 @@
ftm: ftm@400b8000 {
compatible = "fsl,ftm-timer";
reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ftm-evt", "ftm-src",
"ftm-evt-counter-en", "ftm-src-counter-en";
clocks = <&clks VF610_CLK_FTM2>,
@@ -432,6 +478,7 @@
fec0: ethernet@400d0000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d0000 0x1000>;
+ interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET>;
@@ -442,6 +489,7 @@
fec1: ethernet@400d1000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d1000 0x1000>;
+ interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET>;
@@ -452,6 +500,7 @@
can1: flexcan@400d4000 {
compatible = "fsl,vf610-flexcan";
reg = <0x400d4000 0x4000>;
+ interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_FLEXCAN1>,
<&clks VF610_CLK_FLEXCAN1>;
clock-names = "ipg", "per";
--
2.3.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
@ 2015-03-01 22:41 ` Stefan Agner
0 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-01 22:41 UTC (permalink / raw)
To: tglx-hfZtesqFncYOwBW4kG4KsQ, jason-NLaQJdtUoK4Be96aLqz0jA,
mark.rutland-5wv7dgnIgG8
Cc: marc.zyngier-5wv7dgnIgG8, u.kleine-koenig-bIcnvbaLZ9MEGnE8C9+IrQ,
shawn.guo-QSEj5FYQhm4dnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
arnd-r2nGTMty4D4, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
pawel.moll-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, pebolle-IWqWACnzNjzz+pZb47iToQ,
linux-lFZ/pmaqli7XmaaqVzeoHQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, stefan-XLVq0VzYD2Y
Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoC's. This module contains registers
to get information of the individual and current (accessing)
CPU. In a second block, there is an interrupt router, which
handles the routing of the interrupts between the two CPU cores
on VF6xx variants of the SoC. However, also on single core
variants the interrupt router needs to be configured in order
to receive interrupts on the CPU's interrupt controller. Almost
all peripheral interrupts are routed through the router, hence
the MSCM module is the default interrupt parent for this SoC.
In a earlier commit the interrupt nodes were moved out of the
peripheral nodes and specified in the CPU specific vf500.dtsi
device tree. This allowed to use the base device tree vfxxx.dtsi
also for a Cortex-M4 specific device tree, which uses different
interrupt nodes due to the NVIC interrupt controller. However,
since the interrupt parent for peripherals is the MSCM module
independently which CPU the device tree is used for, we can move
the interrupt nodes into the base device tree vfxxx.dtsi again.
Depending on which CPU this base device tree will be used with,
the correct parent interrupt controller has to be assigned to
the MSCM-IR node (GIC or NVIC). The driver takes care of the
parent interrupt controller specific needs (interrupt-cells).
Acked-by: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
Signed-off-by: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org>
---
arch/arm/boot/dts/vf500.dtsi | 137 ++-----------------------------------------
arch/arm/boot/dts/vfxxx.dtsi | 49 ++++++++++++++++
2 files changed, 53 insertions(+), 133 deletions(-)
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index 1dbf8d2..e976d2f 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -24,14 +24,13 @@
};
soc {
- interrupt-parent = <&intc>;
-
aips-bus@40000000 {
intc: interrupt-controller@40002000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
+ interrupt-parent = <&intc>;
reg = <0x40003000 0x1000>,
<0x40002100 0x100>;
};
@@ -40,145 +39,17 @@
compatible = "arm,cortex-a9-global-timer";
reg = <0x40002200 0x20>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
clocks = <&clks VF610_CLK_PLATFORM_BUS>;
};
};
};
};
-&adc0 {
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&adc1 {
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&can0 {
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&can1 {
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&dspi0 {
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&edma0 {
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma-tx", "edma-err";
-};
-
-&edma1 {
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma-tx", "edma-err";
-};
-
-&esdhc1 {
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&fec0 {
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&fec1 {
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&ftm {
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio0 {
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio1 {
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio2 {
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio3 {
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio4 {
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&i2c0 {
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&pit {
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&qspi0 {
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&sai2 {
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&snvsrtc {
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&src {
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart0 {
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart1 {
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart2 {
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart3 {
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart4 {
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart5 {
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbdev0 {
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbh1 {
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbphy0 {
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbphy1 {
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+&mscm_ir {
+ interrupt-parent = <&intc>;
};
&wdoga5 {
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index a29c7ce..32de809 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -54,6 +54,7 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
+ interrupt-parent = <&mscm_ir>;
ranges;
aips0: aips-bus@40000000 {
@@ -62,6 +63,19 @@
#size-cells = <1>;
ranges;
+ mscm_cpucfg: cpucfg@40001000 {
+ compatible = "fsl,vf610-mscm-cpucfg", "syscon";
+ reg = <0x40001000 0x800>;
+ };
+
+ mscm_ir: interrupt-controller@40001800 {
+ compatible = "fsl,vf610-mscm-ir";
+ reg = <0x40001800 0x400>;
+ fsl,cpucfg = <&mscm_cpucfg>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
edma0: dma-controller@40018000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
@@ -69,6 +83,9 @@
<0x40024000 0x1000>,
<0x40025000 0x1000>;
dma-channels = <32>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
+ <9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX0>,
<&clks VF610_CLK_DMAMUX1>;
@@ -78,6 +95,7 @@
can0: flexcan@40020000 {
compatible = "fsl,vf610-flexcan";
reg = <0x40020000 0x4000>;
+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_FLEXCAN0>,
<&clks VF610_CLK_FLEXCAN0>;
clock-names = "ipg", "per";
@@ -87,6 +105,7 @@
uart0: serial@40027000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40027000 0x1000>;
+ interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART0>;
clock-names = "ipg";
dmas = <&edma0 0 2>,
@@ -98,6 +117,7 @@
uart1: serial@40028000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40028000 0x1000>;
+ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART1>;
clock-names = "ipg";
dmas = <&edma0 0 4>,
@@ -109,6 +129,7 @@
uart2: serial@40029000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40029000 0x1000>;
+ interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART2>;
clock-names = "ipg";
dmas = <&edma0 0 6>,
@@ -120,6 +141,7 @@
uart3: serial@4002a000 {
compatible = "fsl,vf610-lpuart";
reg = <0x4002a000 0x1000>;
+ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART3>;
clock-names = "ipg";
dmas = <&edma0 0 8>,
@@ -133,6 +155,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002c000 0x1000>;
+ interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DSPI0>;
clock-names = "dspi";
spi-num-chipselects = <5>;
@@ -142,6 +165,7 @@
sai2: sai@40031000 {
compatible = "fsl,vf610-sai";
reg = <0x40031000 0x1000>;
+ interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SAI2>;
clock-names = "sai";
dma-names = "tx", "rx";
@@ -153,6 +177,7 @@
pit: pit@40037000 {
compatible = "fsl,vf610-pit";
reg = <0x40037000 0x1000>;
+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_PIT>;
clock-names = "pit";
};
@@ -186,6 +211,7 @@
adc0: adc@4003b000 {
compatible = "fsl,vf610-adc";
reg = <0x4003b000 0x1000>;
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ADC0>;
clock-names = "adc";
status = "disabled";
@@ -194,6 +220,7 @@
wdoga5: wdog@4003e000 {
compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
reg = <0x4003e000 0x1000>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_WDT>;
clock-names = "wdog";
status = "disabled";
@@ -204,6 +231,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
reg = <0x40044000 0x1000>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_QSPI0_EN>,
<&clks VF610_CLK_QSPI0>;
clock-names = "qspi_en", "qspi";
@@ -221,6 +249,7 @@
reg = <0x40049000 0x1000 0x400ff000 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 0 32>;
@@ -231,6 +260,7 @@
reg = <0x4004a000 0x1000 0x400ff040 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 32 32>;
@@ -241,6 +271,7 @@
reg = <0x4004b000 0x1000 0x400ff080 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 64 32>;
@@ -251,6 +282,7 @@
reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 96 32>;
@@ -261,6 +293,7 @@
reg = <0x4004d000 0x1000 0x400ff100 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 128 7>;
@@ -274,6 +307,7 @@
usbphy0: usbphy@40050800 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050800 0x400>;
+ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBPHY0>;
fsl,anatop = <&anatop>;
status = "disabled";
@@ -282,6 +316,7 @@
usbphy1: usbphy@40050c00 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050c00 0x400>;
+ interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBPHY1>;
fsl,anatop = <&anatop>;
status = "disabled";
@@ -292,6 +327,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
+ interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_I2C0>;
clock-names = "ipg";
dmas = <&edma0 0 50>,
@@ -311,6 +347,7 @@
usbdev0: usb@40034000 {
compatible = "fsl,vf610-usb", "fsl,imx27-usb";
reg = <0x40034000 0x800>;
+ interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBC0>;
fsl,usbphy = <&usbphy0>;
fsl,usbmisc = <&usbmisc0 0>;
@@ -345,6 +382,9 @@
<0x400a1000 0x1000>,
<0x400a2000 0x1000>;
dma-channels = <32>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
+ <11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX2>,
<&clks VF610_CLK_DMAMUX3>;
@@ -368,6 +408,7 @@
uart4: serial@400a9000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400a9000 0x1000>;
+ interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART4>;
clock-names = "ipg";
status = "disabled";
@@ -376,6 +417,7 @@
uart5: serial@400aa000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400aa000 0x1000>;
+ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART5>;
clock-names = "ipg";
status = "disabled";
@@ -384,6 +426,7 @@
adc1: adc@400bb000 {
compatible = "fsl,vf610-adc";
reg = <0x400bb000 0x1000>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ADC1>;
clock-names = "adc";
status = "disabled";
@@ -392,6 +435,7 @@
esdhc1: esdhc@400b2000 {
compatible = "fsl,imx53-esdhc";
reg = <0x400b2000 0x1000>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_IPG_BUS>,
<&clks VF610_CLK_PLATFORM_BUS>,
<&clks VF610_CLK_ESDHC1>;
@@ -402,6 +446,7 @@
usbh1: usb@400b4000 {
compatible = "fsl,vf610-usb", "fsl,imx27-usb";
reg = <0x400b4000 0x800>;
+ interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBC1>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
@@ -420,6 +465,7 @@
ftm: ftm@400b8000 {
compatible = "fsl,ftm-timer";
reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ftm-evt", "ftm-src",
"ftm-evt-counter-en", "ftm-src-counter-en";
clocks = <&clks VF610_CLK_FTM2>,
@@ -432,6 +478,7 @@
fec0: ethernet@400d0000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d0000 0x1000>;
+ interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET>;
@@ -442,6 +489,7 @@
fec1: ethernet@400d1000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d1000 0x1000>;
+ interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET>;
@@ -452,6 +500,7 @@
can1: flexcan@400d4000 {
compatible = "fsl,vf610-flexcan";
reg = <0x400d4000 0x4000>;
+ interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_FLEXCAN1>,
<&clks VF610_CLK_FLEXCAN1>;
clock-names = "ipg", "per";
--
2.3.0
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^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
@ 2015-03-01 22:41 ` Stefan Agner
0 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-01 22:41 UTC (permalink / raw)
To: linux-arm-kernel
Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoC's. This module contains registers
to get information of the individual and current (accessing)
CPU. In a second block, there is an interrupt router, which
handles the routing of the interrupts between the two CPU cores
on VF6xx variants of the SoC. However, also on single core
variants the interrupt router needs to be configured in order
to receive interrupts on the CPU's interrupt controller. Almost
all peripheral interrupts are routed through the router, hence
the MSCM module is the default interrupt parent for this SoC.
In a earlier commit the interrupt nodes were moved out of the
peripheral nodes and specified in the CPU specific vf500.dtsi
device tree. This allowed to use the base device tree vfxxx.dtsi
also for a Cortex-M4 specific device tree, which uses different
interrupt nodes due to the NVIC interrupt controller. However,
since the interrupt parent for peripherals is the MSCM module
independently which CPU the device tree is used for, we can move
the interrupt nodes into the base device tree vfxxx.dtsi again.
Depending on which CPU this base device tree will be used with,
the correct parent interrupt controller has to be assigned to
the MSCM-IR node (GIC or NVIC). The driver takes care of the
parent interrupt controller specific needs (interrupt-cells).
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm/boot/dts/vf500.dtsi | 137 ++-----------------------------------------
arch/arm/boot/dts/vfxxx.dtsi | 49 ++++++++++++++++
2 files changed, 53 insertions(+), 133 deletions(-)
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index 1dbf8d2..e976d2f 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -24,14 +24,13 @@
};
soc {
- interrupt-parent = <&intc>;
-
aips-bus at 40000000 {
intc: interrupt-controller at 40002000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
+ interrupt-parent = <&intc>;
reg = <0x40003000 0x1000>,
<0x40002100 0x100>;
};
@@ -40,145 +39,17 @@
compatible = "arm,cortex-a9-global-timer";
reg = <0x40002200 0x20>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
clocks = <&clks VF610_CLK_PLATFORM_BUS>;
};
};
};
};
-&adc0 {
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&adc1 {
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&can0 {
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&can1 {
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&dspi0 {
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&edma0 {
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma-tx", "edma-err";
-};
-
-&edma1 {
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma-tx", "edma-err";
-};
-
-&esdhc1 {
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&fec0 {
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&fec1 {
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&ftm {
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio0 {
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio1 {
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio2 {
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio3 {
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio4 {
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&i2c0 {
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&pit {
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&qspi0 {
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&sai2 {
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&snvsrtc {
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&src {
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart0 {
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart1 {
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart2 {
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart3 {
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart4 {
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart5 {
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbdev0 {
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbh1 {
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbphy0 {
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbphy1 {
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+&mscm_ir {
+ interrupt-parent = <&intc>;
};
&wdoga5 {
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index a29c7ce..32de809 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -54,6 +54,7 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
+ interrupt-parent = <&mscm_ir>;
ranges;
aips0: aips-bus at 40000000 {
@@ -62,6 +63,19 @@
#size-cells = <1>;
ranges;
+ mscm_cpucfg: cpucfg at 40001000 {
+ compatible = "fsl,vf610-mscm-cpucfg", "syscon";
+ reg = <0x40001000 0x800>;
+ };
+
+ mscm_ir: interrupt-controller at 40001800 {
+ compatible = "fsl,vf610-mscm-ir";
+ reg = <0x40001800 0x400>;
+ fsl,cpucfg = <&mscm_cpucfg>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
edma0: dma-controller at 40018000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
@@ -69,6 +83,9 @@
<0x40024000 0x1000>,
<0x40025000 0x1000>;
dma-channels = <32>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
+ <9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX0>,
<&clks VF610_CLK_DMAMUX1>;
@@ -78,6 +95,7 @@
can0: flexcan at 40020000 {
compatible = "fsl,vf610-flexcan";
reg = <0x40020000 0x4000>;
+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_FLEXCAN0>,
<&clks VF610_CLK_FLEXCAN0>;
clock-names = "ipg", "per";
@@ -87,6 +105,7 @@
uart0: serial at 40027000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40027000 0x1000>;
+ interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART0>;
clock-names = "ipg";
dmas = <&edma0 0 2>,
@@ -98,6 +117,7 @@
uart1: serial at 40028000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40028000 0x1000>;
+ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART1>;
clock-names = "ipg";
dmas = <&edma0 0 4>,
@@ -109,6 +129,7 @@
uart2: serial at 40029000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40029000 0x1000>;
+ interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART2>;
clock-names = "ipg";
dmas = <&edma0 0 6>,
@@ -120,6 +141,7 @@
uart3: serial at 4002a000 {
compatible = "fsl,vf610-lpuart";
reg = <0x4002a000 0x1000>;
+ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART3>;
clock-names = "ipg";
dmas = <&edma0 0 8>,
@@ -133,6 +155,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002c000 0x1000>;
+ interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DSPI0>;
clock-names = "dspi";
spi-num-chipselects = <5>;
@@ -142,6 +165,7 @@
sai2: sai at 40031000 {
compatible = "fsl,vf610-sai";
reg = <0x40031000 0x1000>;
+ interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SAI2>;
clock-names = "sai";
dma-names = "tx", "rx";
@@ -153,6 +177,7 @@
pit: pit at 40037000 {
compatible = "fsl,vf610-pit";
reg = <0x40037000 0x1000>;
+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_PIT>;
clock-names = "pit";
};
@@ -186,6 +211,7 @@
adc0: adc at 4003b000 {
compatible = "fsl,vf610-adc";
reg = <0x4003b000 0x1000>;
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ADC0>;
clock-names = "adc";
status = "disabled";
@@ -194,6 +220,7 @@
wdoga5: wdog at 4003e000 {
compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
reg = <0x4003e000 0x1000>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_WDT>;
clock-names = "wdog";
status = "disabled";
@@ -204,6 +231,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
reg = <0x40044000 0x1000>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_QSPI0_EN>,
<&clks VF610_CLK_QSPI0>;
clock-names = "qspi_en", "qspi";
@@ -221,6 +249,7 @@
reg = <0x40049000 0x1000 0x400ff000 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 0 32>;
@@ -231,6 +260,7 @@
reg = <0x4004a000 0x1000 0x400ff040 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 32 32>;
@@ -241,6 +271,7 @@
reg = <0x4004b000 0x1000 0x400ff080 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 64 32>;
@@ -251,6 +282,7 @@
reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 96 32>;
@@ -261,6 +293,7 @@
reg = <0x4004d000 0x1000 0x400ff100 0x40>;
gpio-controller;
#gpio-cells = <2>;
+ interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 128 7>;
@@ -274,6 +307,7 @@
usbphy0: usbphy at 40050800 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050800 0x400>;
+ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBPHY0>;
fsl,anatop = <&anatop>;
status = "disabled";
@@ -282,6 +316,7 @@
usbphy1: usbphy at 40050c00 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050c00 0x400>;
+ interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBPHY1>;
fsl,anatop = <&anatop>;
status = "disabled";
@@ -292,6 +327,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
+ interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_I2C0>;
clock-names = "ipg";
dmas = <&edma0 0 50>,
@@ -311,6 +347,7 @@
usbdev0: usb at 40034000 {
compatible = "fsl,vf610-usb", "fsl,imx27-usb";
reg = <0x40034000 0x800>;
+ interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBC0>;
fsl,usbphy = <&usbphy0>;
fsl,usbmisc = <&usbmisc0 0>;
@@ -345,6 +382,9 @@
<0x400a1000 0x1000>,
<0x400a2000 0x1000>;
dma-channels = <32>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
+ <11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX2>,
<&clks VF610_CLK_DMAMUX3>;
@@ -368,6 +408,7 @@
uart4: serial at 400a9000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400a9000 0x1000>;
+ interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART4>;
clock-names = "ipg";
status = "disabled";
@@ -376,6 +417,7 @@
uart5: serial at 400aa000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400aa000 0x1000>;
+ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_UART5>;
clock-names = "ipg";
status = "disabled";
@@ -384,6 +426,7 @@
adc1: adc at 400bb000 {
compatible = "fsl,vf610-adc";
reg = <0x400bb000 0x1000>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ADC1>;
clock-names = "adc";
status = "disabled";
@@ -392,6 +435,7 @@
esdhc1: esdhc at 400b2000 {
compatible = "fsl,imx53-esdhc";
reg = <0x400b2000 0x1000>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_IPG_BUS>,
<&clks VF610_CLK_PLATFORM_BUS>,
<&clks VF610_CLK_ESDHC1>;
@@ -402,6 +446,7 @@
usbh1: usb at 400b4000 {
compatible = "fsl,vf610-usb", "fsl,imx27-usb";
reg = <0x400b4000 0x800>;
+ interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBC1>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
@@ -420,6 +465,7 @@
ftm: ftm at 400b8000 {
compatible = "fsl,ftm-timer";
reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ftm-evt", "ftm-src",
"ftm-evt-counter-en", "ftm-src-counter-en";
clocks = <&clks VF610_CLK_FTM2>,
@@ -432,6 +478,7 @@
fec0: ethernet at 400d0000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d0000 0x1000>;
+ interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET>;
@@ -442,6 +489,7 @@
fec1: ethernet at 400d1000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d1000 0x1000>;
+ interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET>;
@@ -452,6 +500,7 @@
can1: flexcan at 400d4000 {
compatible = "fsl,vf610-flexcan";
reg = <0x400d4000 0x4000>;
+ interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_FLEXCAN1>,
<&clks VF610_CLK_FLEXCAN1>;
clock-names = "ipg", "per";
--
2.3.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH v6 0/3] irqchip: vf610-mscm: add MSCM interrupt router driver
2015-03-01 22:41 ` Stefan Agner
(?)
@ 2015-03-08 5:31 ` Jason Cooper
-1 siblings, 0 replies; 30+ messages in thread
From: Jason Cooper @ 2015-03-08 5:31 UTC (permalink / raw)
To: Stefan Agner
Cc: tglx, mark.rutland, marc.zyngier, u.kleine-koenig, shawn.guo,
kernel, arnd, robh+dt, pawel.moll, ijc+devicetree, galak,
pebolle, linux, devicetree, linux-arm-kernel, linux-kernel
On Sun, Mar 01, 2015 at 11:41:26PM +0100, Stefan Agner wrote:
...
> Stefan Agner (3):
> irqchip: vf610-mscm-ir: add support for MSCM interrupt router
> irqchip: vf610-mscm: dt-bindings: add MSCM bindings
> ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
>
> .../arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 ++
> .../bindings/arm/freescale/fsl,vf610-mscm-ir.txt | 33 ++++
> arch/arm/boot/dts/vf500.dtsi | 137 +------------
> arch/arm/boot/dts/vfxxx.dtsi | 49 +++++
> arch/arm/mach-imx/Kconfig | 1 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-vf610-mscm-ir.c | 212 +++++++++++++++++++++
> 7 files changed, 314 insertions(+), 133 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
> create mode 100644 drivers/irqchip/irq-vf610-mscm-ir.c
Applied patches 1 and 2 to irqchip/vybrid. Please let me know if you need to
base other work off of this.
thx,
Jason.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v6 0/3] irqchip: vf610-mscm: add MSCM interrupt router driver
@ 2015-03-08 5:31 ` Jason Cooper
0 siblings, 0 replies; 30+ messages in thread
From: Jason Cooper @ 2015-03-08 5:31 UTC (permalink / raw)
To: Stefan Agner
Cc: mark.rutland, devicetree, pebolle, linux, pawel.moll, arnd,
ijc+devicetree, marc.zyngier, galak, linux-kernel, robh+dt,
kernel, u.kleine-koenig, tglx, shawn.guo, linux-arm-kernel
On Sun, Mar 01, 2015 at 11:41:26PM +0100, Stefan Agner wrote:
...
> Stefan Agner (3):
> irqchip: vf610-mscm-ir: add support for MSCM interrupt router
> irqchip: vf610-mscm: dt-bindings: add MSCM bindings
> ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
>
> .../arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 ++
> .../bindings/arm/freescale/fsl,vf610-mscm-ir.txt | 33 ++++
> arch/arm/boot/dts/vf500.dtsi | 137 +------------
> arch/arm/boot/dts/vfxxx.dtsi | 49 +++++
> arch/arm/mach-imx/Kconfig | 1 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-vf610-mscm-ir.c | 212 +++++++++++++++++++++
> 7 files changed, 314 insertions(+), 133 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
> create mode 100644 drivers/irqchip/irq-vf610-mscm-ir.c
Applied patches 1 and 2 to irqchip/vybrid. Please let me know if you need to
base other work off of this.
thx,
Jason.
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v6 0/3] irqchip: vf610-mscm: add MSCM interrupt router driver
@ 2015-03-08 5:31 ` Jason Cooper
0 siblings, 0 replies; 30+ messages in thread
From: Jason Cooper @ 2015-03-08 5:31 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Mar 01, 2015 at 11:41:26PM +0100, Stefan Agner wrote:
...
> Stefan Agner (3):
> irqchip: vf610-mscm-ir: add support for MSCM interrupt router
> irqchip: vf610-mscm: dt-bindings: add MSCM bindings
> ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
>
> .../arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 ++
> .../bindings/arm/freescale/fsl,vf610-mscm-ir.txt | 33 ++++
> arch/arm/boot/dts/vf500.dtsi | 137 +------------
> arch/arm/boot/dts/vfxxx.dtsi | 49 +++++
> arch/arm/mach-imx/Kconfig | 1 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-vf610-mscm-ir.c | 212 +++++++++++++++++++++
> 7 files changed, 314 insertions(+), 133 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
> create mode 100644 drivers/irqchip/irq-vf610-mscm-ir.c
Applied patches 1 and 2 to irqchip/vybrid. Please let me know if you need to
base other work off of this.
thx,
Jason.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v6 0/3] irqchip: vf610-mscm: add MSCM interrupt router driver
2015-03-08 5:31 ` Jason Cooper
@ 2015-03-08 23:43 ` Stefan Agner
-1 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-08 23:43 UTC (permalink / raw)
To: Jason Cooper
Cc: tglx, mark.rutland, marc.zyngier, u.kleine-koenig, shawn.guo,
kernel, arnd, robh+dt, pawel.moll, ijc+devicetree, galak,
pebolle, linux, devicetree, linux-arm-kernel, linux-kernel
On 2015-03-08 06:31, Jason Cooper wrote:
> On Sun, Mar 01, 2015 at 11:41:26PM +0100, Stefan Agner wrote:
> ...
>> Stefan Agner (3):
>> irqchip: vf610-mscm-ir: add support for MSCM interrupt router
>> irqchip: vf610-mscm: dt-bindings: add MSCM bindings
>> ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
>>
>> .../arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 ++
>> .../bindings/arm/freescale/fsl,vf610-mscm-ir.txt | 33 ++++
>> arch/arm/boot/dts/vf500.dtsi | 137 +------------
>> arch/arm/boot/dts/vfxxx.dtsi | 49 +++++
>> arch/arm/mach-imx/Kconfig | 1 +
>> drivers/irqchip/Makefile | 1 +
>> drivers/irqchip/irq-vf610-mscm-ir.c | 212 +++++++++++++++++++++
>> 7 files changed, 314 insertions(+), 133 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
>> create mode 100644 drivers/irqchip/irq-vf610-mscm-ir.c
>
> Applied patches 1 and 2 to irqchip/vybrid. Please let me know if you need to
> base other work off of this.
Thx. Some patches in the patchset to run Linux on the Cortex-M4 of
Vybrid is based on this driver. I will post a rebased version of that
probably tomorrow.
--
Stefan
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v6 0/3] irqchip: vf610-mscm: add MSCM interrupt router driver
@ 2015-03-08 23:43 ` Stefan Agner
0 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-08 23:43 UTC (permalink / raw)
To: linux-arm-kernel
On 2015-03-08 06:31, Jason Cooper wrote:
> On Sun, Mar 01, 2015 at 11:41:26PM +0100, Stefan Agner wrote:
> ...
>> Stefan Agner (3):
>> irqchip: vf610-mscm-ir: add support for MSCM interrupt router
>> irqchip: vf610-mscm: dt-bindings: add MSCM bindings
>> ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
>>
>> .../arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 ++
>> .../bindings/arm/freescale/fsl,vf610-mscm-ir.txt | 33 ++++
>> arch/arm/boot/dts/vf500.dtsi | 137 +------------
>> arch/arm/boot/dts/vfxxx.dtsi | 49 +++++
>> arch/arm/mach-imx/Kconfig | 1 +
>> drivers/irqchip/Makefile | 1 +
>> drivers/irqchip/irq-vf610-mscm-ir.c | 212 +++++++++++++++++++++
>> 7 files changed, 314 insertions(+), 133 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
>> create mode 100644 drivers/irqchip/irq-vf610-mscm-ir.c
>
> Applied patches 1 and 2 to irqchip/vybrid. Please let me know if you need to
> base other work off of this.
Thx. Some patches in the patchset to run Linux on the Cortex-M4 of
Vybrid is based on this driver. I will post a rebased version of that
probably tomorrow.
--
Stefan
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v6 0/3] irqchip: vf610-mscm: add MSCM interrupt router driver
2015-03-08 23:43 ` Stefan Agner
(?)
@ 2015-03-09 1:22 ` Jason Cooper
-1 siblings, 0 replies; 30+ messages in thread
From: Jason Cooper @ 2015-03-09 1:22 UTC (permalink / raw)
To: Stefan Agner
Cc: tglx, mark.rutland, marc.zyngier, u.kleine-koenig, shawn.guo,
kernel, arnd, robh+dt, pawel.moll, ijc+devicetree, galak,
pebolle, linux, devicetree, linux-arm-kernel, linux-kernel
On Mon, Mar 09, 2015 at 12:43:56AM +0100, Stefan Agner wrote:
> On 2015-03-08 06:31, Jason Cooper wrote:
> > On Sun, Mar 01, 2015 at 11:41:26PM +0100, Stefan Agner wrote:
> > ...
> >> Stefan Agner (3):
> >> irqchip: vf610-mscm-ir: add support for MSCM interrupt router
> >> irqchip: vf610-mscm: dt-bindings: add MSCM bindings
> >> ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
> >>
> >> .../arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 ++
> >> .../bindings/arm/freescale/fsl,vf610-mscm-ir.txt | 33 ++++
> >> arch/arm/boot/dts/vf500.dtsi | 137 +------------
> >> arch/arm/boot/dts/vfxxx.dtsi | 49 +++++
> >> arch/arm/mach-imx/Kconfig | 1 +
> >> drivers/irqchip/Makefile | 1 +
> >> drivers/irqchip/irq-vf610-mscm-ir.c | 212 +++++++++++++++++++++
> >> 7 files changed, 314 insertions(+), 133 deletions(-)
> >> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
> >> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
> >> create mode 100644 drivers/irqchip/irq-vf610-mscm-ir.c
> >
> > Applied patches 1 and 2 to irqchip/vybrid. Please let me know if you need to
> > base other work off of this.
>
> Thx. Some patches in the patchset to run Linux on the Cortex-M4 of
> Vybrid is based on this driver. I will post a rebased version of that
> probably tomorrow.
What I meant, is: will you be submitting patches which have build or runtime
dependencies on this branch? If so, I'll make sure to leave irqchip/vybrid up
after I pull it into irqchip/core so that patches going into other trees and
can depend on it.
It's no extra work on my part, I just need to know not to clean it up ;-)
thx,
Jason.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v6 0/3] irqchip: vf610-mscm: add MSCM interrupt router driver
@ 2015-03-09 1:22 ` Jason Cooper
0 siblings, 0 replies; 30+ messages in thread
From: Jason Cooper @ 2015-03-09 1:22 UTC (permalink / raw)
To: Stefan Agner
Cc: mark.rutland, devicetree, pebolle, linux, pawel.moll, arnd,
ijc+devicetree, marc.zyngier, galak, linux-kernel, robh+dt,
kernel, u.kleine-koenig, tglx, shawn.guo, linux-arm-kernel
On Mon, Mar 09, 2015 at 12:43:56AM +0100, Stefan Agner wrote:
> On 2015-03-08 06:31, Jason Cooper wrote:
> > On Sun, Mar 01, 2015 at 11:41:26PM +0100, Stefan Agner wrote:
> > ...
> >> Stefan Agner (3):
> >> irqchip: vf610-mscm-ir: add support for MSCM interrupt router
> >> irqchip: vf610-mscm: dt-bindings: add MSCM bindings
> >> ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
> >>
> >> .../arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 ++
> >> .../bindings/arm/freescale/fsl,vf610-mscm-ir.txt | 33 ++++
> >> arch/arm/boot/dts/vf500.dtsi | 137 +------------
> >> arch/arm/boot/dts/vfxxx.dtsi | 49 +++++
> >> arch/arm/mach-imx/Kconfig | 1 +
> >> drivers/irqchip/Makefile | 1 +
> >> drivers/irqchip/irq-vf610-mscm-ir.c | 212 +++++++++++++++++++++
> >> 7 files changed, 314 insertions(+), 133 deletions(-)
> >> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
> >> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
> >> create mode 100644 drivers/irqchip/irq-vf610-mscm-ir.c
> >
> > Applied patches 1 and 2 to irqchip/vybrid. Please let me know if you need to
> > base other work off of this.
>
> Thx. Some patches in the patchset to run Linux on the Cortex-M4 of
> Vybrid is based on this driver. I will post a rebased version of that
> probably tomorrow.
What I meant, is: will you be submitting patches which have build or runtime
dependencies on this branch? If so, I'll make sure to leave irqchip/vybrid up
after I pull it into irqchip/core so that patches going into other trees and
can depend on it.
It's no extra work on my part, I just need to know not to clean it up ;-)
thx,
Jason.
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v6 0/3] irqchip: vf610-mscm: add MSCM interrupt router driver
@ 2015-03-09 1:22 ` Jason Cooper
0 siblings, 0 replies; 30+ messages in thread
From: Jason Cooper @ 2015-03-09 1:22 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Mar 09, 2015 at 12:43:56AM +0100, Stefan Agner wrote:
> On 2015-03-08 06:31, Jason Cooper wrote:
> > On Sun, Mar 01, 2015 at 11:41:26PM +0100, Stefan Agner wrote:
> > ...
> >> Stefan Agner (3):
> >> irqchip: vf610-mscm-ir: add support for MSCM interrupt router
> >> irqchip: vf610-mscm: dt-bindings: add MSCM bindings
> >> ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
> >>
> >> .../arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 ++
> >> .../bindings/arm/freescale/fsl,vf610-mscm-ir.txt | 33 ++++
> >> arch/arm/boot/dts/vf500.dtsi | 137 +------------
> >> arch/arm/boot/dts/vfxxx.dtsi | 49 +++++
> >> arch/arm/mach-imx/Kconfig | 1 +
> >> drivers/irqchip/Makefile | 1 +
> >> drivers/irqchip/irq-vf610-mscm-ir.c | 212 +++++++++++++++++++++
> >> 7 files changed, 314 insertions(+), 133 deletions(-)
> >> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
> >> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
> >> create mode 100644 drivers/irqchip/irq-vf610-mscm-ir.c
> >
> > Applied patches 1 and 2 to irqchip/vybrid. Please let me know if you need to
> > base other work off of this.
>
> Thx. Some patches in the patchset to run Linux on the Cortex-M4 of
> Vybrid is based on this driver. I will post a rebased version of that
> probably tomorrow.
What I meant, is: will you be submitting patches which have build or runtime
dependencies on this branch? If so, I'll make sure to leave irqchip/vybrid up
after I pull it into irqchip/core so that patches going into other trees and
can depend on it.
It's no extra work on my part, I just need to know not to clean it up ;-)
thx,
Jason.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
2015-03-01 22:41 ` Stefan Agner
@ 2015-03-11 0:48 ` Shawn Guo
-1 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2015-03-11 0:48 UTC (permalink / raw)
To: Stefan Agner
Cc: tglx, jason, mark.rutland, marc.zyngier, u.kleine-koenig, kernel,
arnd, robh+dt, pawel.moll, ijc+devicetree, galak, pebolle, linux,
devicetree, linux-arm-kernel, linux-kernel
On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
> Add the Miscellaneous System Control Module (MSCM) to the base
> device tree for Vybrid SoC's. This module contains registers
> to get information of the individual and current (accessing)
> CPU. In a second block, there is an interrupt router, which
> handles the routing of the interrupts between the two CPU cores
> on VF6xx variants of the SoC. However, also on single core
> variants the interrupt router needs to be configured in order
> to receive interrupts on the CPU's interrupt controller. Almost
> all peripheral interrupts are routed through the router, hence
> the MSCM module is the default interrupt parent for this SoC.
>
> In a earlier commit the interrupt nodes were moved out of the
> peripheral nodes and specified in the CPU specific vf500.dtsi
> device tree. This allowed to use the base device tree vfxxx.dtsi
> also for a Cortex-M4 specific device tree, which uses different
> interrupt nodes due to the NVIC interrupt controller. However,
> since the interrupt parent for peripherals is the MSCM module
> independently which CPU the device tree is used for, we can move
> the interrupt nodes into the base device tree vfxxx.dtsi again.
> Depending on which CPU this base device tree will be used with,
> the correct parent interrupt controller has to be assigned to
> the MSCM-IR node (GIC or NVIC). The driver takes care of the
> parent interrupt controller specific needs (interrupt-cells).
>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
Stefan,
I guess this patch has a run-time dependency on the first two in the
series, right? Or put it another way, if I apply this single patch on
my branch, the dtb and kernel built from the same branch do not work
together, right? If so, we will need to either wait for the first two
hit mainline or pull Jason's irqchip/vybrid branch into my tree as
prerequisite (irqchip/vybrid needs to be stable).
Shawn
> ---
> arch/arm/boot/dts/vf500.dtsi | 137 ++-----------------------------------------
> arch/arm/boot/dts/vfxxx.dtsi | 49 ++++++++++++++++
> 2 files changed, 53 insertions(+), 133 deletions(-)
>
> diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
> index 1dbf8d2..e976d2f 100644
> --- a/arch/arm/boot/dts/vf500.dtsi
> +++ b/arch/arm/boot/dts/vf500.dtsi
> @@ -24,14 +24,13 @@
> };
>
> soc {
> - interrupt-parent = <&intc>;
> -
> aips-bus@40000000 {
>
> intc: interrupt-controller@40002000 {
> compatible = "arm,cortex-a9-gic";
> #interrupt-cells = <3>;
> interrupt-controller;
> + interrupt-parent = <&intc>;
> reg = <0x40003000 0x1000>,
> <0x40002100 0x100>;
> };
> @@ -40,145 +39,17 @@
> compatible = "arm,cortex-a9-global-timer";
> reg = <0x40002200 0x20>;
> interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&intc>;
> clocks = <&clks VF610_CLK_PLATFORM_BUS>;
> };
> };
> };
> };
>
> -&adc0 {
> - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&adc1 {
> - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&can0 {
> - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&can1 {
> - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&dspi0 {
> - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&edma0 {
> - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "edma-tx", "edma-err";
> -};
> -
> -&edma1 {
> - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "edma-tx", "edma-err";
> -};
> -
> -&esdhc1 {
> - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&fec0 {
> - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&fec1 {
> - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&ftm {
> - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&gpio0 {
> - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&gpio1 {
> - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&gpio2 {
> - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&gpio3 {
> - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&gpio4 {
> - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&i2c0 {
> - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&pit {
> - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&qspi0 {
> - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&sai2 {
> - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&snvsrtc {
> - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&src {
> - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&uart0 {
> - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&uart1 {
> - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&uart2 {
> - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&uart3 {
> - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&uart4 {
> - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&uart5 {
> - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&usbdev0 {
> - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&usbh1 {
> - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&usbphy0 {
> - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&usbphy1 {
> - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +&mscm_ir {
> + interrupt-parent = <&intc>;
> };
>
> &wdoga5 {
> - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> status = "okay";
> };
> diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
> index a29c7ce..32de809 100644
> --- a/arch/arm/boot/dts/vfxxx.dtsi
> +++ b/arch/arm/boot/dts/vfxxx.dtsi
> @@ -54,6 +54,7 @@
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "simple-bus";
> + interrupt-parent = <&mscm_ir>;
> ranges;
>
> aips0: aips-bus@40000000 {
> @@ -62,6 +63,19 @@
> #size-cells = <1>;
> ranges;
>
> + mscm_cpucfg: cpucfg@40001000 {
> + compatible = "fsl,vf610-mscm-cpucfg", "syscon";
> + reg = <0x40001000 0x800>;
> + };
> +
> + mscm_ir: interrupt-controller@40001800 {
> + compatible = "fsl,vf610-mscm-ir";
> + reg = <0x40001800 0x400>;
> + fsl,cpucfg = <&mscm_cpucfg>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> edma0: dma-controller@40018000 {
> #dma-cells = <2>;
> compatible = "fsl,vf610-edma";
> @@ -69,6 +83,9 @@
> <0x40024000 0x1000>,
> <0x40025000 0x1000>;
> dma-channels = <32>;
> + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
> + <9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "edma-tx", "edma-err";
> clock-names = "dmamux0", "dmamux1";
> clocks = <&clks VF610_CLK_DMAMUX0>,
> <&clks VF610_CLK_DMAMUX1>;
> @@ -78,6 +95,7 @@
> can0: flexcan@40020000 {
> compatible = "fsl,vf610-flexcan";
> reg = <0x40020000 0x4000>;
> + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_FLEXCAN0>,
> <&clks VF610_CLK_FLEXCAN0>;
> clock-names = "ipg", "per";
> @@ -87,6 +105,7 @@
> uart0: serial@40027000 {
> compatible = "fsl,vf610-lpuart";
> reg = <0x40027000 0x1000>;
> + interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_UART0>;
> clock-names = "ipg";
> dmas = <&edma0 0 2>,
> @@ -98,6 +117,7 @@
> uart1: serial@40028000 {
> compatible = "fsl,vf610-lpuart";
> reg = <0x40028000 0x1000>;
> + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_UART1>;
> clock-names = "ipg";
> dmas = <&edma0 0 4>,
> @@ -109,6 +129,7 @@
> uart2: serial@40029000 {
> compatible = "fsl,vf610-lpuart";
> reg = <0x40029000 0x1000>;
> + interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_UART2>;
> clock-names = "ipg";
> dmas = <&edma0 0 6>,
> @@ -120,6 +141,7 @@
> uart3: serial@4002a000 {
> compatible = "fsl,vf610-lpuart";
> reg = <0x4002a000 0x1000>;
> + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_UART3>;
> clock-names = "ipg";
> dmas = <&edma0 0 8>,
> @@ -133,6 +155,7 @@
> #size-cells = <0>;
> compatible = "fsl,vf610-dspi";
> reg = <0x4002c000 0x1000>;
> + interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_DSPI0>;
> clock-names = "dspi";
> spi-num-chipselects = <5>;
> @@ -142,6 +165,7 @@
> sai2: sai@40031000 {
> compatible = "fsl,vf610-sai";
> reg = <0x40031000 0x1000>;
> + interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_SAI2>;
> clock-names = "sai";
> dma-names = "tx", "rx";
> @@ -153,6 +177,7 @@
> pit: pit@40037000 {
> compatible = "fsl,vf610-pit";
> reg = <0x40037000 0x1000>;
> + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_PIT>;
> clock-names = "pit";
> };
> @@ -186,6 +211,7 @@
> adc0: adc@4003b000 {
> compatible = "fsl,vf610-adc";
> reg = <0x4003b000 0x1000>;
> + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_ADC0>;
> clock-names = "adc";
> status = "disabled";
> @@ -194,6 +220,7 @@
> wdoga5: wdog@4003e000 {
> compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
> reg = <0x4003e000 0x1000>;
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_WDT>;
> clock-names = "wdog";
> status = "disabled";
> @@ -204,6 +231,7 @@
> #size-cells = <0>;
> compatible = "fsl,vf610-qspi";
> reg = <0x40044000 0x1000>;
> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_QSPI0_EN>,
> <&clks VF610_CLK_QSPI0>;
> clock-names = "qspi_en", "qspi";
> @@ -221,6 +249,7 @@
> reg = <0x40049000 0x1000 0x400ff000 0x40>;
> gpio-controller;
> #gpio-cells = <2>;
> + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-controller;
> #interrupt-cells = <2>;
> gpio-ranges = <&iomuxc 0 0 32>;
> @@ -231,6 +260,7 @@
> reg = <0x4004a000 0x1000 0x400ff040 0x40>;
> gpio-controller;
> #gpio-cells = <2>;
> + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-controller;
> #interrupt-cells = <2>;
> gpio-ranges = <&iomuxc 0 32 32>;
> @@ -241,6 +271,7 @@
> reg = <0x4004b000 0x1000 0x400ff080 0x40>;
> gpio-controller;
> #gpio-cells = <2>;
> + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-controller;
> #interrupt-cells = <2>;
> gpio-ranges = <&iomuxc 0 64 32>;
> @@ -251,6 +282,7 @@
> reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
> gpio-controller;
> #gpio-cells = <2>;
> + interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-controller;
> #interrupt-cells = <2>;
> gpio-ranges = <&iomuxc 0 96 32>;
> @@ -261,6 +293,7 @@
> reg = <0x4004d000 0x1000 0x400ff100 0x40>;
> gpio-controller;
> #gpio-cells = <2>;
> + interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-controller;
> #interrupt-cells = <2>;
> gpio-ranges = <&iomuxc 0 128 7>;
> @@ -274,6 +307,7 @@
> usbphy0: usbphy@40050800 {
> compatible = "fsl,vf610-usbphy";
> reg = <0x40050800 0x400>;
> + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_USBPHY0>;
> fsl,anatop = <&anatop>;
> status = "disabled";
> @@ -282,6 +316,7 @@
> usbphy1: usbphy@40050c00 {
> compatible = "fsl,vf610-usbphy";
> reg = <0x40050c00 0x400>;
> + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_USBPHY1>;
> fsl,anatop = <&anatop>;
> status = "disabled";
> @@ -292,6 +327,7 @@
> #size-cells = <0>;
> compatible = "fsl,vf610-i2c";
> reg = <0x40066000 0x1000>;
> + interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_I2C0>;
> clock-names = "ipg";
> dmas = <&edma0 0 50>,
> @@ -311,6 +347,7 @@
> usbdev0: usb@40034000 {
> compatible = "fsl,vf610-usb", "fsl,imx27-usb";
> reg = <0x40034000 0x800>;
> + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_USBC0>;
> fsl,usbphy = <&usbphy0>;
> fsl,usbmisc = <&usbmisc0 0>;
> @@ -345,6 +382,9 @@
> <0x400a1000 0x1000>,
> <0x400a2000 0x1000>;
> dma-channels = <32>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
> + <11 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "edma-tx", "edma-err";
> clock-names = "dmamux0", "dmamux1";
> clocks = <&clks VF610_CLK_DMAMUX2>,
> <&clks VF610_CLK_DMAMUX3>;
> @@ -368,6 +408,7 @@
> uart4: serial@400a9000 {
> compatible = "fsl,vf610-lpuart";
> reg = <0x400a9000 0x1000>;
> + interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_UART4>;
> clock-names = "ipg";
> status = "disabled";
> @@ -376,6 +417,7 @@
> uart5: serial@400aa000 {
> compatible = "fsl,vf610-lpuart";
> reg = <0x400aa000 0x1000>;
> + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_UART5>;
> clock-names = "ipg";
> status = "disabled";
> @@ -384,6 +426,7 @@
> adc1: adc@400bb000 {
> compatible = "fsl,vf610-adc";
> reg = <0x400bb000 0x1000>;
> + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_ADC1>;
> clock-names = "adc";
> status = "disabled";
> @@ -392,6 +435,7 @@
> esdhc1: esdhc@400b2000 {
> compatible = "fsl,imx53-esdhc";
> reg = <0x400b2000 0x1000>;
> + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_IPG_BUS>,
> <&clks VF610_CLK_PLATFORM_BUS>,
> <&clks VF610_CLK_ESDHC1>;
> @@ -402,6 +446,7 @@
> usbh1: usb@400b4000 {
> compatible = "fsl,vf610-usb", "fsl,imx27-usb";
> reg = <0x400b4000 0x800>;
> + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_USBC1>;
> fsl,usbphy = <&usbphy1>;
> fsl,usbmisc = <&usbmisc1 0>;
> @@ -420,6 +465,7 @@
> ftm: ftm@400b8000 {
> compatible = "fsl,ftm-timer";
> reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
> + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> clock-names = "ftm-evt", "ftm-src",
> "ftm-evt-counter-en", "ftm-src-counter-en";
> clocks = <&clks VF610_CLK_FTM2>,
> @@ -432,6 +478,7 @@
> fec0: ethernet@400d0000 {
> compatible = "fsl,mvf600-fec";
> reg = <0x400d0000 0x1000>;
> + interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_ENET0>,
> <&clks VF610_CLK_ENET0>,
> <&clks VF610_CLK_ENET>;
> @@ -442,6 +489,7 @@
> fec1: ethernet@400d1000 {
> compatible = "fsl,mvf600-fec";
> reg = <0x400d1000 0x1000>;
> + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_ENET1>,
> <&clks VF610_CLK_ENET1>,
> <&clks VF610_CLK_ENET>;
> @@ -452,6 +500,7 @@
> can1: flexcan@400d4000 {
> compatible = "fsl,vf610-flexcan";
> reg = <0x400d4000 0x4000>;
> + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_FLEXCAN1>,
> <&clks VF610_CLK_FLEXCAN1>;
> clock-names = "ipg", "per";
> --
> 2.3.0
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
@ 2015-03-11 0:48 ` Shawn Guo
0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2015-03-11 0:48 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
> Add the Miscellaneous System Control Module (MSCM) to the base
> device tree for Vybrid SoC's. This module contains registers
> to get information of the individual and current (accessing)
> CPU. In a second block, there is an interrupt router, which
> handles the routing of the interrupts between the two CPU cores
> on VF6xx variants of the SoC. However, also on single core
> variants the interrupt router needs to be configured in order
> to receive interrupts on the CPU's interrupt controller. Almost
> all peripheral interrupts are routed through the router, hence
> the MSCM module is the default interrupt parent for this SoC.
>
> In a earlier commit the interrupt nodes were moved out of the
> peripheral nodes and specified in the CPU specific vf500.dtsi
> device tree. This allowed to use the base device tree vfxxx.dtsi
> also for a Cortex-M4 specific device tree, which uses different
> interrupt nodes due to the NVIC interrupt controller. However,
> since the interrupt parent for peripherals is the MSCM module
> independently which CPU the device tree is used for, we can move
> the interrupt nodes into the base device tree vfxxx.dtsi again.
> Depending on which CPU this base device tree will be used with,
> the correct parent interrupt controller has to be assigned to
> the MSCM-IR node (GIC or NVIC). The driver takes care of the
> parent interrupt controller specific needs (interrupt-cells).
>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
Stefan,
I guess this patch has a run-time dependency on the first two in the
series, right? Or put it another way, if I apply this single patch on
my branch, the dtb and kernel built from the same branch do not work
together, right? If so, we will need to either wait for the first two
hit mainline or pull Jason's irqchip/vybrid branch into my tree as
prerequisite (irqchip/vybrid needs to be stable).
Shawn
> ---
> arch/arm/boot/dts/vf500.dtsi | 137 ++-----------------------------------------
> arch/arm/boot/dts/vfxxx.dtsi | 49 ++++++++++++++++
> 2 files changed, 53 insertions(+), 133 deletions(-)
>
> diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
> index 1dbf8d2..e976d2f 100644
> --- a/arch/arm/boot/dts/vf500.dtsi
> +++ b/arch/arm/boot/dts/vf500.dtsi
> @@ -24,14 +24,13 @@
> };
>
> soc {
> - interrupt-parent = <&intc>;
> -
> aips-bus at 40000000 {
>
> intc: interrupt-controller at 40002000 {
> compatible = "arm,cortex-a9-gic";
> #interrupt-cells = <3>;
> interrupt-controller;
> + interrupt-parent = <&intc>;
> reg = <0x40003000 0x1000>,
> <0x40002100 0x100>;
> };
> @@ -40,145 +39,17 @@
> compatible = "arm,cortex-a9-global-timer";
> reg = <0x40002200 0x20>;
> interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&intc>;
> clocks = <&clks VF610_CLK_PLATFORM_BUS>;
> };
> };
> };
> };
>
> -&adc0 {
> - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&adc1 {
> - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&can0 {
> - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&can1 {
> - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&dspi0 {
> - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&edma0 {
> - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "edma-tx", "edma-err";
> -};
> -
> -&edma1 {
> - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "edma-tx", "edma-err";
> -};
> -
> -&esdhc1 {
> - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&fec0 {
> - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&fec1 {
> - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&ftm {
> - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&gpio0 {
> - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&gpio1 {
> - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&gpio2 {
> - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&gpio3 {
> - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&gpio4 {
> - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&i2c0 {
> - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&pit {
> - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&qspi0 {
> - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&sai2 {
> - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&snvsrtc {
> - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&src {
> - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&uart0 {
> - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&uart1 {
> - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&uart2 {
> - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&uart3 {
> - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&uart4 {
> - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&uart5 {
> - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&usbdev0 {
> - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&usbh1 {
> - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&usbphy0 {
> - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> -};
> -
> -&usbphy1 {
> - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +&mscm_ir {
> + interrupt-parent = <&intc>;
> };
>
> &wdoga5 {
> - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> status = "okay";
> };
> diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
> index a29c7ce..32de809 100644
> --- a/arch/arm/boot/dts/vfxxx.dtsi
> +++ b/arch/arm/boot/dts/vfxxx.dtsi
> @@ -54,6 +54,7 @@
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "simple-bus";
> + interrupt-parent = <&mscm_ir>;
> ranges;
>
> aips0: aips-bus at 40000000 {
> @@ -62,6 +63,19 @@
> #size-cells = <1>;
> ranges;
>
> + mscm_cpucfg: cpucfg at 40001000 {
> + compatible = "fsl,vf610-mscm-cpucfg", "syscon";
> + reg = <0x40001000 0x800>;
> + };
> +
> + mscm_ir: interrupt-controller at 40001800 {
> + compatible = "fsl,vf610-mscm-ir";
> + reg = <0x40001800 0x400>;
> + fsl,cpucfg = <&mscm_cpucfg>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> edma0: dma-controller at 40018000 {
> #dma-cells = <2>;
> compatible = "fsl,vf610-edma";
> @@ -69,6 +83,9 @@
> <0x40024000 0x1000>,
> <0x40025000 0x1000>;
> dma-channels = <32>;
> + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
> + <9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "edma-tx", "edma-err";
> clock-names = "dmamux0", "dmamux1";
> clocks = <&clks VF610_CLK_DMAMUX0>,
> <&clks VF610_CLK_DMAMUX1>;
> @@ -78,6 +95,7 @@
> can0: flexcan at 40020000 {
> compatible = "fsl,vf610-flexcan";
> reg = <0x40020000 0x4000>;
> + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_FLEXCAN0>,
> <&clks VF610_CLK_FLEXCAN0>;
> clock-names = "ipg", "per";
> @@ -87,6 +105,7 @@
> uart0: serial at 40027000 {
> compatible = "fsl,vf610-lpuart";
> reg = <0x40027000 0x1000>;
> + interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_UART0>;
> clock-names = "ipg";
> dmas = <&edma0 0 2>,
> @@ -98,6 +117,7 @@
> uart1: serial at 40028000 {
> compatible = "fsl,vf610-lpuart";
> reg = <0x40028000 0x1000>;
> + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_UART1>;
> clock-names = "ipg";
> dmas = <&edma0 0 4>,
> @@ -109,6 +129,7 @@
> uart2: serial at 40029000 {
> compatible = "fsl,vf610-lpuart";
> reg = <0x40029000 0x1000>;
> + interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_UART2>;
> clock-names = "ipg";
> dmas = <&edma0 0 6>,
> @@ -120,6 +141,7 @@
> uart3: serial at 4002a000 {
> compatible = "fsl,vf610-lpuart";
> reg = <0x4002a000 0x1000>;
> + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_UART3>;
> clock-names = "ipg";
> dmas = <&edma0 0 8>,
> @@ -133,6 +155,7 @@
> #size-cells = <0>;
> compatible = "fsl,vf610-dspi";
> reg = <0x4002c000 0x1000>;
> + interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_DSPI0>;
> clock-names = "dspi";
> spi-num-chipselects = <5>;
> @@ -142,6 +165,7 @@
> sai2: sai at 40031000 {
> compatible = "fsl,vf610-sai";
> reg = <0x40031000 0x1000>;
> + interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_SAI2>;
> clock-names = "sai";
> dma-names = "tx", "rx";
> @@ -153,6 +177,7 @@
> pit: pit at 40037000 {
> compatible = "fsl,vf610-pit";
> reg = <0x40037000 0x1000>;
> + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_PIT>;
> clock-names = "pit";
> };
> @@ -186,6 +211,7 @@
> adc0: adc at 4003b000 {
> compatible = "fsl,vf610-adc";
> reg = <0x4003b000 0x1000>;
> + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_ADC0>;
> clock-names = "adc";
> status = "disabled";
> @@ -194,6 +220,7 @@
> wdoga5: wdog at 4003e000 {
> compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
> reg = <0x4003e000 0x1000>;
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_WDT>;
> clock-names = "wdog";
> status = "disabled";
> @@ -204,6 +231,7 @@
> #size-cells = <0>;
> compatible = "fsl,vf610-qspi";
> reg = <0x40044000 0x1000>;
> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_QSPI0_EN>,
> <&clks VF610_CLK_QSPI0>;
> clock-names = "qspi_en", "qspi";
> @@ -221,6 +249,7 @@
> reg = <0x40049000 0x1000 0x400ff000 0x40>;
> gpio-controller;
> #gpio-cells = <2>;
> + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-controller;
> #interrupt-cells = <2>;
> gpio-ranges = <&iomuxc 0 0 32>;
> @@ -231,6 +260,7 @@
> reg = <0x4004a000 0x1000 0x400ff040 0x40>;
> gpio-controller;
> #gpio-cells = <2>;
> + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-controller;
> #interrupt-cells = <2>;
> gpio-ranges = <&iomuxc 0 32 32>;
> @@ -241,6 +271,7 @@
> reg = <0x4004b000 0x1000 0x400ff080 0x40>;
> gpio-controller;
> #gpio-cells = <2>;
> + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-controller;
> #interrupt-cells = <2>;
> gpio-ranges = <&iomuxc 0 64 32>;
> @@ -251,6 +282,7 @@
> reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
> gpio-controller;
> #gpio-cells = <2>;
> + interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-controller;
> #interrupt-cells = <2>;
> gpio-ranges = <&iomuxc 0 96 32>;
> @@ -261,6 +293,7 @@
> reg = <0x4004d000 0x1000 0x400ff100 0x40>;
> gpio-controller;
> #gpio-cells = <2>;
> + interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-controller;
> #interrupt-cells = <2>;
> gpio-ranges = <&iomuxc 0 128 7>;
> @@ -274,6 +307,7 @@
> usbphy0: usbphy at 40050800 {
> compatible = "fsl,vf610-usbphy";
> reg = <0x40050800 0x400>;
> + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_USBPHY0>;
> fsl,anatop = <&anatop>;
> status = "disabled";
> @@ -282,6 +316,7 @@
> usbphy1: usbphy at 40050c00 {
> compatible = "fsl,vf610-usbphy";
> reg = <0x40050c00 0x400>;
> + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_USBPHY1>;
> fsl,anatop = <&anatop>;
> status = "disabled";
> @@ -292,6 +327,7 @@
> #size-cells = <0>;
> compatible = "fsl,vf610-i2c";
> reg = <0x40066000 0x1000>;
> + interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_I2C0>;
> clock-names = "ipg";
> dmas = <&edma0 0 50>,
> @@ -311,6 +347,7 @@
> usbdev0: usb at 40034000 {
> compatible = "fsl,vf610-usb", "fsl,imx27-usb";
> reg = <0x40034000 0x800>;
> + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_USBC0>;
> fsl,usbphy = <&usbphy0>;
> fsl,usbmisc = <&usbmisc0 0>;
> @@ -345,6 +382,9 @@
> <0x400a1000 0x1000>,
> <0x400a2000 0x1000>;
> dma-channels = <32>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
> + <11 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "edma-tx", "edma-err";
> clock-names = "dmamux0", "dmamux1";
> clocks = <&clks VF610_CLK_DMAMUX2>,
> <&clks VF610_CLK_DMAMUX3>;
> @@ -368,6 +408,7 @@
> uart4: serial at 400a9000 {
> compatible = "fsl,vf610-lpuart";
> reg = <0x400a9000 0x1000>;
> + interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_UART4>;
> clock-names = "ipg";
> status = "disabled";
> @@ -376,6 +417,7 @@
> uart5: serial at 400aa000 {
> compatible = "fsl,vf610-lpuart";
> reg = <0x400aa000 0x1000>;
> + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_UART5>;
> clock-names = "ipg";
> status = "disabled";
> @@ -384,6 +426,7 @@
> adc1: adc at 400bb000 {
> compatible = "fsl,vf610-adc";
> reg = <0x400bb000 0x1000>;
> + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_ADC1>;
> clock-names = "adc";
> status = "disabled";
> @@ -392,6 +435,7 @@
> esdhc1: esdhc at 400b2000 {
> compatible = "fsl,imx53-esdhc";
> reg = <0x400b2000 0x1000>;
> + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_IPG_BUS>,
> <&clks VF610_CLK_PLATFORM_BUS>,
> <&clks VF610_CLK_ESDHC1>;
> @@ -402,6 +446,7 @@
> usbh1: usb at 400b4000 {
> compatible = "fsl,vf610-usb", "fsl,imx27-usb";
> reg = <0x400b4000 0x800>;
> + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_USBC1>;
> fsl,usbphy = <&usbphy1>;
> fsl,usbmisc = <&usbmisc1 0>;
> @@ -420,6 +465,7 @@
> ftm: ftm at 400b8000 {
> compatible = "fsl,ftm-timer";
> reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
> + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> clock-names = "ftm-evt", "ftm-src",
> "ftm-evt-counter-en", "ftm-src-counter-en";
> clocks = <&clks VF610_CLK_FTM2>,
> @@ -432,6 +478,7 @@
> fec0: ethernet at 400d0000 {
> compatible = "fsl,mvf600-fec";
> reg = <0x400d0000 0x1000>;
> + interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_ENET0>,
> <&clks VF610_CLK_ENET0>,
> <&clks VF610_CLK_ENET>;
> @@ -442,6 +489,7 @@
> fec1: ethernet at 400d1000 {
> compatible = "fsl,mvf600-fec";
> reg = <0x400d1000 0x1000>;
> + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_ENET1>,
> <&clks VF610_CLK_ENET1>,
> <&clks VF610_CLK_ENET>;
> @@ -452,6 +500,7 @@
> can1: flexcan at 400d4000 {
> compatible = "fsl,vf610-flexcan";
> reg = <0x400d4000 0x4000>;
> + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks VF610_CLK_FLEXCAN1>,
> <&clks VF610_CLK_FLEXCAN1>;
> clock-names = "ipg", "per";
> --
> 2.3.0
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
2015-03-11 0:48 ` Shawn Guo
(?)
@ 2015-03-11 4:05 ` Jason Cooper
-1 siblings, 0 replies; 30+ messages in thread
From: Jason Cooper @ 2015-03-11 4:05 UTC (permalink / raw)
To: Shawn Guo
Cc: Stefan Agner, tglx, mark.rutland, marc.zyngier, u.kleine-koenig,
kernel, arnd, robh+dt, pawel.moll, ijc+devicetree, galak,
pebolle, linux, devicetree, linux-arm-kernel, linux-kernel
On Wed, Mar 11, 2015 at 08:48:15AM +0800, Shawn Guo wrote:
> On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
> > Add the Miscellaneous System Control Module (MSCM) to the base
> > device tree for Vybrid SoC's. This module contains registers
> > to get information of the individual and current (accessing)
> > CPU. In a second block, there is an interrupt router, which
> > handles the routing of the interrupts between the two CPU cores
> > on VF6xx variants of the SoC. However, also on single core
> > variants the interrupt router needs to be configured in order
> > to receive interrupts on the CPU's interrupt controller. Almost
> > all peripheral interrupts are routed through the router, hence
> > the MSCM module is the default interrupt parent for this SoC.
> >
> > In a earlier commit the interrupt nodes were moved out of the
> > peripheral nodes and specified in the CPU specific vf500.dtsi
> > device tree. This allowed to use the base device tree vfxxx.dtsi
> > also for a Cortex-M4 specific device tree, which uses different
> > interrupt nodes due to the NVIC interrupt controller. However,
> > since the interrupt parent for peripherals is the MSCM module
> > independently which CPU the device tree is used for, we can move
> > the interrupt nodes into the base device tree vfxxx.dtsi again.
> > Depending on which CPU this base device tree will be used with,
> > the correct parent interrupt controller has to be assigned to
> > the MSCM-IR node (GIC or NVIC). The driver takes care of the
> > parent interrupt controller specific needs (interrupt-cells).
> >
> > Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> > Signed-off-by: Stefan Agner <stefan@agner.ch>
>
> Stefan,
>
> I guess this patch has a run-time dependency on the first two in the
> series, right? Or put it another way, if I apply this single patch on
> my branch, the dtb and kernel built from the same branch do not work
> together, right? If so, we will need to either wait for the first two
> hit mainline or pull Jason's irqchip/vybrid branch into my tree as
> prerequisite (irqchip/vybrid needs to be stable).
No problem, I'll only add patches on top of this if needed. no rebasing.
thx,
Jason.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
@ 2015-03-11 4:05 ` Jason Cooper
0 siblings, 0 replies; 30+ messages in thread
From: Jason Cooper @ 2015-03-11 4:05 UTC (permalink / raw)
To: Shawn Guo
Cc: mark.rutland, devicetree, pebolle, linux, pawel.moll, arnd,
ijc+devicetree, marc.zyngier, galak, linux-kernel, Stefan Agner,
robh+dt, kernel, u.kleine-koenig, tglx, linux-arm-kernel
On Wed, Mar 11, 2015 at 08:48:15AM +0800, Shawn Guo wrote:
> On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
> > Add the Miscellaneous System Control Module (MSCM) to the base
> > device tree for Vybrid SoC's. This module contains registers
> > to get information of the individual and current (accessing)
> > CPU. In a second block, there is an interrupt router, which
> > handles the routing of the interrupts between the two CPU cores
> > on VF6xx variants of the SoC. However, also on single core
> > variants the interrupt router needs to be configured in order
> > to receive interrupts on the CPU's interrupt controller. Almost
> > all peripheral interrupts are routed through the router, hence
> > the MSCM module is the default interrupt parent for this SoC.
> >
> > In a earlier commit the interrupt nodes were moved out of the
> > peripheral nodes and specified in the CPU specific vf500.dtsi
> > device tree. This allowed to use the base device tree vfxxx.dtsi
> > also for a Cortex-M4 specific device tree, which uses different
> > interrupt nodes due to the NVIC interrupt controller. However,
> > since the interrupt parent for peripherals is the MSCM module
> > independently which CPU the device tree is used for, we can move
> > the interrupt nodes into the base device tree vfxxx.dtsi again.
> > Depending on which CPU this base device tree will be used with,
> > the correct parent interrupt controller has to be assigned to
> > the MSCM-IR node (GIC or NVIC). The driver takes care of the
> > parent interrupt controller specific needs (interrupt-cells).
> >
> > Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> > Signed-off-by: Stefan Agner <stefan@agner.ch>
>
> Stefan,
>
> I guess this patch has a run-time dependency on the first two in the
> series, right? Or put it another way, if I apply this single patch on
> my branch, the dtb and kernel built from the same branch do not work
> together, right? If so, we will need to either wait for the first two
> hit mainline or pull Jason's irqchip/vybrid branch into my tree as
> prerequisite (irqchip/vybrid needs to be stable).
No problem, I'll only add patches on top of this if needed. no rebasing.
thx,
Jason.
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
@ 2015-03-11 4:05 ` Jason Cooper
0 siblings, 0 replies; 30+ messages in thread
From: Jason Cooper @ 2015-03-11 4:05 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Mar 11, 2015 at 08:48:15AM +0800, Shawn Guo wrote:
> On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
> > Add the Miscellaneous System Control Module (MSCM) to the base
> > device tree for Vybrid SoC's. This module contains registers
> > to get information of the individual and current (accessing)
> > CPU. In a second block, there is an interrupt router, which
> > handles the routing of the interrupts between the two CPU cores
> > on VF6xx variants of the SoC. However, also on single core
> > variants the interrupt router needs to be configured in order
> > to receive interrupts on the CPU's interrupt controller. Almost
> > all peripheral interrupts are routed through the router, hence
> > the MSCM module is the default interrupt parent for this SoC.
> >
> > In a earlier commit the interrupt nodes were moved out of the
> > peripheral nodes and specified in the CPU specific vf500.dtsi
> > device tree. This allowed to use the base device tree vfxxx.dtsi
> > also for a Cortex-M4 specific device tree, which uses different
> > interrupt nodes due to the NVIC interrupt controller. However,
> > since the interrupt parent for peripherals is the MSCM module
> > independently which CPU the device tree is used for, we can move
> > the interrupt nodes into the base device tree vfxxx.dtsi again.
> > Depending on which CPU this base device tree will be used with,
> > the correct parent interrupt controller has to be assigned to
> > the MSCM-IR node (GIC or NVIC). The driver takes care of the
> > parent interrupt controller specific needs (interrupt-cells).
> >
> > Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> > Signed-off-by: Stefan Agner <stefan@agner.ch>
>
> Stefan,
>
> I guess this patch has a run-time dependency on the first two in the
> series, right? Or put it another way, if I apply this single patch on
> my branch, the dtb and kernel built from the same branch do not work
> together, right? If so, we will need to either wait for the first two
> hit mainline or pull Jason's irqchip/vybrid branch into my tree as
> prerequisite (irqchip/vybrid needs to be stable).
No problem, I'll only add patches on top of this if needed. no rebasing.
thx,
Jason.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
2015-03-11 0:48 ` Shawn Guo
@ 2015-03-12 9:03 ` Stefan Agner
-1 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-12 9:03 UTC (permalink / raw)
To: Shawn Guo
Cc: tglx, jason, mark.rutland, marc.zyngier, u.kleine-koenig, kernel,
arnd, robh+dt, pawel.moll, ijc+devicetree, galak, pebolle, linux,
devicetree, linux-arm-kernel, linux-kernel
On 2015-03-11 01:48, Shawn Guo wrote:
> On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
>> Add the Miscellaneous System Control Module (MSCM) to the base
>> device tree for Vybrid SoC's. This module contains registers
>> to get information of the individual and current (accessing)
>> CPU. In a second block, there is an interrupt router, which
>> handles the routing of the interrupts between the two CPU cores
>> on VF6xx variants of the SoC. However, also on single core
>> variants the interrupt router needs to be configured in order
>> to receive interrupts on the CPU's interrupt controller. Almost
>> all peripheral interrupts are routed through the router, hence
>> the MSCM module is the default interrupt parent for this SoC.
>>
>> In a earlier commit the interrupt nodes were moved out of the
>> peripheral nodes and specified in the CPU specific vf500.dtsi
>> device tree. This allowed to use the base device tree vfxxx.dtsi
>> also for a Cortex-M4 specific device tree, which uses different
>> interrupt nodes due to the NVIC interrupt controller. However,
>> since the interrupt parent for peripherals is the MSCM module
>> independently which CPU the device tree is used for, we can move
>> the interrupt nodes into the base device tree vfxxx.dtsi again.
>> Depending on which CPU this base device tree will be used with,
>> the correct parent interrupt controller has to be assigned to
>> the MSCM-IR node (GIC or NVIC). The driver takes care of the
>> parent interrupt controller specific needs (interrupt-cells).
>>
>> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>
> Stefan,
>
> I guess this patch has a run-time dependency on the first two in the
> series, right? Or put it another way, if I apply this single patch on
> my branch, the dtb and kernel built from the same branch do not work
> together, right? If so, we will need to either wait for the first two
> hit mainline or pull Jason's irqchip/vybrid branch into my tree as
> prerequisite (irqchip/vybrid needs to be stable).
>
> Shawn
Yes, that is true. The driver need to be in place in order to
successfully boot with the new device tree.
--
Stefan
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
@ 2015-03-12 9:03 ` Stefan Agner
0 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-12 9:03 UTC (permalink / raw)
To: linux-arm-kernel
On 2015-03-11 01:48, Shawn Guo wrote:
> On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
>> Add the Miscellaneous System Control Module (MSCM) to the base
>> device tree for Vybrid SoC's. This module contains registers
>> to get information of the individual and current (accessing)
>> CPU. In a second block, there is an interrupt router, which
>> handles the routing of the interrupts between the two CPU cores
>> on VF6xx variants of the SoC. However, also on single core
>> variants the interrupt router needs to be configured in order
>> to receive interrupts on the CPU's interrupt controller. Almost
>> all peripheral interrupts are routed through the router, hence
>> the MSCM module is the default interrupt parent for this SoC.
>>
>> In a earlier commit the interrupt nodes were moved out of the
>> peripheral nodes and specified in the CPU specific vf500.dtsi
>> device tree. This allowed to use the base device tree vfxxx.dtsi
>> also for a Cortex-M4 specific device tree, which uses different
>> interrupt nodes due to the NVIC interrupt controller. However,
>> since the interrupt parent for peripherals is the MSCM module
>> independently which CPU the device tree is used for, we can move
>> the interrupt nodes into the base device tree vfxxx.dtsi again.
>> Depending on which CPU this base device tree will be used with,
>> the correct parent interrupt controller has to be assigned to
>> the MSCM-IR node (GIC or NVIC). The driver takes care of the
>> parent interrupt controller specific needs (interrupt-cells).
>>
>> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>
> Stefan,
>
> I guess this patch has a run-time dependency on the first two in the
> series, right? Or put it another way, if I apply this single patch on
> my branch, the dtb and kernel built from the same branch do not work
> together, right? If so, we will need to either wait for the first two
> hit mainline or pull Jason's irqchip/vybrid branch into my tree as
> prerequisite (irqchip/vybrid needs to be stable).
>
> Shawn
Yes, that is true. The driver need to be in place in order to
successfully boot with the new device tree.
--
Stefan
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
@ 2015-03-13 4:48 ` Shawn Guo
0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2015-03-13 4:48 UTC (permalink / raw)
To: Stefan Agner
Cc: tglx, jason, mark.rutland, marc.zyngier, u.kleine-koenig, kernel,
arnd, robh+dt, pawel.moll, ijc+devicetree, galak, pebolle, linux,
devicetree, linux-arm-kernel, linux-kernel
On Thu, Mar 12, 2015 at 10:03:08AM +0100, Stefan Agner wrote:
> On 2015-03-11 01:48, Shawn Guo wrote:
> > On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
> >> Add the Miscellaneous System Control Module (MSCM) to the base
> >> device tree for Vybrid SoC's. This module contains registers
> >> to get information of the individual and current (accessing)
> >> CPU. In a second block, there is an interrupt router, which
> >> handles the routing of the interrupts between the two CPU cores
> >> on VF6xx variants of the SoC. However, also on single core
> >> variants the interrupt router needs to be configured in order
> >> to receive interrupts on the CPU's interrupt controller. Almost
> >> all peripheral interrupts are routed through the router, hence
> >> the MSCM module is the default interrupt parent for this SoC.
> >>
> >> In a earlier commit the interrupt nodes were moved out of the
> >> peripheral nodes and specified in the CPU specific vf500.dtsi
> >> device tree. This allowed to use the base device tree vfxxx.dtsi
> >> also for a Cortex-M4 specific device tree, which uses different
> >> interrupt nodes due to the NVIC interrupt controller. However,
> >> since the interrupt parent for peripherals is the MSCM module
> >> independently which CPU the device tree is used for, we can move
> >> the interrupt nodes into the base device tree vfxxx.dtsi again.
> >> Depending on which CPU this base device tree will be used with,
> >> the correct parent interrupt controller has to be assigned to
> >> the MSCM-IR node (GIC or NVIC). The driver takes care of the
> >> parent interrupt controller specific needs (interrupt-cells).
> >>
> >> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> >> Signed-off-by: Stefan Agner <stefan@agner.ch>
> >
> > Stefan,
> >
> > I guess this patch has a run-time dependency on the first two in the
> > series, right? Or put it another way, if I apply this single patch on
> > my branch, the dtb and kernel built from the same branch do not work
> > together, right? If so, we will need to either wait for the first two
> > hit mainline or pull Jason's irqchip/vybrid branch into my tree as
> > prerequisite (irqchip/vybrid needs to be stable).
> >
> > Shawn
>
> Yes, that is true. The driver need to be in place in order to
> successfully boot with the new device tree.
Okay. Pulled Jason's irqchip/vybrid branch in, and applied the patch.
Stefan,
There was a conflict on device dspi1 when applying the patch to my
imx/dt branch. Please take a look to see if I solved it correctly.
Shawn
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
@ 2015-03-13 4:48 ` Shawn Guo
0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2015-03-13 4:48 UTC (permalink / raw)
To: Stefan Agner
Cc: tglx-hfZtesqFncYOwBW4kG4KsQ, jason-NLaQJdtUoK4Be96aLqz0jA,
mark.rutland-5wv7dgnIgG8, marc.zyngier-5wv7dgnIgG8,
u.kleine-koenig-bIcnvbaLZ9MEGnE8C9+IrQ,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, arnd-r2nGTMty4D4,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, pebolle-IWqWACnzNjzz+pZb47iToQ,
linux-lFZ/pmaqli7XmaaqVzeoHQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On Thu, Mar 12, 2015 at 10:03:08AM +0100, Stefan Agner wrote:
> On 2015-03-11 01:48, Shawn Guo wrote:
> > On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
> >> Add the Miscellaneous System Control Module (MSCM) to the base
> >> device tree for Vybrid SoC's. This module contains registers
> >> to get information of the individual and current (accessing)
> >> CPU. In a second block, there is an interrupt router, which
> >> handles the routing of the interrupts between the two CPU cores
> >> on VF6xx variants of the SoC. However, also on single core
> >> variants the interrupt router needs to be configured in order
> >> to receive interrupts on the CPU's interrupt controller. Almost
> >> all peripheral interrupts are routed through the router, hence
> >> the MSCM module is the default interrupt parent for this SoC.
> >>
> >> In a earlier commit the interrupt nodes were moved out of the
> >> peripheral nodes and specified in the CPU specific vf500.dtsi
> >> device tree. This allowed to use the base device tree vfxxx.dtsi
> >> also for a Cortex-M4 specific device tree, which uses different
> >> interrupt nodes due to the NVIC interrupt controller. However,
> >> since the interrupt parent for peripherals is the MSCM module
> >> independently which CPU the device tree is used for, we can move
> >> the interrupt nodes into the base device tree vfxxx.dtsi again.
> >> Depending on which CPU this base device tree will be used with,
> >> the correct parent interrupt controller has to be assigned to
> >> the MSCM-IR node (GIC or NVIC). The driver takes care of the
> >> parent interrupt controller specific needs (interrupt-cells).
> >>
> >> Acked-by: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
> >> Signed-off-by: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org>
> >
> > Stefan,
> >
> > I guess this patch has a run-time dependency on the first two in the
> > series, right? Or put it another way, if I apply this single patch on
> > my branch, the dtb and kernel built from the same branch do not work
> > together, right? If so, we will need to either wait for the first two
> > hit mainline or pull Jason's irqchip/vybrid branch into my tree as
> > prerequisite (irqchip/vybrid needs to be stable).
> >
> > Shawn
>
> Yes, that is true. The driver need to be in place in order to
> successfully boot with the new device tree.
Okay. Pulled Jason's irqchip/vybrid branch in, and applied the patch.
Stefan,
There was a conflict on device dspi1 when applying the patch to my
imx/dt branch. Please take a look to see if I solved it correctly.
Shawn
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
@ 2015-03-13 4:48 ` Shawn Guo
0 siblings, 0 replies; 30+ messages in thread
From: Shawn Guo @ 2015-03-13 4:48 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 12, 2015 at 10:03:08AM +0100, Stefan Agner wrote:
> On 2015-03-11 01:48, Shawn Guo wrote:
> > On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
> >> Add the Miscellaneous System Control Module (MSCM) to the base
> >> device tree for Vybrid SoC's. This module contains registers
> >> to get information of the individual and current (accessing)
> >> CPU. In a second block, there is an interrupt router, which
> >> handles the routing of the interrupts between the two CPU cores
> >> on VF6xx variants of the SoC. However, also on single core
> >> variants the interrupt router needs to be configured in order
> >> to receive interrupts on the CPU's interrupt controller. Almost
> >> all peripheral interrupts are routed through the router, hence
> >> the MSCM module is the default interrupt parent for this SoC.
> >>
> >> In a earlier commit the interrupt nodes were moved out of the
> >> peripheral nodes and specified in the CPU specific vf500.dtsi
> >> device tree. This allowed to use the base device tree vfxxx.dtsi
> >> also for a Cortex-M4 specific device tree, which uses different
> >> interrupt nodes due to the NVIC interrupt controller. However,
> >> since the interrupt parent for peripherals is the MSCM module
> >> independently which CPU the device tree is used for, we can move
> >> the interrupt nodes into the base device tree vfxxx.dtsi again.
> >> Depending on which CPU this base device tree will be used with,
> >> the correct parent interrupt controller has to be assigned to
> >> the MSCM-IR node (GIC or NVIC). The driver takes care of the
> >> parent interrupt controller specific needs (interrupt-cells).
> >>
> >> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> >> Signed-off-by: Stefan Agner <stefan@agner.ch>
> >
> > Stefan,
> >
> > I guess this patch has a run-time dependency on the first two in the
> > series, right? Or put it another way, if I apply this single patch on
> > my branch, the dtb and kernel built from the same branch do not work
> > together, right? If so, we will need to either wait for the first two
> > hit mainline or pull Jason's irqchip/vybrid branch into my tree as
> > prerequisite (irqchip/vybrid needs to be stable).
> >
> > Shawn
>
> Yes, that is true. The driver need to be in place in order to
> successfully boot with the new device tree.
Okay. Pulled Jason's irqchip/vybrid branch in, and applied the patch.
Stefan,
There was a conflict on device dspi1 when applying the patch to my
imx/dt branch. Please take a look to see if I solved it correctly.
Shawn
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
2015-03-13 4:48 ` Shawn Guo
@ 2015-03-13 9:42 ` Stefan Agner
-1 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-13 9:42 UTC (permalink / raw)
To: Shawn Guo
Cc: tglx, jason, mark.rutland, marc.zyngier, u.kleine-koenig, kernel,
arnd, robh+dt, pawel.moll, ijc+devicetree, galak, pebolle, linux,
devicetree, linux-arm-kernel, linux-kernel
On 2015-03-13 05:48, Shawn Guo wrote:
> On Thu, Mar 12, 2015 at 10:03:08AM +0100, Stefan Agner wrote:
>> On 2015-03-11 01:48, Shawn Guo wrote:
>> > On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
>> >> Add the Miscellaneous System Control Module (MSCM) to the base
>> >> device tree for Vybrid SoC's. This module contains registers
>> >> to get information of the individual and current (accessing)
>> >> CPU. In a second block, there is an interrupt router, which
>> >> handles the routing of the interrupts between the two CPU cores
>> >> on VF6xx variants of the SoC. However, also on single core
>> >> variants the interrupt router needs to be configured in order
>> >> to receive interrupts on the CPU's interrupt controller. Almost
>> >> all peripheral interrupts are routed through the router, hence
>> >> the MSCM module is the default interrupt parent for this SoC.
>> >>
>> >> In a earlier commit the interrupt nodes were moved out of the
>> >> peripheral nodes and specified in the CPU specific vf500.dtsi
>> >> device tree. This allowed to use the base device tree vfxxx.dtsi
>> >> also for a Cortex-M4 specific device tree, which uses different
>> >> interrupt nodes due to the NVIC interrupt controller. However,
>> >> since the interrupt parent for peripherals is the MSCM module
>> >> independently which CPU the device tree is used for, we can move
>> >> the interrupt nodes into the base device tree vfxxx.dtsi again.
>> >> Depending on which CPU this base device tree will be used with,
>> >> the correct parent interrupt controller has to be assigned to
>> >> the MSCM-IR node (GIC or NVIC). The driver takes care of the
>> >> parent interrupt controller specific needs (interrupt-cells).
>> >>
>> >> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>> >> Signed-off-by: Stefan Agner <stefan@agner.ch>
>> >
>> > Stefan,
>> >
>> > I guess this patch has a run-time dependency on the first two in the
>> > series, right? Or put it another way, if I apply this single patch on
>> > my branch, the dtb and kernel built from the same branch do not work
>> > together, right? If so, we will need to either wait for the first two
>> > hit mainline or pull Jason's irqchip/vybrid branch into my tree as
>> > prerequisite (irqchip/vybrid needs to be stable).
>> >
>> > Shawn
>>
>> Yes, that is true. The driver need to be in place in order to
>> successfully boot with the new device tree.
>
> Okay. Pulled Jason's irqchip/vybrid branch in, and applied the patch.
>
> Stefan,
>
> There was a conflict on device dspi1 when applying the patch to my
> imx/dt branch. Please take a look to see if I solved it correctly.
>
Hi Shawn,
Your updated patch looks good to me. Also quickly boot tested the
branch, worked fine.
Thx!
--
Stefan
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
@ 2015-03-13 9:42 ` Stefan Agner
0 siblings, 0 replies; 30+ messages in thread
From: Stefan Agner @ 2015-03-13 9:42 UTC (permalink / raw)
To: linux-arm-kernel
On 2015-03-13 05:48, Shawn Guo wrote:
> On Thu, Mar 12, 2015 at 10:03:08AM +0100, Stefan Agner wrote:
>> On 2015-03-11 01:48, Shawn Guo wrote:
>> > On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
>> >> Add the Miscellaneous System Control Module (MSCM) to the base
>> >> device tree for Vybrid SoC's. This module contains registers
>> >> to get information of the individual and current (accessing)
>> >> CPU. In a second block, there is an interrupt router, which
>> >> handles the routing of the interrupts between the two CPU cores
>> >> on VF6xx variants of the SoC. However, also on single core
>> >> variants the interrupt router needs to be configured in order
>> >> to receive interrupts on the CPU's interrupt controller. Almost
>> >> all peripheral interrupts are routed through the router, hence
>> >> the MSCM module is the default interrupt parent for this SoC.
>> >>
>> >> In a earlier commit the interrupt nodes were moved out of the
>> >> peripheral nodes and specified in the CPU specific vf500.dtsi
>> >> device tree. This allowed to use the base device tree vfxxx.dtsi
>> >> also for a Cortex-M4 specific device tree, which uses different
>> >> interrupt nodes due to the NVIC interrupt controller. However,
>> >> since the interrupt parent for peripherals is the MSCM module
>> >> independently which CPU the device tree is used for, we can move
>> >> the interrupt nodes into the base device tree vfxxx.dtsi again.
>> >> Depending on which CPU this base device tree will be used with,
>> >> the correct parent interrupt controller has to be assigned to
>> >> the MSCM-IR node (GIC or NVIC). The driver takes care of the
>> >> parent interrupt controller specific needs (interrupt-cells).
>> >>
>> >> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>> >> Signed-off-by: Stefan Agner <stefan@agner.ch>
>> >
>> > Stefan,
>> >
>> > I guess this patch has a run-time dependency on the first two in the
>> > series, right? Or put it another way, if I apply this single patch on
>> > my branch, the dtb and kernel built from the same branch do not work
>> > together, right? If so, we will need to either wait for the first two
>> > hit mainline or pull Jason's irqchip/vybrid branch into my tree as
>> > prerequisite (irqchip/vybrid needs to be stable).
>> >
>> > Shawn
>>
>> Yes, that is true. The driver need to be in place in order to
>> successfully boot with the new device tree.
>
> Okay. Pulled Jason's irqchip/vybrid branch in, and applied the patch.
>
> Stefan,
>
> There was a conflict on device dspi1 when applying the patch to my
> imx/dt branch. Please take a look to see if I solved it correctly.
>
Hi Shawn,
Your updated patch looks good to me. Also quickly boot tested the
branch, worked fine.
Thx!
--
Stefan
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2015-03-13 9:42 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-03-01 22:41 [PATCH v6 0/3] irqchip: vf610-mscm: add MSCM interrupt router driver Stefan Agner
2015-03-01 22:41 ` Stefan Agner
2015-03-01 22:41 ` [PATCH v6 1/3] irqchip: vf610-mscm-ir: add support for MSCM interrupt router Stefan Agner
2015-03-01 22:41 ` Stefan Agner
2015-03-01 22:41 ` Stefan Agner
2015-03-01 22:41 ` [PATCH v6 2/3] irqchip: vf610-mscm: dt-bindings: add MSCM bindings Stefan Agner
2015-03-01 22:41 ` Stefan Agner
2015-03-01 22:41 ` [PATCH v6 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Stefan Agner
2015-03-01 22:41 ` Stefan Agner
2015-03-01 22:41 ` Stefan Agner
2015-03-11 0:48 ` Shawn Guo
2015-03-11 0:48 ` Shawn Guo
2015-03-11 4:05 ` Jason Cooper
2015-03-11 4:05 ` Jason Cooper
2015-03-11 4:05 ` Jason Cooper
2015-03-12 9:03 ` Stefan Agner
2015-03-12 9:03 ` Stefan Agner
2015-03-13 4:48 ` Shawn Guo
2015-03-13 4:48 ` Shawn Guo
2015-03-13 4:48 ` Shawn Guo
2015-03-13 9:42 ` Stefan Agner
2015-03-13 9:42 ` Stefan Agner
2015-03-08 5:31 ` [PATCH v6 0/3] irqchip: vf610-mscm: add MSCM interrupt router driver Jason Cooper
2015-03-08 5:31 ` Jason Cooper
2015-03-08 5:31 ` Jason Cooper
2015-03-08 23:43 ` Stefan Agner
2015-03-08 23:43 ` Stefan Agner
2015-03-09 1:22 ` Jason Cooper
2015-03-09 1:22 ` Jason Cooper
2015-03-09 1:22 ` Jason Cooper
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