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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id z6sm7083328wmz.12.2019.12.04.07.35.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Dec 2019 07:35:18 -0800 (PST) Subject: Re: [PATCH 02/11] target/arm: Add arm_mmu_idx_is_stage1 To: Richard Henderson , qemu-devel@nongnu.org References: <20191203225333.17055-1-richard.henderson@linaro.org> <20191203225333.17055-3-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <9f24817e-54dc-dbca-e3f9-09ed185d025f@redhat.com> Date: Wed, 4 Dec 2019 16:35:17 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191203225333.17055-3-richard.henderson@linaro.org> Content-Language: en-US X-MC-Unique: vuYYMlfVMyaLJ9olqW2dQg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/3/19 11:53 PM, Richard Henderson wrote: > Use a common predicate for querying stage1-ness. >=20 > Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=E9 > --- > target/arm/internals.h | 11 +++++++++++ > target/arm/helper.c | 8 +++----- > 2 files changed, 14 insertions(+), 5 deletions(-) >=20 > diff --git a/target/arm/internals.h b/target/arm/internals.h > index 49dac2a677..850f204f14 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -1034,6 +1034,17 @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMS= tate *env) > ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); > #endif > =20 > +static inline bool arm_mmu_idx_is_stage1(ARMMMUIdx mmu_idx) > +{ > + switch (mmu_idx) { > + case ARMMMUIdx_Stage1_E0: > + case ARMMMUIdx_Stage1_E1: > + return true; > + default: > + return false; > + } > +} > + > /* > * Parameters of a given virtual address, as extracted from the > * translation control register (TCR) for a given regime. > diff --git a/target/arm/helper.c b/target/arm/helper.c > index f3785d5ad6..fdb86ea427 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -3212,8 +3212,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint= 64_t value, > bool take_exc =3D false; > =20 > if (fi.s1ptw && current_el =3D=3D 1 && !arm_is_secure(env) > - && (mmu_idx =3D=3D ARMMMUIdx_Stage1_E1 > - || mmu_idx =3D=3D ARMMMUIdx_Stage1_E0)) { > + && arm_mmu_idx_is_stage1(mmu_idx)) { > /* > * Synchronous stage 2 fault on an access made as part of t= he > * translation table walk for AT S1E0* or AT S1E1* insn > @@ -9159,8 +9158,7 @@ static inline bool regime_translation_disabled(CPUA= RMState *env, > } > } > =20 > - if ((env->cp15.hcr_el2 & HCR_DC) && > - (mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_= Stage1_E1)) { > + if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1(mmu_idx)) = { > /* HCR.DC means SCTLR_EL1.M behaves as 0 */ > return true; > } > @@ -9469,7 +9467,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, AR= MMMUIdx mmu_idx, > hwaddr addr, MemTxAttrs txattrs, > ARMMMUFaultInfo *fi) > { > - if ((mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_= Stage1_E1) && > + if (arm_mmu_idx_is_stage1(mmu_idx) && > !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { > target_ulong s2size; > hwaddr s2pa; >=20