From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 230C9C433F5 for ; Tue, 17 May 2022 09:44:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245230AbiEQJow (ORCPT ); Tue, 17 May 2022 05:44:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245377AbiEQJoh (ORCPT ); Tue, 17 May 2022 05:44:37 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11F3F47AD8; Tue, 17 May 2022 02:44:14 -0700 (PDT) X-UUID: 7808b7859d8b418ab7c6aae70101b4d6-20220517 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:4c919e80-f6f1-4c2b-a180-6b1d639b2c9e,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:2a19b09,CLOUDID:2dc47be2-edbf-4bd4-8a34-dfc5f7bb086d,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: 7808b7859d8b418ab7c6aae70101b4d6-20220517 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1524489763; Tue, 17 May 2022 17:44:10 +0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 17 May 2022 17:44:09 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 May 2022 17:44:09 +0800 Received: from mhfsdcap04 (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 May 2022 17:44:07 +0800 Message-ID: <9f290b2bbdfd4b9d46b81d3ab02c2f50999e95e5.camel@mediatek.com> Subject: Re: [PATCH v2 2/2] memory: mtk-smi: Add support for MT6795 Helio X10 From: Yong Wu To: AngeloGioacchino Del Regno , Krzysztof Kozlowski CC: , , , , , , , , , , <~postmarketos/upstreaming@lists.sr.ht>, , , , , , Date: Tue, 17 May 2022 17:44:07 +0800 In-Reply-To: References: <20220513150633.387200-1-angelogioacchino.delregno@collabora.com> <20220513150633.387200-3-angelogioacchino.delregno@collabora.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: phone-devel@vger.kernel.org On Tue, 2022-05-17 at 10:27 +0200, AngeloGioacchino Del Regno wrote: > Il 17/05/22 08:37, Yong Wu ha scritto: > > On Fri, 2022-05-13 at 17:06 +0200, AngeloGioacchino Del Regno > > wrote: > > > The MediaTek Helio X10 (MT6795) SoC has 5 LARBs and one common > > > SMI > > > instance without any sub-common and without GALS. > > > > > > While the smi-common configuration is specific to this SoC, on > > > the > > > LARB side, this is similar to MT8173, in the sense that it > > > doesn't > > > need the port in LARB, and the register layout is also compatible > > > with that one, which makes us able to fully reuse the smi-larb > > > platform data struct that was introduced for MT8173. > > > > > > Signed-off-by: AngeloGioacchino Del Regno < > > > angelogioacchino.delregno@collabora.com> > > > --- > > > drivers/memory/mtk-smi.c | 17 +++++++++++++++++ > > > 1 file changed, 17 insertions(+) > > > > > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > > > index 86a3d34f418e..7e7c3ede19e4 100644 > > > --- a/drivers/memory/mtk-smi.c > > > +++ b/drivers/memory/mtk-smi.c > > > @@ -21,11 +21,13 @@ > > > /* SMI COMMON */ > > > #define SMI_L1LEN 0x100 > > > > > > +#define SMI_L1_ARB 0x200 > > > #define SMI_BUS_SEL 0x220 > > > #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) > > > /* All are MMU0 defaultly. Only specialize mmu1 here. */ > > > #define F_MMU1_LARB(larbid) (0x1 << > > > SMI_BUS_LARB_SHIFT(larbid)) > > > > > > +#define SMI_FIFO_TH0 0x230 > > > > Does the name come from the coda you got? > > It is called SMI_READ_FIFO_TH in my coda. > > > > Documentation for this SoC is not public and I have no access to it, > so > everything that you see here comes from reading downstream kernel > code :-( > > I'll change the name to SMI_READ_FIFO_TH as suggested, thanks! > > > > #define SMI_M4U_TH 0x234 > > > #define SMI_FIFO_TH1 0x238 > > > #define SMI_FIFO_TH2 0x23c > > > @@ -360,6 +362,7 @@ static const struct of_device_id > > > mtk_smi_larb_of_ids[] = { > > > {.compatible = "mediatek,mt2701-smi-larb", .data = > > > &mtk_smi_larb_mt2701}, > > > {.compatible = "mediatek,mt2712-smi-larb", .data = > > > &mtk_smi_larb_mt2712}, > > > {.compatible = "mediatek,mt6779-smi-larb", .data = > > > &mtk_smi_larb_mt6779}, > > > + {.compatible = "mediatek,mt6795-smi-larb", .data = > > > &mtk_smi_larb_mt8173}, > > > {.compatible = "mediatek,mt8167-smi-larb", .data = > > > &mtk_smi_larb_mt8167}, > > > {.compatible = "mediatek,mt8173-smi-larb", .data = > > > &mtk_smi_larb_mt8173}, > > > {.compatible = "mediatek,mt8183-smi-larb", .data = > > > &mtk_smi_larb_mt8183}, > > > @@ -541,6 +544,13 @@ static struct platform_driver > > > mtk_smi_larb_driver = { > > > } > > > }; > > > > > > +static const struct mtk_smi_reg_pair > > > mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = { > > > + {SMI_L1_ARB, 0x1b}, > > > + {SMI_M4U_TH, 0xce810c85}, > > > + {SMI_FIFO_TH1, 0x43214c8}, > > > + {SMI_FIFO_TH0, 0x191f}, > > > +}; > > > + > > > static const struct mtk_smi_reg_pair > > > mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { > > > {SMI_L1LEN, 0xb}, > > > {SMI_M4U_TH, 0xe100e10}, > > > @@ -565,6 +575,12 @@ static const struct mtk_smi_common_plat > > > mtk_smi_common_mt6779 = { > > > F_MMU1_LARB(5) | F_MMU1_LARB(6) | > > > F_MMU1_LARB(7), > > > }; > > > > > > +static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = > > > { > > > + .type = MTK_SMI_GEN2, > > > + .bus_sel = BIT(0), > > > > Like the other larbs, use F_MMU1_LARB(0) here? > > > > I agree that F_MMU1_LARB(0) == (1 << (0 << 1)) == BIT(0), but that > would > not be correct and induce other people to mistake, I think? F_MMU1_LARB(x) means larbx enter MMU1. this is correct for me. OK. Maybe the macro name is not good. About the macro background, please see: 567e58cf96dd (memory: mtk-smi: Add bus_sel for mt8183) If you have better name for this, please tell me:) > Downstream doesn't do MMU1 bits, but MMU0 in this case... but if you > can > check on internal documentation and confirm that the downstream > kernel's > logic is wrong on that - and that you've verified that this should I don't know the detailed downstream code, But I find a internal branch about this SoC. I see the bus_sel did set to 0x1 as you did here. thus I don't think the downstream kernel is wrong. 0x1 means larb0 enter MMU1 while the others still enter MMU0. we could use F_MMU1_LARB(0) here. > indeed > be F_MMU1_LARB(x), you'll get a big(bigger) thank you from me :-) > > Meanwhile... > > Thanks! > Angelo > > > > > After the two changes, > > > > Reviewed-by: Yong Wu > > > > Thanks. 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Tue, 2022-05-17 at 10:27 +0200, AngeloGioacchino Del Regno wrote: > Il 17/05/22 08:37, Yong Wu ha scritto: > > On Fri, 2022-05-13 at 17:06 +0200, AngeloGioacchino Del Regno > > wrote: > > > The MediaTek Helio X10 (MT6795) SoC has 5 LARBs and one common > > > SMI > > > instance without any sub-common and without GALS. > > > > > > While the smi-common configuration is specific to this SoC, on > > > the > > > LARB side, this is similar to MT8173, in the sense that it > > > doesn't > > > need the port in LARB, and the register layout is also compatible > > > with that one, which makes us able to fully reuse the smi-larb > > > platform data struct that was introduced for MT8173. > > > > > > Signed-off-by: AngeloGioacchino Del Regno < > > > angelogioacchino.delregno@collabora.com> > > > --- > > > drivers/memory/mtk-smi.c | 17 +++++++++++++++++ > > > 1 file changed, 17 insertions(+) > > > > > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > > > index 86a3d34f418e..7e7c3ede19e4 100644 > > > --- a/drivers/memory/mtk-smi.c > > > +++ b/drivers/memory/mtk-smi.c > > > @@ -21,11 +21,13 @@ > > > /* SMI COMMON */ > > > #define SMI_L1LEN 0x100 > > > > > > +#define SMI_L1_ARB 0x200 > > > #define SMI_BUS_SEL 0x220 > > > #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) > > > /* All are MMU0 defaultly. Only specialize mmu1 here. */ > > > #define F_MMU1_LARB(larbid) (0x1 << > > > SMI_BUS_LARB_SHIFT(larbid)) > > > > > > +#define SMI_FIFO_TH0 0x230 > > > > Does the name come from the coda you got? > > It is called SMI_READ_FIFO_TH in my coda. > > > > Documentation for this SoC is not public and I have no access to it, > so > everything that you see here comes from reading downstream kernel > code :-( > > I'll change the name to SMI_READ_FIFO_TH as suggested, thanks! > > > > #define SMI_M4U_TH 0x234 > > > #define SMI_FIFO_TH1 0x238 > > > #define SMI_FIFO_TH2 0x23c > > > @@ -360,6 +362,7 @@ static const struct of_device_id > > > mtk_smi_larb_of_ids[] = { > > > {.compatible = "mediatek,mt2701-smi-larb", .data = > > > &mtk_smi_larb_mt2701}, > > > {.compatible = "mediatek,mt2712-smi-larb", .data = > > > &mtk_smi_larb_mt2712}, > > > {.compatible = "mediatek,mt6779-smi-larb", .data = > > > &mtk_smi_larb_mt6779}, > > > + {.compatible = "mediatek,mt6795-smi-larb", .data = > > > &mtk_smi_larb_mt8173}, > > > {.compatible = "mediatek,mt8167-smi-larb", .data = > > > &mtk_smi_larb_mt8167}, > > > {.compatible = "mediatek,mt8173-smi-larb", .data = > > > &mtk_smi_larb_mt8173}, > > > {.compatible = "mediatek,mt8183-smi-larb", .data = > > > &mtk_smi_larb_mt8183}, > > > @@ -541,6 +544,13 @@ static struct platform_driver > > > mtk_smi_larb_driver = { > > > } > > > }; > > > > > > +static const struct mtk_smi_reg_pair > > > mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = { > > > + {SMI_L1_ARB, 0x1b}, > > > + {SMI_M4U_TH, 0xce810c85}, > > > + {SMI_FIFO_TH1, 0x43214c8}, > > > + {SMI_FIFO_TH0, 0x191f}, > > > +}; > > > + > > > static const struct mtk_smi_reg_pair > > > mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { > > > {SMI_L1LEN, 0xb}, > > > {SMI_M4U_TH, 0xe100e10}, > > > @@ -565,6 +575,12 @@ static const struct mtk_smi_common_plat > > > mtk_smi_common_mt6779 = { > > > F_MMU1_LARB(5) | F_MMU1_LARB(6) | > > > F_MMU1_LARB(7), > > > }; > > > > > > +static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = > > > { > > > + .type = MTK_SMI_GEN2, > > > + .bus_sel = BIT(0), > > > > Like the other larbs, use F_MMU1_LARB(0) here? > > > > I agree that F_MMU1_LARB(0) == (1 << (0 << 1)) == BIT(0), but that > would > not be correct and induce other people to mistake, I think? F_MMU1_LARB(x) means larbx enter MMU1. this is correct for me. OK. Maybe the macro name is not good. About the macro background, please see: 567e58cf96dd (memory: mtk-smi: Add bus_sel for mt8183) If you have better name for this, please tell me:) > Downstream doesn't do MMU1 bits, but MMU0 in this case... but if you > can > check on internal documentation and confirm that the downstream > kernel's > logic is wrong on that - and that you've verified that this should I don't know the detailed downstream code, But I find a internal branch about this SoC. I see the bus_sel did set to 0x1 as you did here. thus I don't think the downstream kernel is wrong. 0x1 means larb0 enter MMU1 while the others still enter MMU0. we could use F_MMU1_LARB(0) here. > indeed > be F_MMU1_LARB(x), you'll get a big(bigger) thank you from me :-) > > Meanwhile... > > Thanks! > Angelo > > > > > After the two changes, > > > > Reviewed-by: Yong Wu > > > > Thanks. _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4091C433EF for ; Tue, 17 May 2022 09:46:21 +0000 (UTC) DKIM-Signature: v=1; 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Tue, 17 May 2022 02:44:48 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 May 2022 02:44:10 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 May 2022 17:44:09 +0800 Received: from mhfsdcap04 (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 May 2022 17:44:07 +0800 Message-ID: <9f290b2bbdfd4b9d46b81d3ab02c2f50999e95e5.camel@mediatek.com> Subject: Re: [PATCH v2 2/2] memory: mtk-smi: Add support for MT6795 Helio X10 From: Yong Wu To: AngeloGioacchino Del Regno , Krzysztof Kozlowski CC: , , , , , , , , , , <~postmarketos/upstreaming@lists.sr.ht>, , , , , , Date: Tue, 17 May 2022 17:44:07 +0800 In-Reply-To: References: <20220513150633.387200-1-angelogioacchino.delregno@collabora.com> <20220513150633.387200-3-angelogioacchino.delregno@collabora.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220517_024454_135230_755CA3D9 X-CRM114-Status: GOOD ( 37.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 2022-05-17 at 10:27 +0200, AngeloGioacchino Del Regno wrote: > Il 17/05/22 08:37, Yong Wu ha scritto: > > On Fri, 2022-05-13 at 17:06 +0200, AngeloGioacchino Del Regno > > wrote: > > > The MediaTek Helio X10 (MT6795) SoC has 5 LARBs and one common > > > SMI > > > instance without any sub-common and without GALS. > > > > > > While the smi-common configuration is specific to this SoC, on > > > the > > > LARB side, this is similar to MT8173, in the sense that it > > > doesn't > > > need the port in LARB, and the register layout is also compatible > > > with that one, which makes us able to fully reuse the smi-larb > > > platform data struct that was introduced for MT8173. > > > > > > Signed-off-by: AngeloGioacchino Del Regno < > > > angelogioacchino.delregno@collabora.com> > > > --- > > > drivers/memory/mtk-smi.c | 17 +++++++++++++++++ > > > 1 file changed, 17 insertions(+) > > > > > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > > > index 86a3d34f418e..7e7c3ede19e4 100644 > > > --- a/drivers/memory/mtk-smi.c > > > +++ b/drivers/memory/mtk-smi.c > > > @@ -21,11 +21,13 @@ > > > /* SMI COMMON */ > > > #define SMI_L1LEN 0x100 > > > > > > +#define SMI_L1_ARB 0x200 > > > #define SMI_BUS_SEL 0x220 > > > #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) > > > /* All are MMU0 defaultly. Only specialize mmu1 here. */ > > > #define F_MMU1_LARB(larbid) (0x1 << > > > SMI_BUS_LARB_SHIFT(larbid)) > > > > > > +#define SMI_FIFO_TH0 0x230 > > > > Does the name come from the coda you got? > > It is called SMI_READ_FIFO_TH in my coda. > > > > Documentation for this SoC is not public and I have no access to it, > so > everything that you see here comes from reading downstream kernel > code :-( > > I'll change the name to SMI_READ_FIFO_TH as suggested, thanks! > > > > #define SMI_M4U_TH 0x234 > > > #define SMI_FIFO_TH1 0x238 > > > #define SMI_FIFO_TH2 0x23c > > > @@ -360,6 +362,7 @@ static const struct of_device_id > > > mtk_smi_larb_of_ids[] = { > > > {.compatible = "mediatek,mt2701-smi-larb", .data = > > > &mtk_smi_larb_mt2701}, > > > {.compatible = "mediatek,mt2712-smi-larb", .data = > > > &mtk_smi_larb_mt2712}, > > > {.compatible = "mediatek,mt6779-smi-larb", .data = > > > &mtk_smi_larb_mt6779}, > > > + {.compatible = "mediatek,mt6795-smi-larb", .data = > > > &mtk_smi_larb_mt8173}, > > > {.compatible = "mediatek,mt8167-smi-larb", .data = > > > &mtk_smi_larb_mt8167}, > > > {.compatible = "mediatek,mt8173-smi-larb", .data = > > > &mtk_smi_larb_mt8173}, > > > {.compatible = "mediatek,mt8183-smi-larb", .data = > > > &mtk_smi_larb_mt8183}, > > > @@ -541,6 +544,13 @@ static struct platform_driver > > > mtk_smi_larb_driver = { > > > } > > > }; > > > > > > +static const struct mtk_smi_reg_pair > > > mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = { > > > + {SMI_L1_ARB, 0x1b}, > > > + {SMI_M4U_TH, 0xce810c85}, > > > + {SMI_FIFO_TH1, 0x43214c8}, > > > + {SMI_FIFO_TH0, 0x191f}, > > > +}; > > > + > > > static const struct mtk_smi_reg_pair > > > mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { > > > {SMI_L1LEN, 0xb}, > > > {SMI_M4U_TH, 0xe100e10}, > > > @@ -565,6 +575,12 @@ static const struct mtk_smi_common_plat > > > mtk_smi_common_mt6779 = { > > > F_MMU1_LARB(5) | F_MMU1_LARB(6) | > > > F_MMU1_LARB(7), > > > }; > > > > > > +static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = > > > { > > > + .type = MTK_SMI_GEN2, > > > + .bus_sel = BIT(0), > > > > Like the other larbs, use F_MMU1_LARB(0) here? > > > > I agree that F_MMU1_LARB(0) == (1 << (0 << 1)) == BIT(0), but that > would > not be correct and induce other people to mistake, I think? F_MMU1_LARB(x) means larbx enter MMU1. this is correct for me. OK. Maybe the macro name is not good. About the macro background, please see: 567e58cf96dd (memory: mtk-smi: Add bus_sel for mt8183) If you have better name for this, please tell me:) > Downstream doesn't do MMU1 bits, but MMU0 in this case... but if you > can > check on internal documentation and confirm that the downstream > kernel's > logic is wrong on that - and that you've verified that this should I don't know the detailed downstream code, But I find a internal branch about this SoC. I see the bus_sel did set to 0x1 as you did here. thus I don't think the downstream kernel is wrong. 0x1 means larb0 enter MMU1 while the others still enter MMU0. we could use F_MMU1_LARB(0) here. > indeed > be F_MMU1_LARB(x), you'll get a big(bigger) thank you from me :-) > > Meanwhile... > > Thanks! > Angelo > > > > > After the two changes, > > > > Reviewed-by: Yong Wu > > > > Thanks. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel