From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753805AbeE3R1Y (ORCPT ); Wed, 30 May 2018 13:27:24 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:55065 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753653AbeE3R1T (ORCPT ); Wed, 30 May 2018 13:27:19 -0400 X-Google-Smtp-Source: ADUXVKJWYTgauScPqA+3zlB8Bw/znTrGOpAsZfzQL54r9qLqDk6+EcCIcOhZAOTQAPMjwi+PIDBXDA== Subject: Re: [PATCH 2/6] PCI: iproc: Add INTx support with better modeling To: Andy Shevchenko Cc: Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring , Mark Rutland , Linux Kernel Mailing List , bcm-kernel-feedback-list , linux-pci@vger.kernel.org, devicetree , linux-arm Mailing List References: <1527631130-20045-1-git-send-email-ray.jui@broadcom.com> <1527631130-20045-3-git-send-email-ray.jui@broadcom.com> From: Ray Jui Message-ID: <9f4aedd8-17e0-3747-3bdb-2f2dc0a20756@broadcom.com> Date: Wed, 30 May 2018 10:27:12 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andy, On 5/29/2018 5:59 PM, Andy Shevchenko wrote: > On Wed, May 30, 2018 at 12:58 AM, Ray Jui wrote: >> Add PCIe legacy interrupt INTx support to the iProc PCIe driver by >> modeling it with its own IRQ domain. All 4 interrupts INTA, INTB, INTC, >> INTD share the same interrupt line connected to the GIC in the system, >> while the status of each INTx can be obtained through the INTX CSR >> register > >> + while ((status = iproc_pcie_read_reg(pcie, IPROC_PCIE_INTX_CSR) & >> + SYS_RC_INTX_MASK) != 0) { >> + for_each_set_bit(bit, &status, PCI_NUM_INTX) { >> + virq = irq_find_mapping(pcie->irq_domain, bit + 1); >> + if (virq) >> + generic_handle_irq(virq); >> + else >> + dev_err(dev, "unexpected INTx%u\n", bit); >> + } >> + } > > do { > status = ...; > for_each_set_bit() { > ... > } > } while (status); > > would look slightly better for my opinion. > Indeed. I agree with you. I'll wait for comments before sending out v2 which will include this improvement. Thanks, Ray From mboxrd@z Thu Jan 1 00:00:00 1970 From: ray.jui@broadcom.com (Ray Jui) Date: Wed, 30 May 2018 10:27:12 -0700 Subject: [PATCH 2/6] PCI: iproc: Add INTx support with better modeling In-Reply-To: References: <1527631130-20045-1-git-send-email-ray.jui@broadcom.com> <1527631130-20045-3-git-send-email-ray.jui@broadcom.com> Message-ID: <9f4aedd8-17e0-3747-3bdb-2f2dc0a20756@broadcom.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Andy, On 5/29/2018 5:59 PM, Andy Shevchenko wrote: > On Wed, May 30, 2018 at 12:58 AM, Ray Jui wrote: >> Add PCIe legacy interrupt INTx support to the iProc PCIe driver by >> modeling it with its own IRQ domain. All 4 interrupts INTA, INTB, INTC, >> INTD share the same interrupt line connected to the GIC in the system, >> while the status of each INTx can be obtained through the INTX CSR >> register > >> + while ((status = iproc_pcie_read_reg(pcie, IPROC_PCIE_INTX_CSR) & >> + SYS_RC_INTX_MASK) != 0) { >> + for_each_set_bit(bit, &status, PCI_NUM_INTX) { >> + virq = irq_find_mapping(pcie->irq_domain, bit + 1); >> + if (virq) >> + generic_handle_irq(virq); >> + else >> + dev_err(dev, "unexpected INTx%u\n", bit); >> + } >> + } > > do { > status = ...; > for_each_set_bit() { > ... > } > } while (status); > > would look slightly better for my opinion. > Indeed. I agree with you. I'll wait for comments before sending out v2 which will include this improvement. Thanks, Ray