From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90976C47247 for ; Sat, 9 May 2020 12:54:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7282320820 for ; Sat, 9 May 2020 12:54:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728004AbgEIMyG (ORCPT ); Sat, 9 May 2020 08:54:06 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:60004 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727122AbgEIMyG (ORCPT ); Sat, 9 May 2020 08:54:06 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: ezequiel) with ESMTPSA id CE30B2A2CA6 Message-ID: <9fdceef69a390235225a8fd08f89f67be9c5c920.camel@collabora.com> Subject: Re: [PATCH v2 8/9] arm64: dts: rockchip: add rx0 mipi-phy for rk3399 From: Ezequiel Garcia To: Helen Koike , devicetree@vger.kernel.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, Heiko Stuebner Cc: linux-kernel@vger.kernel.org, devel@driverdev.osuosl.org, robh+dt@kernel.org, heiko@sntech.de, hverkuil-cisco@xs4all.nl, kernel@collabora.com, dafna.hirschfeld@collabora.com, mark.rutland@arm.com, karthik.poduval@gmail.com, jbx6244@gmail.com, kishon@ti.com Date: Sat, 09 May 2020 09:53:53 -0300 In-Reply-To: <20200403161538.1375908-9-helen.koike@collabora.com> References: <20200403161538.1375908-1-helen.koike@collabora.com> <20200403161538.1375908-9-helen.koike@collabora.com> Organization: Collabora Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.36.0-1 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Heiko, On Fri, 2020-04-03 at 13:15 -0300, Helen Koike wrote: > From: Shunqian Zheng > > Designware MIPI D-PHY, used for ISP0 in rk3399. > > Verified with: > make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml > > Signed-off-by: Shunqian Zheng > Signed-off-by: Jacob Chen > Signed-off-by: Helen Koike > > --- > > Changes in v2: > - fix alignment of clocks > > V1: > This patchset came from the original ISP series from Rockchip: > > https://patchwork.kernel.org/patch/10267409/ > Can you take the devicetree changes (patches 8 and 9) ? Thanks, Ezequiel > The only difference is: > - add phy-cells > - update compatible to "rockchip,rk3399-mipi-dphy-rx0" > - commit message > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > index 33cc21fcf4c10..6b3380b10e596 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -1394,6 +1394,17 @@ io_domains: io-domains { > status = "disabled"; > }; > > + mipi_dphy_rx0: mipi-dphy-rx0 { > + compatible = "rockchip,rk3399-mipi-dphy-rx0"; > + clocks = <&cru SCLK_MIPIDPHY_REF>, > + <&cru SCLK_DPHY_RX0_CFG>, > + <&cru PCLK_VIO_GRF>; > + clock-names = "dphy-ref", "dphy-cfg", "grf"; > + power-domains = <&power RK3399_PD_VIO>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > u2phy0: usb2-phy@e450 { > compatible = "rockchip,rk3399-usb2phy"; > reg = <0xe450 0x10>; > -- > 2.26.0 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D559C47255 for ; Sat, 9 May 2020 12:54:11 +0000 (UTC) Received: from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3D69120820 for ; Sat, 9 May 2020 12:54:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3D69120820 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=collabora.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=driverdev-devel-bounces@linuxdriverproject.org Received: from localhost (localhost [127.0.0.1]) by silver.osuosl.org (Postfix) with ESMTP id C489D2302C; Sat, 9 May 2020 12:54:10 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from silver.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IIdX4qoO144f; Sat, 9 May 2020 12:54:09 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by silver.osuosl.org (Postfix) with ESMTP id 555C822F22; Sat, 9 May 2020 12:54:09 +0000 (UTC) Received: from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137]) by ash.osuosl.org (Postfix) with ESMTP id 82FC81BF3DD for ; Sat, 9 May 2020 12:54:07 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id 7D3E086FFD for ; Sat, 9 May 2020 12:54:07 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cY_YZPFXaMVm for ; Sat, 9 May 2020 12:54:06 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by fraxinus.osuosl.org (Postfix) with ESMTPS id 3FCDA86F80 for ; Sat, 9 May 2020 12:54:06 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: ezequiel) with ESMTPSA id CE30B2A2CA6 Message-ID: <9fdceef69a390235225a8fd08f89f67be9c5c920.camel@collabora.com> Subject: Re: [PATCH v2 8/9] arm64: dts: rockchip: add rx0 mipi-phy for rk3399 From: Ezequiel Garcia To: Helen Koike , devicetree@vger.kernel.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, Heiko Stuebner Date: Sat, 09 May 2020 09:53:53 -0300 In-Reply-To: <20200403161538.1375908-9-helen.koike@collabora.com> References: <20200403161538.1375908-1-helen.koike@collabora.com> <20200403161538.1375908-9-helen.koike@collabora.com> Organization: Collabora User-Agent: Evolution 3.36.0-1 MIME-Version: 1.0 X-BeenThere: driverdev-devel@linuxdriverproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux Driver Project Developer List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devel@driverdev.osuosl.org, mark.rutland@arm.com, dafna.hirschfeld@collabora.com, heiko@sntech.de, kishon@ti.com, linux-kernel@vger.kernel.org, karthik.poduval@gmail.com, robh+dt@kernel.org, hverkuil-cisco@xs4all.nl, jbx6244@gmail.com, kernel@collabora.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: driverdev-devel-bounces@linuxdriverproject.org Sender: "devel" Hi Heiko, On Fri, 2020-04-03 at 13:15 -0300, Helen Koike wrote: > From: Shunqian Zheng > > Designware MIPI D-PHY, used for ISP0 in rk3399. > > Verified with: > make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml > > Signed-off-by: Shunqian Zheng > Signed-off-by: Jacob Chen > Signed-off-by: Helen Koike > > --- > > Changes in v2: > - fix alignment of clocks > > V1: > This patchset came from the original ISP series from Rockchip: > > https://patchwork.kernel.org/patch/10267409/ > Can you take the devicetree changes (patches 8 and 9) ? Thanks, Ezequiel > The only difference is: > - add phy-cells > - update compatible to "rockchip,rk3399-mipi-dphy-rx0" > - commit message > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > index 33cc21fcf4c10..6b3380b10e596 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -1394,6 +1394,17 @@ io_domains: io-domains { > status = "disabled"; > }; > > + mipi_dphy_rx0: mipi-dphy-rx0 { > + compatible = "rockchip,rk3399-mipi-dphy-rx0"; > + clocks = <&cru SCLK_MIPIDPHY_REF>, > + <&cru SCLK_DPHY_RX0_CFG>, > + <&cru PCLK_VIO_GRF>; > + clock-names = "dphy-ref", "dphy-cfg", "grf"; > + power-domains = <&power RK3399_PD_VIO>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > u2phy0: usb2-phy@e450 { > compatible = "rockchip,rk3399-usb2phy"; > reg = <0xe450 0x10>; > -- > 2.26.0 > > _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ezequiel Garcia Subject: Re: [PATCH v2 8/9] arm64: dts: rockchip: add rx0 mipi-phy for rk3399 Date: Sat, 09 May 2020 09:53:53 -0300 Message-ID: <9fdceef69a390235225a8fd08f89f67be9c5c920.camel@collabora.com> References: <20200403161538.1375908-1-helen.koike@collabora.com> <20200403161538.1375908-9-helen.koike@collabora.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20200403161538.1375908-9-helen.koike-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Helen Koike , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org, hverkuil-cisco-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org, kernel-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org, dafna.hirschfeld-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, karthik.poduval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, jbx6244-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, kishon-l0cyMroinI0@public.gmane.org List-Id: linux-rockchip.vger.kernel.org Hi Heiko, On Fri, 2020-04-03 at 13:15 -0300, Helen Koike wrote: > From: Shunqian Zheng > > Designware MIPI D-PHY, used for ISP0 in rk3399. > > Verified with: > make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml > > Signed-off-by: Shunqian Zheng > Signed-off-by: Jacob Chen > Signed-off-by: Helen Koike > > --- > > Changes in v2: > - fix alignment of clocks > > V1: > This patchset came from the original ISP series from Rockchip: > > https://patchwork.kernel.org/patch/10267409/ > Can you take the devicetree changes (patches 8 and 9) ? Thanks, Ezequiel > The only difference is: > - add phy-cells > - update compatible to "rockchip,rk3399-mipi-dphy-rx0" > - commit message > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > index 33cc21fcf4c10..6b3380b10e596 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -1394,6 +1394,17 @@ io_domains: io-domains { > status = "disabled"; > }; > > + mipi_dphy_rx0: mipi-dphy-rx0 { > + compatible = "rockchip,rk3399-mipi-dphy-rx0"; > + clocks = <&cru SCLK_MIPIDPHY_REF>, > + <&cru SCLK_DPHY_RX0_CFG>, > + <&cru PCLK_VIO_GRF>; > + clock-names = "dphy-ref", "dphy-cfg", "grf"; > + power-domains = <&power RK3399_PD_VIO>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > u2phy0: usb2-phy@e450 { > compatible = "rockchip,rk3399-usb2phy"; > reg = <0xe450 0x10>; > -- > 2.26.0 > >