From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00DFDC433EF for ; Tue, 14 Dec 2021 14:16:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234791AbhLNOQd (ORCPT ); Tue, 14 Dec 2021 09:16:33 -0500 Received: from foss.arm.com ([217.140.110.172]:57056 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234834AbhLNOQd (ORCPT ); Tue, 14 Dec 2021 09:16:33 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EC2A4139F; Tue, 14 Dec 2021 06:16:32 -0800 (PST) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D021B3F793; Tue, 14 Dec 2021 06:16:31 -0800 (PST) From: Robin Murphy To: will@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: catalin.marinas@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 4/5] dt-bindings: perf: Convert Arm DSU to schema Date: Tue, 14 Dec 2021 14:16:16 +0000 Message-Id: <9fde2e11b0d11285c26d0e9d261034a1628c7901.1639490264.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.28.0.dirty In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the DSU binding to schema, as one does. Signed-off-by: Robin Murphy --- v2: Actually finish converting the thing to valid schema... .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ------------ .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++ 2 files changed, 41 insertions(+), 27 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt deleted file mode 100644 index 6efabba530f1..000000000000 --- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt +++ /dev/null @@ -1,27 +0,0 @@ -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) - -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores -with a shared L3 memory system, control logic and external interfaces to -form a multicore cluster. The PMU enables to gather various statistics on -the operations of the DSU. The PMU provides independent 32bit counters that -can count any of the supported events, along with a 64bit cycle counter. -The PMU is accessed via CPU system registers and has no MMIO component. - -** DSU PMU required properties: - -- compatible : should be one of : - - "arm,dsu-pmu" - -- interrupts : Exactly 1 SPI must be listed. - -- cpus : List of phandles for the CPUs connected to this DSU instance. - - -** Example: - -dsu-pmu-0 { - compatible = "arm,dsu-pmu"; - interrupts = ; - cpus = <&cpu_0>, <&cpu_1>; -}; diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml new file mode 100644 index 000000000000..09ddeb6a3ccc --- /dev/null +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2021 Arm Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) + +maintainers: + - Suzuki K Poulose + - Robin Murphy + +description: + ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores with a shared + L3 memory system, control logic and external interfaces to form a multicore + cluster. The PMU enables gathering various statistics on the operation of the + DSU. The PMU provides independent 32-bit counters that can count any of the + supported events, along with a 64-bit cycle counter. The PMU is accessed via + CPU system registers and has no MMIO component. + +properties: + compatible: + const: arm,dsu-pmu + + interrupts: + items: + - description: nCLUSTERPMUIRQ interrupt + + cpus: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 8 + description: List of phandles for the CPUs connected to this DSU instance. + +required: + - compatible + - interrupts + - cpus + +additionalProperties: false -- 2.28.0.dirty From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79991C433EF for ; Tue, 14 Dec 2021 14:18:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6k3AcGEqf0KqSL6fzI5VvQbOOnJssIhip5M4FNxpSpo=; b=oLWyUwJz27JHs7 8itM7rAKIwuYIjHzBIW0B/lt2hES1317X2V4DaL86pI7zijvvzkmcF+Xp9qnijT6n/JVJ5XcqGKFf yqqF2NDVmRGDgfNKrnfiue/uJbb9FdS06bOE6hE+U0ACw4D5gWI+VMUp4NRMIU4XTzJi92aHGRs5r kPBvqYnMqFiNEJoH9MACvnb9EHjOB85GbOyTINfPzWgn353Wt94SXer3iv/SDuAPolcDbZNaE5Pa8 tGwWcvEGuR9z+juaFQ8W2p7xCodiajkBeuWr+XCBgSxXzHVGOow9LzGYkSzpBhesH4Nldr4yoA7m9 agwagv3T3kmElrEDe/Jg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx8cN-00EKi8-0d; Tue, 14 Dec 2021 14:17:23 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx8ba-00EKTs-4C for linux-arm-kernel@lists.infradead.org; Tue, 14 Dec 2021 14:16:36 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EC2A4139F; Tue, 14 Dec 2021 06:16:32 -0800 (PST) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D021B3F793; Tue, 14 Dec 2021 06:16:31 -0800 (PST) From: Robin Murphy To: will@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: catalin.marinas@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 4/5] dt-bindings: perf: Convert Arm DSU to schema Date: Tue, 14 Dec 2021 14:16:16 +0000 Message-Id: <9fde2e11b0d11285c26d0e9d261034a1628c7901.1639490264.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.28.0.dirty In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_061634_286050_5FD9ED88 X-CRM114-Status: GOOD ( 12.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert the DSU binding to schema, as one does. Signed-off-by: Robin Murphy --- v2: Actually finish converting the thing to valid schema... .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ------------ .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++ 2 files changed, 41 insertions(+), 27 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt deleted file mode 100644 index 6efabba530f1..000000000000 --- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt +++ /dev/null @@ -1,27 +0,0 @@ -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) - -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores -with a shared L3 memory system, control logic and external interfaces to -form a multicore cluster. The PMU enables to gather various statistics on -the operations of the DSU. The PMU provides independent 32bit counters that -can count any of the supported events, along with a 64bit cycle counter. -The PMU is accessed via CPU system registers and has no MMIO component. - -** DSU PMU required properties: - -- compatible : should be one of : - - "arm,dsu-pmu" - -- interrupts : Exactly 1 SPI must be listed. - -- cpus : List of phandles for the CPUs connected to this DSU instance. - - -** Example: - -dsu-pmu-0 { - compatible = "arm,dsu-pmu"; - interrupts = ; - cpus = <&cpu_0>, <&cpu_1>; -}; diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml new file mode 100644 index 000000000000..09ddeb6a3ccc --- /dev/null +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2021 Arm Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) + +maintainers: + - Suzuki K Poulose + - Robin Murphy + +description: + ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores with a shared + L3 memory system, control logic and external interfaces to form a multicore + cluster. The PMU enables gathering various statistics on the operation of the + DSU. The PMU provides independent 32-bit counters that can count any of the + supported events, along with a 64-bit cycle counter. The PMU is accessed via + CPU system registers and has no MMIO component. + +properties: + compatible: + const: arm,dsu-pmu + + interrupts: + items: + - description: nCLUSTERPMUIRQ interrupt + + cpus: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 8 + description: List of phandles for the CPUs connected to this DSU instance. + +required: + - compatible + - interrupts + - cpus + +additionalProperties: false -- 2.28.0.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel