From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34C40C11F64 for ; Tue, 29 Jun 2021 02:52:21 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AE19161D05 for ; Tue, 29 Jun 2021 02:52:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AE19161D05 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:33692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ly3rH-0007gv-Kq for qemu-devel@archiver.kernel.org; Mon, 28 Jun 2021 22:52:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58146) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ly3qb-0006up-12; Mon, 28 Jun 2021 22:51:37 -0400 Received: from out28-76.mail.aliyun.com ([115.124.28.76]:49192) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ly3qV-0008RW-R1; Mon, 28 Jun 2021 22:51:36 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07452463|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_enroll_verification|0.0029479-0.000897628-0.996154; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047201; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.KZYlZgT_1624935084; Received: from 10.0.2.15(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KZYlZgT_1624935084) by smtp.aliyun-inc.com(10.147.43.95); Tue, 29 Jun 2021 10:51:24 +0800 Subject: Re: [RFC PATCH 03/11] hw/intc: Add CLIC device To: Frank Chang References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> <20210409074857.166082-4-zhiwei_liu@c-sky.com> From: LIU Zhiwei Message-ID: <9ff6e3f9-58ff-7a9b-2678-486d0f3b9cdf@c-sky.com> Date: Tue, 29 Jun 2021 10:50:15 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/alternative; boundary="------------55895C893B79C53052CBD4CE" Content-Language: en-US Received-SPF: none client-ip=115.124.28.76; envelope-from=zhiwei_liu@c-sky.com; helo=out28-76.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, HTML_MESSAGE=0.001, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , Alistair Francis , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is a multi-part message in MIME format. --------------55895C893B79C53052CBD4CE Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit On 2021/6/26 下午11:20, Frank Chang wrote: > LIU Zhiwei > 於 > 2021年4月9日 週五 下午3:57寫道： > > > + > +/* > + * riscv_clic_create: > + * > + * @addr: base address of M-Mode CLIC memory-mapped registers > + * @prv_s: have smode region > + * @prv_u: have umode region > + * @num_harts: number of CPU harts > + * @num_sources: number of interrupts supporting by each aperture > + * @clicintctlbits: bits are actually implemented in the > clicintctl registers > + * @version: clic version, such as "v0.9" > + * > + * Returns: the device object > + */ > +DeviceState *riscv_clic_create(hwaddr addr, bool prv_s, bool prv_u, > +                               uint32_t num_harts, uint32_t > num_sources, > +                               uint8_t clicintctlbits, > +                               const char *version) > +{ > +    DeviceState *dev = qdev_new(TYPE_RISCV_CLIC); > + > +    assert(num_sources <= 4096); > +    assert(num_harts <= 1024); > +    assert(clicintctlbits <= 8); > +    assert(!strcmp(version, "v0.8") || !strcmp(version, "v0.9")); > + > +    qdev_prop_set_bit(dev, "prv-s", prv_s); > +    qdev_prop_set_bit(dev, "prv-u", prv_u); > +    qdev_prop_set_uint32(dev, "num-harts", num_harts); > +    qdev_prop_set_uint32(dev, "num-sources", num_sources); > +    qdev_prop_set_uint32(dev, "clicintctlbits", clicintctlbits); > +    qdev_prop_set_uint64(dev, "mclicbase", addr); > > > According to spec: >   Since the CLIC memory map must be aligned at a 4KiB boundary, >   the mclicbase CSR has its 12 least-significant bits hardwired to zero. >   It is used to inform software about the location of CLIC memory > mappped registers. > > I think it's better to add another addr check to ensure it's 4KiB aligned. > Agree. Thanks, Zhiwei > Thanks, > Frank Chang > > +    qdev_prop_set_string(dev, "version", version); > + > +    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > +    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); > +    return dev; > +} > + > --------------55895C893B79C53052CBD4CE Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 8bit


On 2021/6/26 下午11:20, Frank Chang wrote:
LIU Zhiwei <zhiwei_liu@c-sky.com> 於 2021年4月9日 週五 下午3:57寫道：

+
+/*
+ * riscv_clic_create:
+ *
+ * @addr: base address of M-Mode CLIC memory-mapped registers
+ * @prv_s: have smode region
+ * @prv_u: have umode region
+ * @num_harts: number of CPU harts
+ * @num_sources: number of interrupts supporting by each aperture
+ * @clicintctlbits: bits are actually implemented in the clicintctl registers
+ * @version: clic version, such as "v0.9"
+ *
+ * Returns: the device object
+ */
+DeviceState *riscv_clic_create(hwaddr addr, bool prv_s, bool prv_u,
+                               uint32_t num_harts, uint32_t num_sources,
+                               uint8_t clicintctlbits,
+                               const char *version)
+{
+    DeviceState *dev = qdev_new(TYPE_RISCV_CLIC);
+
+    assert(num_sources <= 4096);
+    assert(num_harts <= 1024);
+    assert(clicintctlbits <= 8);
+    assert(!strcmp(version, "v0.8") || !strcmp(version, "v0.9"));
+
+    qdev_prop_set_bit(dev, "prv-s", prv_s);
+    qdev_prop_set_bit(dev, "prv-u", prv_u);
+    qdev_prop_set_uint32(dev, "num-harts", num_harts);
+    qdev_prop_set_uint32(dev, "num-sources", num_sources);
+    qdev_prop_set_uint32(dev, "clicintctlbits", clicintctlbits);
+    qdev_prop_set_uint64(dev, "mclicbase", addr);

According to spec:
  Since the CLIC memory map must be aligned at a 4KiB boundary,
  the mclicbase CSR has its 12 least-significant bits hardwired to zero.
  It is used to inform software about the location of CLIC memory mappped registers.

I think it's better to add another addr check to ensure it's 4KiB aligned.

Agree.

Thanks,
Zhiwei

Thanks,
Frank Chang
 
+    qdev_prop_set_string(dev, "version", version);
+
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+    return dev;
+}
+

--------------55895C893B79C53052CBD4CE-- From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ly3qc-0006v2-2L for mharc-qemu-riscv@gnu.org; Mon, 28 Jun 2021 22:51:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58146) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ly3qb-0006up-12; Mon, 28 Jun 2021 22:51:37 -0400 Received: from out28-76.mail.aliyun.com ([115.124.28.76]:49192) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ly3qV-0008RW-R1; Mon, 28 Jun 2021 22:51:36 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07452463|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_enroll_verification|0.0029479-0.000897628-0.996154; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047201; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.KZYlZgT_1624935084; Received: from 10.0.2.15(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KZYlZgT_1624935084) by smtp.aliyun-inc.com(10.147.43.95); Tue, 29 Jun 2021 10:51:24 +0800 Subject: Re: [RFC PATCH 03/11] hw/intc: Add CLIC device To: Frank Chang Cc: "qemu-devel@nongnu.org Developers" , "open list:RISC-V" , Palmer Dabbelt , Alistair Francis , wxy194768@alibaba-inc.com References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> <20210409074857.166082-4-zhiwei_liu@c-sky.com> From: LIU Zhiwei Message-ID: <9ff6e3f9-58ff-7a9b-2678-486d0f3b9cdf@c-sky.com> Date: Tue, 29 Jun 2021 10:50:15 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/alternative; boundary="------------55895C893B79C53052CBD4CE" Content-Language: en-US Received-SPF: none client-ip=115.124.28.76; envelope-from=zhiwei_liu@c-sky.com; helo=out28-76.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, HTML_MESSAGE=0.001, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Jun 2021 02:51:37 -0000 This is a multi-part message in MIME format. --------------55895C893B79C53052CBD4CE Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit On 2021/6/26 下午11:20, Frank Chang wrote: > LIU Zhiwei > 於 > 2021年4月9日 週五 下午3:57寫道： > > > + > +/* > + * riscv_clic_create: > + * > + * @addr: base address of M-Mode CLIC memory-mapped registers > + * @prv_s: have smode region > + * @prv_u: have umode region > + * @num_harts: number of CPU harts > + * @num_sources: number of interrupts supporting by each aperture > + * @clicintctlbits: bits are actually implemented in the > clicintctl registers > + * @version: clic version, such as "v0.9" > + * > + * Returns: the device object > + */ > +DeviceState *riscv_clic_create(hwaddr addr, bool prv_s, bool prv_u, > +                               uint32_t num_harts, uint32_t > num_sources, > +                               uint8_t clicintctlbits, > +                               const char *version) > +{ > +    DeviceState *dev = qdev_new(TYPE_RISCV_CLIC); > + > +    assert(num_sources <= 4096); > +    assert(num_harts <= 1024); > +    assert(clicintctlbits <= 8); > +    assert(!strcmp(version, "v0.8") || !strcmp(version, "v0.9")); > + > +    qdev_prop_set_bit(dev, "prv-s", prv_s); > +    qdev_prop_set_bit(dev, "prv-u", prv_u); > +    qdev_prop_set_uint32(dev, "num-harts", num_harts); > +    qdev_prop_set_uint32(dev, "num-sources", num_sources); > +    qdev_prop_set_uint32(dev, "clicintctlbits", clicintctlbits); > +    qdev_prop_set_uint64(dev, "mclicbase", addr); > > > According to spec: >   Since the CLIC memory map must be aligned at a 4KiB boundary, >   the mclicbase CSR has its 12 least-significant bits hardwired to zero. >   It is used to inform software about the location of CLIC memory > mappped registers. > > I think it's better to add another addr check to ensure it's 4KiB aligned. > Agree. Thanks, Zhiwei > Thanks, > Frank Chang > > +    qdev_prop_set_string(dev, "version", version); > + > +    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > +    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); > +    return dev; > +} > + > --------------55895C893B79C53052CBD4CE Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 8bit


On 2021/6/26 下午11:20, Frank Chang wrote:
LIU Zhiwei <zhiwei_liu@c-sky.com> 於 2021年4月9日 週五 下午3:57寫道：

+
+/*
+ * riscv_clic_create:
+ *
+ * @addr: base address of M-Mode CLIC memory-mapped registers
+ * @prv_s: have smode region
+ * @prv_u: have umode region
+ * @num_harts: number of CPU harts
+ * @num_sources: number of interrupts supporting by each aperture
+ * @clicintctlbits: bits are actually implemented in the clicintctl registers
+ * @version: clic version, such as "v0.9"
+ *
+ * Returns: the device object
+ */
+DeviceState *riscv_clic_create(hwaddr addr, bool prv_s, bool prv_u,
+                               uint32_t num_harts, uint32_t num_sources,
+                               uint8_t clicintctlbits,
+                               const char *version)
+{
+    DeviceState *dev = qdev_new(TYPE_RISCV_CLIC);
+
+    assert(num_sources <= 4096);
+    assert(num_harts <= 1024);
+    assert(clicintctlbits <= 8);
+    assert(!strcmp(version, "v0.8") || !strcmp(version, "v0.9"));
+
+    qdev_prop_set_bit(dev, "prv-s", prv_s);
+    qdev_prop_set_bit(dev, "prv-u", prv_u);
+    qdev_prop_set_uint32(dev, "num-harts", num_harts);
+    qdev_prop_set_uint32(dev, "num-sources", num_sources);
+    qdev_prop_set_uint32(dev, "clicintctlbits", clicintctlbits);
+    qdev_prop_set_uint64(dev, "mclicbase", addr);

According to spec:
  Since the CLIC memory map must be aligned at a 4KiB boundary,
  the mclicbase CSR has its 12 least-significant bits hardwired to zero.
  It is used to inform software about the location of CLIC memory mappped registers.

I think it's better to add another addr check to ensure it's 4KiB aligned.

Agree.

Thanks,
Zhiwei

Thanks,
Frank Chang
 
+    qdev_prop_set_string(dev, "version", version);
+
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+    return dev;
+}
+

--------------55895C893B79C53052CBD4CE--