From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57E4FC47093 for ; Sun, 30 May 2021 11:09:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 38D046108D for ; Sun, 30 May 2021 11:09:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229784AbhE3LKo (ORCPT ); Sun, 30 May 2021 07:10:44 -0400 Received: from new3-smtp.messagingengine.com ([66.111.4.229]:44003 "EHLO new3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229500AbhE3LKl (ORCPT ); Sun, 30 May 2021 07:10:41 -0400 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailnew.nyi.internal (Postfix) with ESMTP id 31C255849E1; Sun, 30 May 2021 07:09:03 -0400 (EDT) Received: from imap21 ([10.202.2.71]) by compute3.internal (MEProxy); Sun, 30 May 2021 07:09:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svenpeter.dev; h=mime-version:message-id:in-reply-to:references:date:from:to :cc:subject:content-type; s=fm1; bh=2hN+Y6whIltMm10I8URjSpg82Tc2 xNvQpJgef9e0Lso=; b=3yxm8ZMxOOpax8We+5bmJ1kcUXGO118hg7ilPzQ8Pdyp 1RUu/oUotRGBMHONPuHAl6HLJIkwfYvGj6JVCvWPg1X7244159mygY0xi9ujZWV1 /GSOdilq9hDIJRU2ScziiwR/U21hQwxUcZzlp1MWOACYPwKVRFMzFclSp35B78qz s75lF7q+Eog0U8AhEsuSpF//QMtZo0r+JFa5Dw3O6nvVlGzIiDZK6L+LrlnHi9mi ZLoAcbSlezBYH2SB6a8ETeTf2HZCiFnb0J4JLReFDsA4hUjQU8vj/CKKoZExrTzL uy3XjavLMsDa5ITwglUMrC+aOgqRXOmu2T+qR1cW/A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm2; bh=2hN+Y6 whIltMm10I8URjSpg82Tc2xNvQpJgef9e0Lso=; b=E+E/wiF5bQgY4EgKydN4PM A1KAWksDctqpsGZ3nqW0O+o5OMMBaLmg2jT8VNsXYHA21giDbk1ppJzxpCSD2dw9 EJR+xx9wg0OFbBEyCJbQQcb1IrlWPJkJ50PPYYBWkBFNKET1fW97BFrJ99U5r110 gtF3FCBIMYVtNDfCD45xFULbBoWQeXlewrBNbWdaueKB1Gscm0SF3HRw6K6MAVvx 8GkEhpQ8TMR2mhcAP1D7oHM0ZaCww/2iTf2ksYsHHHiraPYxpIqUJh9b11DVvZT7 Gy4MkxiQDj+uGpE//2o1C1T5mDcKt46e/Yv1dcCxfS2+anl+kSM/LrWJvffXVaiA == X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduledrvdeluddgfeejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepofgfggfkjghffffhvffutgesthdtredtreertdenucfhrhhomhepfdfuvhgv nhcurfgvthgvrhdfuceoshhvvghnsehsvhgvnhhpvghtvghrrdguvghvqeenucggtffrrg htthgvrhhnpefgieegieffuefhtedtjefgteejteefleefgfefgfdvvddtgffhffduhedv feekffenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpe hsvhgvnhesshhvvghnphgvthgvrhdruggvvh X-ME-Proxy: Received: by mailuser.nyi.internal (Postfix, from userid 501) id DF48F51C0060; Sun, 30 May 2021 07:09:01 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.5.0-alpha0-468-gdb53729b73-fm-20210517.001-gdb53729b Mime-Version: 1.0 Message-Id: <9ff6ec26-4b78-4684-9c23-16d5cbfef857@www.fastmail.com> In-Reply-To: References: <20210524182745.22923-1-sven@svenpeter.dev> Date: Sun, 30 May 2021 13:08:40 +0200 From: "Sven Peter" To: "Tony Lindgren" , "Rob Herring" Cc: devicetree@vger.kernel.org, linux-clk , linux-arm-kernel , "linux-kernel@vger.kernel.org" , "Hector Martin" , "Michael Turquette" , "Stephen Boyd" , "Mark Kettenis" , "Arnd Bergmann" Subject: Re: [PATCH 0/3] Apple M1 clock gate driver Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Wed, May 26, 2021, at 09:18, Tony Lindgren wrote: > Hi, > > * Rob Herring [210525 18:09]: > > I would do a single node per mmio region with the register offset (or > > offset / 4) being the clock id. This can still support new SoCs easily > > if you have a fallback compatible. If you want/need to get all the > > clocks, just walk the DT 'clocks' properties and extract all the IDs. > > I mostly agree.. Except I'd also leave out the artificial clock ID and > just use real register offsets from the clock controller base instead. Sure, I'll do that. > > So a single clock controller node for each MMIO range, then set > #clock=cells = <1>. Then the binding follows what we have for the > interrupts-extended binding for example. > > If the clock controller optionally needs some data in the dts, > that can be added to the clock controller node. Or it can be driver > internal built-in data. If the data for dts can be described in a > generic way, even better :) Now the big question is *how* to describe this additional data in the dts. Essentially I need to specify that e.g. to enable clock 0x270 I first need to enable the (internal) clocks 0x1c0 and then 0x220. Are you aware of any generic way to describe this? I'm not even sure how a sane non-generic way would look like when I just have a single clock controller node. Best, Sven From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF3DCC47091 for ; Sun, 30 May 2021 11:10:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8ADF5610A8 for ; Sun, 30 May 2021 11:10:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8ADF5610A8 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=svenpeter.dev Authentication-Results: mail.kernel.org; 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Sun, 30 May 2021 07:09:01 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.5.0-alpha0-468-gdb53729b73-fm-20210517.001-gdb53729b Mime-Version: 1.0 Message-Id: <9ff6ec26-4b78-4684-9c23-16d5cbfef857@www.fastmail.com> In-Reply-To: References: <20210524182745.22923-1-sven@svenpeter.dev> Date: Sun, 30 May 2021 13:08:40 +0200 From: "Sven Peter" To: "Tony Lindgren" , "Rob Herring" Cc: devicetree@vger.kernel.org, linux-clk , linux-arm-kernel , "linux-kernel@vger.kernel.org" , "Hector Martin" , "Michael Turquette" , "Stephen Boyd" , "Mark Kettenis" , "Arnd Bergmann" Subject: Re: [PATCH 0/3] Apple M1 clock gate driver X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210530_040905_448843_0F0144D2 X-CRM114-Status: GOOD ( 17.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On Wed, May 26, 2021, at 09:18, Tony Lindgren wrote: > Hi, > > * Rob Herring [210525 18:09]: > > I would do a single node per mmio region with the register offset (or > > offset / 4) being the clock id. This can still support new SoCs easily > > if you have a fallback compatible. If you want/need to get all the > > clocks, just walk the DT 'clocks' properties and extract all the IDs. > > I mostly agree.. Except I'd also leave out the artificial clock ID and > just use real register offsets from the clock controller base instead. Sure, I'll do that. > > So a single clock controller node for each MMIO range, then set > #clock=cells = <1>. Then the binding follows what we have for the > interrupts-extended binding for example. > > If the clock controller optionally needs some data in the dts, > that can be added to the clock controller node. Or it can be driver > internal built-in data. If the data for dts can be described in a > generic way, even better :) Now the big question is *how* to describe this additional data in the dts. Essentially I need to specify that e.g. to enable clock 0x270 I first need to enable the (internal) clocks 0x1c0 and then 0x220. Are you aware of any generic way to describe this? I'm not even sure how a sane non-generic way would look like when I just have a single clock controller node. Best, Sven _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel