From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 05 Oct 2019 06:33:14 -0000 Received: from mga05.intel.com ([192.55.52.43]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iGdcv-0007Mn-Eh for speck@linutronix.de; Sat, 05 Oct 2019 08:33:13 +0200 Date: Fri, 4 Oct 2019 23:27:31 -0700 From: Pawan Gupta Subject: [MODERATED] [PATCH v5 02/11] TAAv5 2 Message-ID: =?utf-8?q?=3Ce6fbe7bb3310c7bd6603af8dc80409425d7ef759=2E157025?= =?utf-8?q?5065=2Egit=2Epawan=2Ekumar=2Egupta=40linux=2Eintel=2Ecom=3E?= References: MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: Move IA32_ARCH_CAPABILITIES MSR read to a helper function. If the CPU doesn't support this MSR return 0. Use this function in following commits to read IA32_ARCH_CAPABILITIES MSR. Signed-off-by: Pawan Gupta Reviewed-by: Mark Gross Reviewed-by: Tony Luck Tested-by: Neelima Krishnan --- arch/x86/kernel/cpu/common.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index f125bf7ecb6f..af9e357b2ca9 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1091,19 +1091,27 @@ static bool __init cpu_matches(unsigned long which) return m && !!(m->driver_data & which); } -static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) +u64 read_ia32_arch_cap(void) { u64 ia32_cap = 0; + /* Leave the MSR set to all 0's when not supported */ + if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) + rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); + + return ia32_cap; +} + +static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) +{ + u64 ia32_cap = read_ia32_arch_cap(); + if (cpu_matches(NO_SPECULATION)) return; setup_force_cpu_bug(X86_BUG_SPECTRE_V1); setup_force_cpu_bug(X86_BUG_SPECTRE_V2); - if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) - rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); - if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) && !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); -- 2.20.1