From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Eelco Chaudron" Subject: Re: [dpdk-stable] [PATCH v4 2/5] bus/pci: use IOVAs check when setting IOVA mode Date: Wed, 11 Jul 2018 12:18:25 +0200 Message-ID: References: <1531243552-7795-1-git-send-email-alejandro.lucero@netronome.com> <1531243552-7795-3-git-send-email-alejandro.lucero@netronome.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Cc: dev@dpdk.org, stable@dpdk.org, anatoly.burakov@intel.com To: "Alejandro Lucero" Return-path: In-Reply-To: <1531243552-7795-3-git-send-email-alejandro.lucero@netronome.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 10 Jul 2018, at 19:25, Alejandro Lucero wrote: > Although VT-d emulation currently only supports 39 bits, it could > be iovas being within that supported range. This patch allows > IOVA mode in such a case. > > Indeed, memory initialization code can be modified for using lower > virtual addresses than those used by the kernel for 64 bits processes > by default, and therefore memsegs iovas can use 39 bits or less for > most system. And this is likely 100% true for VMs. > > Applicable to v17.11.3 only. > > Signed-off-by: Alejandro Lucero > --- > drivers/bus/pci/linux/pci.c | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > > diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c > index 74deef3..792c819 100644 > --- a/drivers/bus/pci/linux/pci.c > +++ b/drivers/bus/pci/linux/pci.c > @@ -43,6 +43,7 @@ > #include > #include > #include > +#include > > #include "eal_private.h" > #include "eal_filesystem.h" > @@ -613,10 +614,12 @@ > fclose(fp); > > mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + > 1; > - if (mgaw < X86_VA_WIDTH) > + > + if (!rte_eal_check_dma_mask(mgaw)) > + return true; > + else > return false; > > - return true; > } > #elif defined(RTE_ARCH_PPC_64) > static bool > @@ -640,13 +643,17 @@ > { > struct rte_pci_device *dev = NULL; > struct rte_pci_driver *drv = NULL; > + int iommu_dma_mask_check_done = 0; > > FOREACH_DRIVER_ON_PCIBUS(drv) { > FOREACH_DEVICE_ON_PCIBUS(dev) { > if (!rte_pci_match(drv, dev)) > continue; > - if (!pci_one_device_iommu_support_va(dev)) > - return false; > + if (!iommu_dma_mask_check_done) { > + if (pci_one_device_iommu_support_va(dev) < 0) > + return false; > + iommu_dma_mask_check_done = 1; As I do not know enough on what IOMMU hardware can coexist, I leave this patch for others to review. Here is the previous question/answer: >>> Not sure why this change? Why do we only need to check one device on >>> all the buses? >> Because there is just one emulated IOMMU hardware. The limitation in >> this case is not in a specific PCI device. And I do not think it is >> possible to have two different (emulated or not) IOMMU hardware. Yes, >> you can have more than one controller but being same IOMMU type. If the above is confirmed, you can consider this patch ack’ed. > + } > } > } > return true; > -- > 1.9.1