From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935056AbcATDmH (ORCPT ); Tue, 19 Jan 2016 22:42:07 -0500 Received: from mailout.micron.com ([137.201.242.129]:36567 "EHLO mailout.micron.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933912AbcATDmB (ORCPT ); Tue, 19 Jan 2016 22:42:01 -0500 From: =?utf-8?B?QmVhbiBIdW8g6ZyN5paM5paMIChiZWFuaHVvKQ==?= To: Brian Norris CC: Cyrille Pitchen , "linux-mtd@lists.infradead.org" , "nicolas.ferre@atmel.com" , "marex@denx.de" , "vigneshr@ti.com" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "robh+dt@kernel.org" , "pawel.moll@arm.com" , "mark.rutland@arm.com" , "ijc+devicetree@hellion.org.uk" , "galak@codeaurora.org" Subject: RE: [PATCH linux-next 0/5] mtd: spi-nor: add driver for Atmel QSPI controller Thread-Topic: [PATCH linux-next 0/5] mtd: spi-nor: add driver for Atmel QSPI controller Thread-Index: AQHRMSZWykU45oYb1kuwJJaYJWEbHJ7Ae7/ggA7yBoCANIumEA== Date: Wed, 20 Jan 2016 03:41:04 +0000 Message-ID: References: <20151207193441.GO120110@google.com> <20151218002901.GE10460@google.com> In-Reply-To: <20151218002901.GE10460@google.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [137.201.21.209] x-mt-checkinternalsenderrule: True Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u0K3gxxb021209 Hi, Brian Sorry for response this too later. Please see my comment below: > Hi Bean, > > On Tue, Dec 08, 2015 at 06:21:00AM +0000, Bean Huo 霍斌斌 wrote: > > > -----Original Message----- > > > From: Brian Norris [mailto:computersforpeace@gmail.com] > > > > > > I'll admit I'm a little fuzzy on the differences between dual and > > > quad modes on various flash manufacturers. Can you help clear it up for > me? > > > > For Micron SPI NOR spi quad mode, means that Qaud I/O prototocol, it > > follows I/O Bus width is command-address-Data 4-4-4, at this time, > > DQ0,DQ1,DQ2,DQ3 are all used to transfer address/command/data. For > > this maybe not the same between different flash manufactures. For > > example, for Spansion Qspi NOR, its all instructions are transferred > > from host to memory as a single bit serial sequence on the DQ0 signal, even > under Quad mode. Dual mode the same as Qaud mode scenario. > > > > for SPI NOR 1-1-4, means command and address are transferred on the > > DQ0, but for data, being transferred on DQ0,DQ1,DQ2,DQ3.For this, it > > is the same between different flash manufacturers. Of course, at this > > moment, SPI NOR should work under extended I/O mode. > > OK, so to make these statements *much* shorter: > > * Micron "Quad Mode" means putting the flash in a 4/4/4 mode Yes. > * Spansion (and all others?) are using 1/1/4 modes Per my experience, Spansion are using 1/4/4 in quad mode, But Macronix is the same with Micron, also putting flash into 4/4/4 mode. > > Correct? > > > > I think some of the comments on patch 2 help too, but I'll just > > > comment here for now. > > > It looks like the current driver has problems regarding the non > > > 1-x-y modes (e.g., 4-4-4), right? But I see that spi-nor.c never > > > tries to send a 4_4_4 command; it only sets read_opcode to > > > SPINOR_OP_READ_1_1_{1,2,4}. So is this an oversight in patches like > Bean's patch? > > > > For SPINOR_OP_READ_1_1_{1,2,4} commands, Spi NOR actually works > under > > Extended I/O mode, not Quad mode. They just push Spi NOR output data > > by Quad mode, Command and address still following extended I/O mode. > > The naming is confusing enough here... so in your words, "extended" > means 1/1/{1,2,4} (i.e., command, and maybe address, use 1 line, but data > goes on 4)? And "quad" means 4/4/4? Extended mode : means it is the standard spi interface, command and Address use 1 line, and how many lines being used by data, it depends on Specified command, for example, fast read command, uses 4 lines. > > For 4-4-4 I/O protocol, SPI NOR should change to Quad mode(just as my > > patch), of course, SPI controller should support this. for Micron Qspi > > NOR, under quad mode, all commands/address/data are transferred on > > DQ0,DQ1,DQ2,DQ3 signals. No matter what kind of command. > > OK, so I think your patch is broken: > > > > commit 548cd3ab54da ("mtd: spi-nor: Add quad I/O support for > Micron > > > SPI NOR") > > How did you test this? Specifically, this can't possibly have worked with a > regular drivers/spi/ controllers, since: > > (a) you're enabling 4/4/4 (i.e., "Quad mode") on the flash but > (b) m25p80_read() only sets .rx_bits for the data; i.e., it's using > 1/1/4 (i.e., "Extended mode") > I'm tempted to essentially revert that, as it looks essentially untested. It > would be nice to have a cleaner baseline before trying to extend it with > Cyrille's work. Definitely ,for my patch , it is tested and verified OK. But I add a hoot function in m25p80.c To put spi controller into quad mode as long as spi nor switch into quad mode. For this hook function patch is an independent patch with my patch, I did not submit. Because if we don't use m25p80.c driver, use new spi structure(such as : driver/mtd/spi-nor/fsl_quadspi.c) spi controller driver, This hook function patch is not necessary. > Cyrille, what do you think? Is my analysis at all correct here? (Sorry if this is > addressed elsewhere; there's a lot of text in this conversation, but I'm getting > hung up very early.) And if so, does it hurt to just drop Micron "Quad mode" > (4/4/4)? > (AIUI, this won't exactly be a panacea, since you mention bootloaders that > start us off in quad mode, so we can't use single I/O 0x9f READ > ID.) > > > > Why would we even need to enable quad modes like that, if we're not > > > going to send the 4-4-4 opcodes? > > I think, in order to high speed SPI NOR, after enable quad mode, > > SPINOR_OP_READ_1_1_{1,2,4} commands don't need any more, normal > read > > command (0x03) Can implement as them. > > OK. That's odd, but I guess it doesn't matter much. It just makes it a little less > obvious what's going on. > > > > My next question (if my understanding is roughly correct) is, do we > > > need the > > > 4-4-4 modes, and what risks come with them? I understand we can > > > shorten the command and address phases, but does that alone yield > > > much performance benefit? And I think the risk is that a given > > > system might not be prepared for the flash to be in a 4-4-4 mode, if > > > the boot code tries to use 1-x-y commands. > > > > As far as my current experience and knowledge, this still need to be > > enabled, especially for fast boot, and some IOT devices to store info into > SPI NOR. > > Do you have any data to about the speed? And you haven't addressed the > risks. There are definitely risks. Cyrille looks like he's trying to address the > risks (e.g., use volatile modes whenever possible), but it doesn't seem that > you are. > > For this patches, my current concern is that host side how to get > > different I/O protocol changes, and distinguish between different flash > manufacturers I/O mode. > > Brian From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?utf-8?B?QmVhbiBIdW8g6ZyN5paM5paMIChiZWFuaHVvKQ==?= Subject: RE: [PATCH linux-next 0/5] mtd: spi-nor: add driver for Atmel QSPI controller Date: Wed, 20 Jan 2016 03:41:04 +0000 Message-ID: References: <20151207193441.GO120110@google.com> <20151218002901.GE10460@google.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20151218002901.GE10460@google.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Brian Norris Cc: "marex@denx.de" , "devicetree@vger.kernel.org" , "vigneshr@ti.com" , "pawel.moll@arm.com" , "ijc+devicetree@hellion.org.uk" , "mark.rutland@arm.com" , "nicolas.ferre@atmel.com" , "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "linux-mtd@lists.infradead.org" , "galak@codeaurora.org" , Cyrille Pitchen , "linux-arm-kernel@lists.infradead.org" List-Id: devicetree@vger.kernel.org SGksIEJyaWFuDQpTb3JyeSBmb3IgcmVzcG9uc2UgdGhpcyB0b28gbGF0ZXIuIFBsZWFzZSBzZWUg bXkgY29tbWVudCBiZWxvdzoNCiANCj4gSGkgQmVhbiwNCj4gDQo+IE9uIFR1ZSwgRGVjIDA4LCAy MDE1IGF0IDA2OjIxOjAwQU0gKzAwMDAsIEJlYW4gSHVvIOmcjeaWjOaWjCB3cm90ZToNCj4gPiA+ IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+ID4gPiBGcm9tOiBCcmlhbiBOb3JyaXMgW21h aWx0bzpjb21wdXRlcnNmb3JwZWFjZUBnbWFpbC5jb21dDQo+ID4gPg0KPiA+ID4gSSdsbCBhZG1p dCBJJ20gYSBsaXR0bGUgZnV6enkgb24gdGhlIGRpZmZlcmVuY2VzIGJldHdlZW4gZHVhbCBhbmQN Cj4gPiA+IHF1YWQgbW9kZXMgb24gdmFyaW91cyBmbGFzaCBtYW51ZmFjdHVyZXJzLiBDYW4geW91 IGhlbHAgY2xlYXIgaXQgdXAgZm9yDQo+IG1lPw0KPiA+DQo+ID4gRm9yIE1pY3JvbiBTUEkgTk9S IHNwaSBxdWFkIG1vZGUsIG1lYW5zIHRoYXQgUWF1ZCBJL08gcHJvdG90b2NvbCwgaXQNCj4gPiBm b2xsb3dzIEkvTyBCdXMgd2lkdGggaXMgY29tbWFuZC1hZGRyZXNzLURhdGEgNC00LTQsIGF0IHRo aXMgdGltZSwNCj4gPiBEUTAsRFExLERRMixEUTMgYXJlIGFsbCB1c2VkIHRvIHRyYW5zZmVyIGFk ZHJlc3MvY29tbWFuZC9kYXRhLiBGb3INCj4gPiB0aGlzIG1heWJlIG5vdCB0aGUgc2FtZSBiZXR3 ZWVuIGRpZmZlcmVudCBmbGFzaCBtYW51ZmFjdHVyZXMuIEZvcg0KPiA+IGV4YW1wbGUsIGZvciBT cGFuc2lvbiBRc3BpIE5PUiwgaXRzIGFsbCBpbnN0cnVjdGlvbnMgYXJlIHRyYW5zZmVycmVkDQo+ ID4gZnJvbSBob3N0IHRvIG1lbW9yeSBhcyBhIHNpbmdsZSBiaXQgc2VyaWFsIHNlcXVlbmNlIG9u IHRoZSBEUTAgc2lnbmFsLCBldmVuDQo+IHVuZGVyIFF1YWQgbW9kZS4gIER1YWwgbW9kZSB0aGUg c2FtZSBhcyBRYXVkIG1vZGUgc2NlbmFyaW8uDQo+ID4NCj4gPiBmb3IgU1BJIE5PUiAxLTEtNCwg bWVhbnMgY29tbWFuZCBhbmQgYWRkcmVzcyBhcmUgdHJhbnNmZXJyZWQgb24gdGhlDQo+ID4gRFEw LCBidXQgZm9yIGRhdGEsIGJlaW5nIHRyYW5zZmVycmVkIG9uIERRMCxEUTEsRFEyLERRMy5Gb3Ig dGhpcywgaXQNCj4gPiBpcyB0aGUgc2FtZSBiZXR3ZWVuIGRpZmZlcmVudCBmbGFzaCBtYW51ZmFj dHVyZXJzLiBPZiBjb3Vyc2UsIGF0IHRoaXMNCj4gPiBtb21lbnQsIFNQSSBOT1Igc2hvdWxkIHdv cmsgdW5kZXIgZXh0ZW5kZWQgSS9PIG1vZGUuDQo+IA0KPiBPSywgc28gdG8gbWFrZSB0aGVzZSBz dGF0ZW1lbnRzICptdWNoKiBzaG9ydGVyOg0KPiANCj4gICogTWljcm9uICJRdWFkIE1vZGUiIG1l YW5zIHB1dHRpbmcgdGhlIGZsYXNoIGluIGEgNC80LzQgbW9kZQ0KCVllcy4NCj4gICogU3BhbnNp b24gKGFuZCBhbGwgb3RoZXJzPykgYXJlIHVzaW5nIDEvMS80IG1vZGVzDQoJUGVyIG15IGV4cGVy aWVuY2UsIFNwYW5zaW9uIGFyZSB1c2luZyAxLzQvNCBpbiBxdWFkIG1vZGUsDQoJQnV0IE1hY3Jv bml4IGlzIHRoZSBzYW1lIHdpdGggTWljcm9uLCBhbHNvIHB1dHRpbmcgZmxhc2ggaW50byA0LzQv NCBtb2RlLg0KDQo+IA0KPiBDb3JyZWN0Pw0KPiANCj4gPiA+IEkgdGhpbmsgc29tZSBvZiB0aGUg Y29tbWVudHMgb24gcGF0Y2ggMiBoZWxwIHRvbywgYnV0IEknbGwganVzdA0KPiA+ID4gY29tbWVu dCBoZXJlIGZvciBub3cuDQo+ID4gPiBJdCBsb29rcyBsaWtlIHRoZSBjdXJyZW50IGRyaXZlciBo YXMgcHJvYmxlbXMgcmVnYXJkaW5nIHRoZSBub24NCj4gPiA+IDEteC15IG1vZGVzIChlLmcuLCA0 LTQtNCksIHJpZ2h0PyBCdXQgSSBzZWUgdGhhdCBzcGktbm9yLmMgbmV2ZXINCj4gPiA+IHRyaWVz IHRvIHNlbmQgYSA0XzRfNCBjb21tYW5kOyBpdCBvbmx5IHNldHMgcmVhZF9vcGNvZGUgdG8NCj4g PiA+IFNQSU5PUl9PUF9SRUFEXzFfMV97MSwyLDR9LiBTbyBpcyB0aGlzIGFuIG92ZXJzaWdodCBp biBwYXRjaGVzIGxpa2UNCj4gQmVhbidzIHBhdGNoPw0KPiA+DQo+ID4gRm9yIFNQSU5PUl9PUF9S RUFEXzFfMV97MSwyLDR9IGNvbW1hbmRzLCBTcGkgTk9SIGFjdHVhbGx5IHdvcmtzDQo+IHVuZGVy DQo+ID4gRXh0ZW5kZWQgSS9PIG1vZGUsIG5vdCBRdWFkIG1vZGUuIFRoZXkganVzdCBwdXNoIFNw aSBOT1Igb3V0cHV0IGRhdGENCj4gPiBieSBRdWFkIG1vZGUsIENvbW1hbmQgYW5kIGFkZHJlc3Mg c3RpbGwgZm9sbG93aW5nIGV4dGVuZGVkIEkvTyBtb2RlLg0KPiANCj4gVGhlIG5hbWluZyBpcyBj b25mdXNpbmcgZW5vdWdoIGhlcmUuLi4gc28gaW4geW91ciB3b3JkcywgImV4dGVuZGVkIg0KPiBt ZWFucyAxLzEvezEsMiw0fSAoaS5lLiwgY29tbWFuZCwgYW5kIG1heWJlIGFkZHJlc3MsIHVzZSAx IGxpbmUsIGJ1dCBkYXRhDQo+IGdvZXMgb24gNCk/IEFuZCAicXVhZCIgbWVhbnMgNC80LzQ/DQoN CkV4dGVuZGVkIG1vZGUgOg0KbWVhbnMgaXQgaXMgdGhlIHN0YW5kYXJkIHNwaSBpbnRlcmZhY2Us IGNvbW1hbmQgYW5kIA0KQWRkcmVzcyB1c2UgMSBsaW5lLCBhbmQgaG93IG1hbnkgbGluZXMgYmVp bmcgdXNlZCBieSBkYXRhLCBpdCBkZXBlbmRzIG9uDQpTcGVjaWZpZWQgY29tbWFuZCwgZm9yIGV4 YW1wbGUsIGZhc3QgcmVhZCBjb21tYW5kLCB1c2VzIDQgbGluZXMuDQoNCg0KPiA+IEZvciA0LTQt NCBJL08gcHJvdG9jb2wsIFNQSSBOT1Igc2hvdWxkIGNoYW5nZSB0byBRdWFkIG1vZGUoanVzdCBh cyBteQ0KPiA+IHBhdGNoKSwgb2YgY291cnNlLCBTUEkgY29udHJvbGxlciBzaG91bGQgc3VwcG9y dCB0aGlzLiBmb3IgTWljcm9uIFFzcGkNCj4gPiBOT1IsIHVuZGVyIHF1YWQgbW9kZSwgYWxsIGNv bW1hbmRzL2FkZHJlc3MvZGF0YSBhcmUgdHJhbnNmZXJyZWQgb24NCj4gPiBEUTAsRFExLERRMixE UTMgc2lnbmFscy4gTm8gbWF0dGVyIHdoYXQga2luZCBvZiBjb21tYW5kLg0KPiANCj4gT0ssIHNv IEkgdGhpbmsgeW91ciBwYXRjaCBpcyBicm9rZW46DQo+IA0KPiA+ID4gICAgIGNvbW1pdCA1NDhj ZDNhYjU0ZGEgKCJtdGQ6IHNwaS1ub3I6IEFkZCBxdWFkIEkvTyBzdXBwb3J0IGZvcg0KPiBNaWNy b24NCj4gPiA+ICAgICBTUEkgTk9SIikNCj4gDQo+IEhvdyBkaWQgeW91IHRlc3QgdGhpcz8gU3Bl Y2lmaWNhbGx5LCB0aGlzIGNhbid0IHBvc3NpYmx5IGhhdmUgd29ya2VkIHdpdGggYQ0KPiByZWd1 bGFyIGRyaXZlcnMvc3BpLyBjb250cm9sbGVycywgc2luY2U6DQo+IA0KPiAgKGEpIHlvdSdyZSBl bmFibGluZyA0LzQvNCAoaS5lLiwgIlF1YWQgbW9kZSIpIG9uIHRoZSBmbGFzaCBidXQNCj4gIChi KSBtMjVwODBfcmVhZCgpIG9ubHkgc2V0cyAucnhfYml0cyBmb3IgdGhlIGRhdGE7IGkuZS4sIGl0 J3MgdXNpbmcNCj4gIDEvMS80IChpLmUuLCAiRXh0ZW5kZWQgbW9kZSIpDQoNCj4gSSdtIHRlbXB0 ZWQgdG8gZXNzZW50aWFsbHkgcmV2ZXJ0IHRoYXQsIGFzIGl0IGxvb2tzIGVzc2VudGlhbGx5IHVu dGVzdGVkLiBJdA0KPiB3b3VsZCBiZSBuaWNlIHRvIGhhdmUgYSBjbGVhbmVyIGJhc2VsaW5lIGJl Zm9yZSB0cnlpbmcgdG8gZXh0ZW5kIGl0IHdpdGgNCj4gQ3lyaWxsZSdzIHdvcmsuDQoNCkRlZmlu aXRlbHkgLGZvciBteSBwYXRjaCAsIGl0IGlzIHRlc3RlZCBhbmQgdmVyaWZpZWQgT0suIEJ1dCBJ IGFkZCBhIGhvb3QgZnVuY3Rpb24gaW4gbTI1cDgwLmMNClRvIHB1dCBzcGkgY29udHJvbGxlciBp bnRvIHF1YWQgbW9kZSBhcyBsb25nIGFzIHNwaSBub3Igc3dpdGNoIGludG8gcXVhZCBtb2RlLg0K Rm9yIHRoaXMgaG9vayBmdW5jdGlvbiBwYXRjaCBpcyBhbiBpbmRlcGVuZGVudCBwYXRjaCB3aXRo IG15IHBhdGNoLCBJIGRpZCBub3Qgc3VibWl0Lg0KQmVjYXVzZSBpZiB3ZSBkb24ndCB1c2UgbTI1 cDgwLmMgZHJpdmVyLCB1c2UgbmV3IHNwaSBzdHJ1Y3R1cmUoc3VjaCBhcyA6IGRyaXZlci9tdGQv c3BpLW5vci9mc2xfcXVhZHNwaS5jKQ0Kc3BpIGNvbnRyb2xsZXIgZHJpdmVyLCBUaGlzIGhvb2sg ZnVuY3Rpb24gcGF0Y2ggaXMgbm90IG5lY2Vzc2FyeS4NCg0KPiBDeXJpbGxlLCB3aGF0IGRvIHlv dSB0aGluaz8gSXMgbXkgYW5hbHlzaXMgYXQgYWxsIGNvcnJlY3QgaGVyZT8gKFNvcnJ5IGlmIHRo aXMgaXMNCj4gYWRkcmVzc2VkIGVsc2V3aGVyZTsgdGhlcmUncyBhIGxvdCBvZiB0ZXh0IGluIHRo aXMgY29udmVyc2F0aW9uLCBidXQgSSdtIGdldHRpbmcNCj4gaHVuZyB1cCB2ZXJ5IGVhcmx5Likg QW5kIGlmIHNvLCBkb2VzIGl0IGh1cnQgdG8ganVzdCBkcm9wIE1pY3JvbiAiUXVhZCBtb2RlIg0K PiAoNC80LzQpPw0KPiAoQUlVSSwgdGhpcyB3b24ndCBleGFjdGx5IGJlIGEgcGFuYWNlYSwgc2lu Y2UgeW91IG1lbnRpb24gYm9vdGxvYWRlcnMgdGhhdA0KPiBzdGFydCB1cyBvZmYgaW4gcXVhZCBt b2RlLCBzbyB3ZSBjYW4ndCB1c2Ugc2luZ2xlIEkvTyAweDlmIFJFQUQNCj4gSUQuKQ0KPiANCj4g PiA+IFdoeSB3b3VsZCB3ZSBldmVuIG5lZWQgdG8gZW5hYmxlIHF1YWQgbW9kZXMgbGlrZSB0aGF0 LCBpZiB3ZSdyZSBub3QNCj4gPiA+IGdvaW5nIHRvIHNlbmQgdGhlIDQtNC00IG9wY29kZXM/DQo+ ID4gSSB0aGluaywgaW4gb3JkZXIgdG8gaGlnaCBzcGVlZCBTUEkgTk9SLCBhZnRlciBlbmFibGUg cXVhZCBtb2RlLA0KPiA+IFNQSU5PUl9PUF9SRUFEXzFfMV97MSwyLDR9IGNvbW1hbmRzIGRvbid0 IG5lZWQgYW55IG1vcmUsIG5vcm1hbA0KPiByZWFkDQo+ID4gY29tbWFuZCAoMHgwMykgQ2FuIGlt cGxlbWVudCBhcyB0aGVtLg0KPiANCj4gT0suIFRoYXQncyBvZGQsIGJ1dCBJIGd1ZXNzIGl0IGRv ZXNuJ3QgbWF0dGVyIG11Y2guIEl0IGp1c3QgbWFrZXMgaXQgYSBsaXR0bGUgbGVzcw0KPiBvYnZp b3VzIHdoYXQncyBnb2luZyBvbi4NCj4gDQo+ID4gPiBNeSBuZXh0IHF1ZXN0aW9uIChpZiBteSB1 bmRlcnN0YW5kaW5nIGlzIHJvdWdobHkgY29ycmVjdCkgaXMsIGRvIHdlDQo+ID4gPiBuZWVkIHRo ZQ0KPiA+ID4gNC00LTQgbW9kZXMsIGFuZCB3aGF0IHJpc2tzIGNvbWUgd2l0aCB0aGVtPyBJIHVu ZGVyc3RhbmQgd2UgY2FuDQo+ID4gPiBzaG9ydGVuIHRoZSBjb21tYW5kIGFuZCBhZGRyZXNzIHBo YXNlcywgYnV0IGRvZXMgdGhhdCBhbG9uZSB5aWVsZA0KPiA+ID4gbXVjaCBwZXJmb3JtYW5jZSBi ZW5lZml0PyBBbmQgSSB0aGluayB0aGUgcmlzayBpcyB0aGF0IGEgZ2l2ZW4NCj4gPiA+IHN5c3Rl bSBtaWdodCBub3QgYmUgcHJlcGFyZWQgZm9yIHRoZSBmbGFzaCB0byBiZSBpbiBhIDQtNC00IG1v ZGUsIGlmDQo+ID4gPiB0aGUgYm9vdCBjb2RlIHRyaWVzIHRvIHVzZSAxLXgteSBjb21tYW5kcy4N Cj4gPg0KPiA+IEFzIGZhciBhcyBteSBjdXJyZW50IGV4cGVyaWVuY2UgYW5kIGtub3dsZWRnZSwg dGhpcyBzdGlsbCBuZWVkIHRvIGJlDQo+ID4gZW5hYmxlZCwgZXNwZWNpYWxseSBmb3IgZmFzdCBi b290LCBhbmQgc29tZSBJT1QgZGV2aWNlcyB0byBzdG9yZSBpbmZvIGludG8NCj4gU1BJIE5PUi4N Cj4gDQo+IERvIHlvdSBoYXZlIGFueSBkYXRhIHRvIGFib3V0IHRoZSBzcGVlZD8gQW5kIHlvdSBo YXZlbid0IGFkZHJlc3NlZCB0aGUNCj4gcmlza3MuIFRoZXJlIGFyZSBkZWZpbml0ZWx5IHJpc2tz LiBDeXJpbGxlIGxvb2tzIGxpa2UgaGUncyB0cnlpbmcgdG8gYWRkcmVzcyB0aGUNCj4gcmlza3Mg KGUuZy4sIHVzZSB2b2xhdGlsZSBtb2RlcyB3aGVuZXZlciBwb3NzaWJsZSksIGJ1dCBpdCBkb2Vz bid0IHNlZW0gdGhhdA0KPiB5b3UgYXJlLg0KPiA+IEZvciB0aGlzIHBhdGNoZXMsIG15IGN1cnJl bnQgY29uY2VybiBpcyB0aGF0IGhvc3Qgc2lkZSBob3cgdG8gZ2V0DQo+ID4gZGlmZmVyZW50IEkv TyBwcm90b2NvbCBjaGFuZ2VzLCBhbmQgZGlzdGluZ3Vpc2ggYmV0d2VlbiBkaWZmZXJlbnQgZmxh c2gNCj4gbWFudWZhY3R1cmVycyBJL08gbW9kZS4NCj4gDQo+IEJyaWFuDQpfX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxp bmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3Rz LmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?utf-8?B?QmVhbiBIdW8g6ZyN5paM5paMIChiZWFuaHVvKQ==?= To: Brian Norris CC: Cyrille Pitchen , "linux-mtd@lists.infradead.org" , "nicolas.ferre@atmel.com" , "marex@denx.de" , "vigneshr@ti.com" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "robh+dt@kernel.org" , "pawel.moll@arm.com" , "mark.rutland@arm.com" , "ijc+devicetree@hellion.org.uk" , "galak@codeaurora.org" Subject: RE: [PATCH linux-next 0/5] mtd: spi-nor: add driver for Atmel QSPI controller Date: Wed, 20 Jan 2016 03:41:04 +0000 Message-ID: References: <20151207193441.GO120110@google.com> <20151218002901.GE10460@google.com> In-Reply-To: <20151218002901.GE10460@google.com> Content-Language: en-US Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , SGksIEJyaWFuDQpTb3JyeSBmb3IgcmVzcG9uc2UgdGhpcyB0b28gbGF0ZXIuIFBsZWFzZSBzZWUg bXkgY29tbWVudCBiZWxvdzoNCiANCj4gSGkgQmVhbiwNCj4gDQo+IE9uIFR1ZSwgRGVjIDA4LCAy MDE1IGF0IDA2OjIxOjAwQU0gKzAwMDAsIEJlYW4gSHVvIOmcjeaWjOaWjCB3cm90ZToNCj4gPiA+ IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+ID4gPiBGcm9tOiBCcmlhbiBOb3JyaXMgW21h aWx0bzpjb21wdXRlcnNmb3JwZWFjZUBnbWFpbC5jb21dDQo+ID4gPg0KPiA+ID4gSSdsbCBhZG1p dCBJJ20gYSBsaXR0bGUgZnV6enkgb24gdGhlIGRpZmZlcmVuY2VzIGJldHdlZW4gZHVhbCBhbmQN Cj4gPiA+IHF1YWQgbW9kZXMgb24gdmFyaW91cyBmbGFzaCBtYW51ZmFjdHVyZXJzLiBDYW4geW91 IGhlbHAgY2xlYXIgaXQgdXAgZm9yDQo+IG1lPw0KPiA+DQo+ID4gRm9yIE1pY3JvbiBTUEkgTk9S IHNwaSBxdWFkIG1vZGUsIG1lYW5zIHRoYXQgUWF1ZCBJL08gcHJvdG90b2NvbCwgaXQNCj4gPiBm b2xsb3dzIEkvTyBCdXMgd2lkdGggaXMgY29tbWFuZC1hZGRyZXNzLURhdGEgNC00LTQsIGF0IHRo aXMgdGltZSwNCj4gPiBEUTAsRFExLERRMixEUTMgYXJlIGFsbCB1c2VkIHRvIHRyYW5zZmVyIGFk ZHJlc3MvY29tbWFuZC9kYXRhLiBGb3INCj4gPiB0aGlzIG1heWJlIG5vdCB0aGUgc2FtZSBiZXR3 ZWVuIGRpZmZlcmVudCBmbGFzaCBtYW51ZmFjdHVyZXMuIEZvcg0KPiA+IGV4YW1wbGUsIGZvciBT cGFuc2lvbiBRc3BpIE5PUiwgaXRzIGFsbCBpbnN0cnVjdGlvbnMgYXJlIHRyYW5zZmVycmVkDQo+ ID4gZnJvbSBob3N0IHRvIG1lbW9yeSBhcyBhIHNpbmdsZSBiaXQgc2VyaWFsIHNlcXVlbmNlIG9u IHRoZSBEUTAgc2lnbmFsLCBldmVuDQo+IHVuZGVyIFF1YWQgbW9kZS4gIER1YWwgbW9kZSB0aGUg c2FtZSBhcyBRYXVkIG1vZGUgc2NlbmFyaW8uDQo+ID4NCj4gPiBmb3IgU1BJIE5PUiAxLTEtNCwg bWVhbnMgY29tbWFuZCBhbmQgYWRkcmVzcyBhcmUgdHJhbnNmZXJyZWQgb24gdGhlDQo+ID4gRFEw LCBidXQgZm9yIGRhdGEsIGJlaW5nIHRyYW5zZmVycmVkIG9uIERRMCxEUTEsRFEyLERRMy5Gb3Ig dGhpcywgaXQNCj4gPiBpcyB0aGUgc2FtZSBiZXR3ZWVuIGRpZmZlcmVudCBmbGFzaCBtYW51ZmFj dHVyZXJzLiBPZiBjb3Vyc2UsIGF0IHRoaXMNCj4gPiBtb21lbnQsIFNQSSBOT1Igc2hvdWxkIHdv cmsgdW5kZXIgZXh0ZW5kZWQgSS9PIG1vZGUuDQo+IA0KPiBPSywgc28gdG8gbWFrZSB0aGVzZSBz dGF0ZW1lbnRzICptdWNoKiBzaG9ydGVyOg0KPiANCj4gICogTWljcm9uICJRdWFkIE1vZGUiIG1l YW5zIHB1dHRpbmcgdGhlIGZsYXNoIGluIGEgNC80LzQgbW9kZQ0KCVllcy4NCj4gICogU3BhbnNp b24gKGFuZCBhbGwgb3RoZXJzPykgYXJlIHVzaW5nIDEvMS80IG1vZGVzDQoJUGVyIG15IGV4cGVy aWVuY2UsIFNwYW5zaW9uIGFyZSB1c2luZyAxLzQvNCBpbiBxdWFkIG1vZGUsDQoJQnV0IE1hY3Jv bml4IGlzIHRoZSBzYW1lIHdpdGggTWljcm9uLCBhbHNvIHB1dHRpbmcgZmxhc2ggaW50byA0LzQv NCBtb2RlLg0KDQo+IA0KPiBDb3JyZWN0Pw0KPiANCj4gPiA+IEkgdGhpbmsgc29tZSBvZiB0aGUg Y29tbWVudHMgb24gcGF0Y2ggMiBoZWxwIHRvbywgYnV0IEknbGwganVzdA0KPiA+ID4gY29tbWVu dCBoZXJlIGZvciBub3cuDQo+ID4gPiBJdCBsb29rcyBsaWtlIHRoZSBjdXJyZW50IGRyaXZlciBo YXMgcHJvYmxlbXMgcmVnYXJkaW5nIHRoZSBub24NCj4gPiA+IDEteC15IG1vZGVzIChlLmcuLCA0 LTQtNCksIHJpZ2h0PyBCdXQgSSBzZWUgdGhhdCBzcGktbm9yLmMgbmV2ZXINCj4gPiA+IHRyaWVz IHRvIHNlbmQgYSA0XzRfNCBjb21tYW5kOyBpdCBvbmx5IHNldHMgcmVhZF9vcGNvZGUgdG8NCj4g PiA+IFNQSU5PUl9PUF9SRUFEXzFfMV97MSwyLDR9LiBTbyBpcyB0aGlzIGFuIG92ZXJzaWdodCBp biBwYXRjaGVzIGxpa2UNCj4gQmVhbidzIHBhdGNoPw0KPiA+DQo+ID4gRm9yIFNQSU5PUl9PUF9S RUFEXzFfMV97MSwyLDR9IGNvbW1hbmRzLCBTcGkgTk9SIGFjdHVhbGx5IHdvcmtzDQo+IHVuZGVy DQo+ID4gRXh0ZW5kZWQgSS9PIG1vZGUsIG5vdCBRdWFkIG1vZGUuIFRoZXkganVzdCBwdXNoIFNw aSBOT1Igb3V0cHV0IGRhdGENCj4gPiBieSBRdWFkIG1vZGUsIENvbW1hbmQgYW5kIGFkZHJlc3Mg c3RpbGwgZm9sbG93aW5nIGV4dGVuZGVkIEkvTyBtb2RlLg0KPiANCj4gVGhlIG5hbWluZyBpcyBj b25mdXNpbmcgZW5vdWdoIGhlcmUuLi4gc28gaW4geW91ciB3b3JkcywgImV4dGVuZGVkIg0KPiBt ZWFucyAxLzEvezEsMiw0fSAoaS5lLiwgY29tbWFuZCwgYW5kIG1heWJlIGFkZHJlc3MsIHVzZSAx IGxpbmUsIGJ1dCBkYXRhDQo+IGdvZXMgb24gNCk/IEFuZCAicXVhZCIgbWVhbnMgNC80LzQ/DQoN CkV4dGVuZGVkIG1vZGUgOg0KbWVhbnMgaXQgaXMgdGhlIHN0YW5kYXJkIHNwaSBpbnRlcmZhY2Us IGNvbW1hbmQgYW5kIA0KQWRkcmVzcyB1c2UgMSBsaW5lLCBhbmQgaG93IG1hbnkgbGluZXMgYmVp bmcgdXNlZCBieSBkYXRhLCBpdCBkZXBlbmRzIG9uDQpTcGVjaWZpZWQgY29tbWFuZCwgZm9yIGV4 YW1wbGUsIGZhc3QgcmVhZCBjb21tYW5kLCB1c2VzIDQgbGluZXMuDQoNCg0KPiA+IEZvciA0LTQt NCBJL08gcHJvdG9jb2wsIFNQSSBOT1Igc2hvdWxkIGNoYW5nZSB0byBRdWFkIG1vZGUoanVzdCBh cyBteQ0KPiA+IHBhdGNoKSwgb2YgY291cnNlLCBTUEkgY29udHJvbGxlciBzaG91bGQgc3VwcG9y dCB0aGlzLiBmb3IgTWljcm9uIFFzcGkNCj4gPiBOT1IsIHVuZGVyIHF1YWQgbW9kZSwgYWxsIGNv bW1hbmRzL2FkZHJlc3MvZGF0YSBhcmUgdHJhbnNmZXJyZWQgb24NCj4gPiBEUTAsRFExLERRMixE UTMgc2lnbmFscy4gTm8gbWF0dGVyIHdoYXQga2luZCBvZiBjb21tYW5kLg0KPiANCj4gT0ssIHNv IEkgdGhpbmsgeW91ciBwYXRjaCBpcyBicm9rZW46DQo+IA0KPiA+ID4gICAgIGNvbW1pdCA1NDhj ZDNhYjU0ZGEgKCJtdGQ6IHNwaS1ub3I6IEFkZCBxdWFkIEkvTyBzdXBwb3J0IGZvcg0KPiBNaWNy b24NCj4gPiA+ICAgICBTUEkgTk9SIikNCj4gDQo+IEhvdyBkaWQgeW91IHRlc3QgdGhpcz8gU3Bl Y2lmaWNhbGx5LCB0aGlzIGNhbid0IHBvc3NpYmx5IGhhdmUgd29ya2VkIHdpdGggYQ0KPiByZWd1 bGFyIGRyaXZlcnMvc3BpLyBjb250cm9sbGVycywgc2luY2U6DQo+IA0KPiAgKGEpIHlvdSdyZSBl bmFibGluZyA0LzQvNCAoaS5lLiwgIlF1YWQgbW9kZSIpIG9uIHRoZSBmbGFzaCBidXQNCj4gIChi KSBtMjVwODBfcmVhZCgpIG9ubHkgc2V0cyAucnhfYml0cyBmb3IgdGhlIGRhdGE7IGkuZS4sIGl0 J3MgdXNpbmcNCj4gIDEvMS80IChpLmUuLCAiRXh0ZW5kZWQgbW9kZSIpDQoNCj4gSSdtIHRlbXB0 ZWQgdG8gZXNzZW50aWFsbHkgcmV2ZXJ0IHRoYXQsIGFzIGl0IGxvb2tzIGVzc2VudGlhbGx5IHVu dGVzdGVkLiBJdA0KPiB3b3VsZCBiZSBuaWNlIHRvIGhhdmUgYSBjbGVhbmVyIGJhc2VsaW5lIGJl Zm9yZSB0cnlpbmcgdG8gZXh0ZW5kIGl0IHdpdGgNCj4gQ3lyaWxsZSdzIHdvcmsuDQoNCkRlZmlu aXRlbHkgLGZvciBteSBwYXRjaCAsIGl0IGlzIHRlc3RlZCBhbmQgdmVyaWZpZWQgT0suIEJ1dCBJ IGFkZCBhIGhvb3QgZnVuY3Rpb24gaW4gbTI1cDgwLmMNClRvIHB1dCBzcGkgY29udHJvbGxlciBp bnRvIHF1YWQgbW9kZSBhcyBsb25nIGFzIHNwaSBub3Igc3dpdGNoIGludG8gcXVhZCBtb2RlLg0K Rm9yIHRoaXMgaG9vayBmdW5jdGlvbiBwYXRjaCBpcyBhbiBpbmRlcGVuZGVudCBwYXRjaCB3aXRo IG15IHBhdGNoLCBJIGRpZCBub3Qgc3VibWl0Lg0KQmVjYXVzZSBpZiB3ZSBkb24ndCB1c2UgbTI1 cDgwLmMgZHJpdmVyLCB1c2UgbmV3IHNwaSBzdHJ1Y3R1cmUoc3VjaCBhcyA6IGRyaXZlci9tdGQv c3BpLW5vci9mc2xfcXVhZHNwaS5jKQ0Kc3BpIGNvbnRyb2xsZXIgZHJpdmVyLCBUaGlzIGhvb2sg ZnVuY3Rpb24gcGF0Y2ggaXMgbm90IG5lY2Vzc2FyeS4NCg0KPiBDeXJpbGxlLCB3aGF0IGRvIHlv dSB0aGluaz8gSXMgbXkgYW5hbHlzaXMgYXQgYWxsIGNvcnJlY3QgaGVyZT8gKFNvcnJ5IGlmIHRo aXMgaXMNCj4gYWRkcmVzc2VkIGVsc2V3aGVyZTsgdGhlcmUncyBhIGxvdCBvZiB0ZXh0IGluIHRo aXMgY29udmVyc2F0aW9uLCBidXQgSSdtIGdldHRpbmcNCj4gaHVuZyB1cCB2ZXJ5IGVhcmx5Likg QW5kIGlmIHNvLCBkb2VzIGl0IGh1cnQgdG8ganVzdCBkcm9wIE1pY3JvbiAiUXVhZCBtb2RlIg0K PiAoNC80LzQpPw0KPiAoQUlVSSwgdGhpcyB3b24ndCBleGFjdGx5IGJlIGEgcGFuYWNlYSwgc2lu Y2UgeW91IG1lbnRpb24gYm9vdGxvYWRlcnMgdGhhdA0KPiBzdGFydCB1cyBvZmYgaW4gcXVhZCBt b2RlLCBzbyB3ZSBjYW4ndCB1c2Ugc2luZ2xlIEkvTyAweDlmIFJFQUQNCj4gSUQuKQ0KPiANCj4g PiA+IFdoeSB3b3VsZCB3ZSBldmVuIG5lZWQgdG8gZW5hYmxlIHF1YWQgbW9kZXMgbGlrZSB0aGF0 LCBpZiB3ZSdyZSBub3QNCj4gPiA+IGdvaW5nIHRvIHNlbmQgdGhlIDQtNC00IG9wY29kZXM/DQo+ ID4gSSB0aGluaywgaW4gb3JkZXIgdG8gaGlnaCBzcGVlZCBTUEkgTk9SLCBhZnRlciBlbmFibGUg cXVhZCBtb2RlLA0KPiA+IFNQSU5PUl9PUF9SRUFEXzFfMV97MSwyLDR9IGNvbW1hbmRzIGRvbid0 IG5lZWQgYW55IG1vcmUsIG5vcm1hbA0KPiByZWFkDQo+ID4gY29tbWFuZCAoMHgwMykgQ2FuIGlt cGxlbWVudCBhcyB0aGVtLg0KPiANCj4gT0suIFRoYXQncyBvZGQsIGJ1dCBJIGd1ZXNzIGl0IGRv ZXNuJ3QgbWF0dGVyIG11Y2guIEl0IGp1c3QgbWFrZXMgaXQgYSBsaXR0bGUgbGVzcw0KPiBvYnZp b3VzIHdoYXQncyBnb2luZyBvbi4NCj4gDQo+ID4gPiBNeSBuZXh0IHF1ZXN0aW9uIChpZiBteSB1 bmRlcnN0YW5kaW5nIGlzIHJvdWdobHkgY29ycmVjdCkgaXMsIGRvIHdlDQo+ID4gPiBuZWVkIHRo ZQ0KPiA+ID4gNC00LTQgbW9kZXMsIGFuZCB3aGF0IHJpc2tzIGNvbWUgd2l0aCB0aGVtPyBJIHVu ZGVyc3RhbmQgd2UgY2FuDQo+ID4gPiBzaG9ydGVuIHRoZSBjb21tYW5kIGFuZCBhZGRyZXNzIHBo YXNlcywgYnV0IGRvZXMgdGhhdCBhbG9uZSB5aWVsZA0KPiA+ID4gbXVjaCBwZXJmb3JtYW5jZSBi ZW5lZml0PyBBbmQgSSB0aGluayB0aGUgcmlzayBpcyB0aGF0IGEgZ2l2ZW4NCj4gPiA+IHN5c3Rl bSBtaWdodCBub3QgYmUgcHJlcGFyZWQgZm9yIHRoZSBmbGFzaCB0byBiZSBpbiBhIDQtNC00IG1v ZGUsIGlmDQo+ID4gPiB0aGUgYm9vdCBjb2RlIHRyaWVzIHRvIHVzZSAxLXgteSBjb21tYW5kcy4N Cj4gPg0KPiA+IEFzIGZhciBhcyBteSBjdXJyZW50IGV4cGVyaWVuY2UgYW5kIGtub3dsZWRnZSwg dGhpcyBzdGlsbCBuZWVkIHRvIGJlDQo+ID4gZW5hYmxlZCwgZXNwZWNpYWxseSBmb3IgZmFzdCBi b290LCBhbmQgc29tZSBJT1QgZGV2aWNlcyB0byBzdG9yZSBpbmZvIGludG8NCj4gU1BJIE5PUi4N Cj4gDQo+IERvIHlvdSBoYXZlIGFueSBkYXRhIHRvIGFib3V0IHRoZSBzcGVlZD8gQW5kIHlvdSBo YXZlbid0IGFkZHJlc3NlZCB0aGUNCj4gcmlza3MuIFRoZXJlIGFyZSBkZWZpbml0ZWx5IHJpc2tz LiBDeXJpbGxlIGxvb2tzIGxpa2UgaGUncyB0cnlpbmcgdG8gYWRkcmVzcyB0aGUNCj4gcmlza3Mg KGUuZy4sIHVzZSB2b2xhdGlsZSBtb2RlcyB3aGVuZXZlciBwb3NzaWJsZSksIGJ1dCBpdCBkb2Vz bid0IHNlZW0gdGhhdA0KPiB5b3UgYXJlLg0KPiA+IEZvciB0aGlzIHBhdGNoZXMsIG15IGN1cnJl bnQgY29uY2VybiBpcyB0aGF0IGhvc3Qgc2lkZSBob3cgdG8gZ2V0DQo+ID4gZGlmZmVyZW50IEkv TyBwcm90b2NvbCBjaGFuZ2VzLCBhbmQgZGlzdGluZ3Vpc2ggYmV0d2VlbiBkaWZmZXJlbnQgZmxh c2gNCj4gbWFudWZhY3R1cmVycyBJL08gbW9kZS4NCj4gDQo+IEJyaWFuDQo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: beanhuo@micron.com (=?utf-8?B?QmVhbiBIdW8g6ZyN5paM5paMIChiZWFuaHVvKQ==?=) Date: Wed, 20 Jan 2016 03:41:04 +0000 Subject: [PATCH linux-next 0/5] mtd: spi-nor: add driver for Atmel QSPI controller In-Reply-To: <20151218002901.GE10460@google.com> References: <20151207193441.GO120110@google.com> <20151218002901.GE10460@google.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, Brian Sorry for response this too later. Please see my comment below: > Hi Bean, > > On Tue, Dec 08, 2015 at 06:21:00AM +0000, Bean Huo ??? wrote: > > > -----Original Message----- > > > From: Brian Norris [mailto:computersforpeace at gmail.com] > > > > > > I'll admit I'm a little fuzzy on the differences between dual and > > > quad modes on various flash manufacturers. Can you help clear it up for > me? > > > > For Micron SPI NOR spi quad mode, means that Qaud I/O prototocol, it > > follows I/O Bus width is command-address-Data 4-4-4, at this time, > > DQ0,DQ1,DQ2,DQ3 are all used to transfer address/command/data. For > > this maybe not the same between different flash manufactures. For > > example, for Spansion Qspi NOR, its all instructions are transferred > > from host to memory as a single bit serial sequence on the DQ0 signal, even > under Quad mode. Dual mode the same as Qaud mode scenario. > > > > for SPI NOR 1-1-4, means command and address are transferred on the > > DQ0, but for data, being transferred on DQ0,DQ1,DQ2,DQ3.For this, it > > is the same between different flash manufacturers. Of course, at this > > moment, SPI NOR should work under extended I/O mode. > > OK, so to make these statements *much* shorter: > > * Micron "Quad Mode" means putting the flash in a 4/4/4 mode Yes. > * Spansion (and all others?) are using 1/1/4 modes Per my experience, Spansion are using 1/4/4 in quad mode, But Macronix is the same with Micron, also putting flash into 4/4/4 mode. > > Correct? > > > > I think some of the comments on patch 2 help too, but I'll just > > > comment here for now. > > > It looks like the current driver has problems regarding the non > > > 1-x-y modes (e.g., 4-4-4), right? But I see that spi-nor.c never > > > tries to send a 4_4_4 command; it only sets read_opcode to > > > SPINOR_OP_READ_1_1_{1,2,4}. So is this an oversight in patches like > Bean's patch? > > > > For SPINOR_OP_READ_1_1_{1,2,4} commands, Spi NOR actually works > under > > Extended I/O mode, not Quad mode. They just push Spi NOR output data > > by Quad mode, Command and address still following extended I/O mode. > > The naming is confusing enough here... so in your words, "extended" > means 1/1/{1,2,4} (i.e., command, and maybe address, use 1 line, but data > goes on 4)? And "quad" means 4/4/4? Extended mode : means it is the standard spi interface, command and Address use 1 line, and how many lines being used by data, it depends on Specified command, for example, fast read command, uses 4 lines. > > For 4-4-4 I/O protocol, SPI NOR should change to Quad mode(just as my > > patch), of course, SPI controller should support this. for Micron Qspi > > NOR, under quad mode, all commands/address/data are transferred on > > DQ0,DQ1,DQ2,DQ3 signals. No matter what kind of command. > > OK, so I think your patch is broken: > > > > commit 548cd3ab54da ("mtd: spi-nor: Add quad I/O support for > Micron > > > SPI NOR") > > How did you test this? Specifically, this can't possibly have worked with a > regular drivers/spi/ controllers, since: > > (a) you're enabling 4/4/4 (i.e., "Quad mode") on the flash but > (b) m25p80_read() only sets .rx_bits for the data; i.e., it's using > 1/1/4 (i.e., "Extended mode") > I'm tempted to essentially revert that, as it looks essentially untested. It > would be nice to have a cleaner baseline before trying to extend it with > Cyrille's work. Definitely ,for my patch , it is tested and verified OK. But I add a hoot function in m25p80.c To put spi controller into quad mode as long as spi nor switch into quad mode. For this hook function patch is an independent patch with my patch, I did not submit. Because if we don't use m25p80.c driver, use new spi structure(such as : driver/mtd/spi-nor/fsl_quadspi.c) spi controller driver, This hook function patch is not necessary. > Cyrille, what do you think? Is my analysis at all correct here? (Sorry if this is > addressed elsewhere; there's a lot of text in this conversation, but I'm getting > hung up very early.) And if so, does it hurt to just drop Micron "Quad mode" > (4/4/4)? > (AIUI, this won't exactly be a panacea, since you mention bootloaders that > start us off in quad mode, so we can't use single I/O 0x9f READ > ID.) > > > > Why would we even need to enable quad modes like that, if we're not > > > going to send the 4-4-4 opcodes? > > I think, in order to high speed SPI NOR, after enable quad mode, > > SPINOR_OP_READ_1_1_{1,2,4} commands don't need any more, normal > read > > command (0x03) Can implement as them. > > OK. That's odd, but I guess it doesn't matter much. It just makes it a little less > obvious what's going on. > > > > My next question (if my understanding is roughly correct) is, do we > > > need the > > > 4-4-4 modes, and what risks come with them? I understand we can > > > shorten the command and address phases, but does that alone yield > > > much performance benefit? And I think the risk is that a given > > > system might not be prepared for the flash to be in a 4-4-4 mode, if > > > the boot code tries to use 1-x-y commands. > > > > As far as my current experience and knowledge, this still need to be > > enabled, especially for fast boot, and some IOT devices to store info into > SPI NOR. > > Do you have any data to about the speed? And you haven't addressed the > risks. There are definitely risks. Cyrille looks like he's trying to address the > risks (e.g., use volatile modes whenever possible), but it doesn't seem that > you are. > > For this patches, my current concern is that host side how to get > > different I/O protocol changes, and distinguish between different flash > manufacturers I/O mode. > > Brian