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Thu, 25 Jun 2020 21:13:54 +0000 (GMT) Received: from [9.160.117.167] (unknown [9.160.117.167]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTPS; Thu, 25 Jun 2020 21:13:54 +0000 (GMT) From: Lijun Pan Message-Id: Content-Type: multipart/alternative; boundary="Apple-Mail=_4328898D-CD54-42A7-A4EC-1771B91DC396" Mime-Version: 1.0 (Mac OS X Mail 13.4 \(3608.80.23.2.2\)) Subject: Re: [PATCH v3 4/8] target/ppc: add vmulld instruction Date: Thu, 25 Jun 2020 16:13:54 -0500 In-Reply-To: To: Richard Henderson References: <20200625170018.64265-1-ljp@linux.ibm.com> <20200625170018.64265-5-ljp@linux.ibm.com> X-Mailer: Apple Mail (2.3608.80.23.2.2) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.687 definitions=2020-06-25_16:2020-06-25, 2020-06-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 cotscore=-2147483648 adultscore=0 mlxscore=0 malwarescore=0 clxscore=1015 phishscore=0 suspectscore=0 spamscore=0 impostorscore=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2006250120 Received-SPF: none client-ip=148.163.156.1; envelope-from=ljp@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/25 17:13:06 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Lijun Pan , qemu-devel@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --Apple-Mail=_4328898D-CD54-42A7-A4EC-1771B91DC396 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 > On Jun 25, 2020, at 1:25 PM, Richard Henderson = wrote: >=20 > On 6/25/20 10:00 AM, Lijun Pan wrote: >> vmulld: Vector Multiply Low Doubleword. >>=20 >> Signed-off-by: Lijun Pan >> --- >> v3: use tcg_gen_gvec_mul() >>=20 >> target/ppc/translate/vmx-impl.inc.c | 1 + >> target/ppc/translate/vmx-ops.inc.c | 4 ++++ >=20 > This part looks fine. >=20 >> tcg/ppc/tcg-target.h | 2 ++ >> tcg/ppc/tcg-target.inc.c | 7 +++++-- >=20 > This part must be a separate patch. >=20 >=20 >> @@ -3149,6 +3150,7 @@ static void tcg_out_vec_op(TCGContext *s, = TCGOpcode opc, >> static const uint32_t >> add_op[4] =3D { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, >> sub_op[4] =3D { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, >> + mul_op[4] =3D { 0, 0, VMULUWM, VMULLD }, >> neg_op[4] =3D { 0, 0, VNEGW, VNEGD }, >> eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, >> ne_op[4] =3D { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, >> @@ -3199,8 +3201,9 @@ static void tcg_out_vec_op(TCGContext *s, = TCGOpcode opc, >> a1 =3D 0; >> break; >> case INDEX_op_mul_vec: >> - tcg_debug_assert(vece =3D=3D MO_32 && have_isa_2_07); >> - insn =3D VMULUWM; >> + tcg_debug_assert((vece =3D=3D MO_32 && have_isa_2_07) || >> + (vece =3D=3D MO_64 && have_isa_3_10)); >> + insn =3D mul_op[vece]; >=20 > I think it would be ok to just index mul_op here, since the real isa = check is > to be done elsewhere. Just keep "insn =3D mul_op[vece];" and remove" tcg_debug_assert((vece =3D=3D MO_32 && have_isa_2_07) = || (vece =3D=3D MO_64 && have_isa_3_10));=E2=80=9C? >=20 > Missing a change to tcg_can_emit_vec_op to do that isa check, and = allow > INDEX_op_mul_vec to be used for MO_64. something like below? " @@ -3016,6 +3016,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType = type, unsigned vece) return -1; case MO_32: return have_isa_2_07 ? 1 : -1; + case MO_64: + return have_isa_3_10 ? 1 : -1; } " >=20 > Missing a change to tcg_target_init to test for PPC_FEATURE2_ARCH_3_1. something like below? @@ -3712,6 +3712,11 @@ static void tcg_target_init(TCGContext *s) have_isa =3D tcg_isa_3_00; } #endif +#ifdef PPC_FEATURE2_ARCH_3_10 + if (hwcap2 & PPC_FEATURE2_ARCH_3_10) { + have_isa =3D tcg_isa_3_10; + } +#endif +++ b/include/elf.h @@ -554,6 +554,7 @@ typedef struct { #define PPC_FEATURE2_HTM_NOSC 0x01000000 #define PPC_FEATURE2_ARCH_3_00 0x00800000 #define PPC_FEATURE2_HAS_IEEE128 0x00400000 +#define PPC_FEATURE2_ARCH_3_10 0x00200000 Thanks, Lijun= --Apple-Mail=_4328898D-CD54-42A7-A4EC-1771B91DC396 Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=utf-8

On Jun 25, 2020, at 1:25 PM, Richard Henderson <richard.henderson@linaro.org> wrote:

On = 6/25/20 10:00 AM, Lijun Pan wrote:
vmulld: Vector Multiply Low Doubleword.

Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v3: use tcg_gen_gvec_mul()

target/ppc/translate/vmx-impl.inc.c | 1 +
= target/ppc/translate/vmx-ops.inc.c  | 4 ++++

This part looks fine.

= tcg/ppc/tcg-target.h =             &n= bsp;  | 2 ++
tcg/ppc/tcg-target.inc.c =            | 7 = +++++--

This part must be a = separate patch.


@@ -3149,6 +3150,7 @@ static void = tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
=     static const uint32_t
=         add_op[4] =3D { VADDUBM, = VADDUHM, VADDUWM, VADDUDM },
=         sub_op[4] =3D { VSUBUBM, = VSUBUHM, VSUBUWM, VSUBUDM },
+ =        mul_op[4] =3D { 0, 0, VMULUWM, = VMULLD },
=         neg_op[4] =3D { 0, 0, = VNEGW, VNEGD },
=         eq_op[4]  =3D { = VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
=         ne_op[4]  =3D { = VCMPNEB, VCMPNEH, VCMPNEW, 0 },
@@ -3199,8 +3201,9 @@ = static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
=         a1 =3D 0;
=         break;
=     case INDEX_op_mul_vec:
- =        tcg_debug_assert(vece =3D=3D = MO_32 && have_isa_2_07);
- =        insn =3D VMULUWM;
+ =        tcg_debug_assert((vece =3D=3D = MO_32 && have_isa_2_07) ||
+ =             &n= bsp;           (vec= e =3D=3D MO_64 && have_isa_3_10));
+ =        insn =3D mul_op[vece];

I think it would be ok to just = index mul_op here, since the real isa check is
to be done = elsewhere.

Just keep "insn =3D mul_op[vece];"
and = remove"        tcg_debug_assert((vece =3D=3D MO_32 = && have_isa_2_07) ||
        =                  (vece =3D=3D= MO_64 && have_isa_3_10));=E2=80=9C?


Missing a change to tcg_can_emit_vec_op to do = that isa check, and allow
INDEX_op_mul_vec to be used for = MO_64.

something like below?
"
@@ -3016,6 +3016,8 @@ int = tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned = vece)
           =   return -1;
         case = MO_32:
           =   return have_isa_2_07 ? 1 : -1;
+  =       case MO_64:
+  =           return have_isa_3_10 ? 1 : = -1;
         = }
"


Missing a change to tcg_target_init to test = for PPC_FEATURE2_ARCH_3_1.
something like below?
@@ -3712,6 +3712,11 @@ static = void tcg_target_init(TCGContext *s)
         have_isa =3D = tcg_isa_3_00;
     }
 #endif
+#ifdef = PPC_FEATURE2_ARCH_3_10
+  =   if (hwcap2 & PPC_FEATURE2_ARCH_3_10) {
+        have_isa =3D = tcg_isa_3_10;
+    }
+#endif

+++ = b/include/elf.h
@@ = -554,6 +554,7 @@ typedef struct = {
 #define PPC_FEATURE2_HTM_NOSC       =     0x01000000
 #define PPC_FEATURE2_ARCH_3_00      =     0x00800000
 #define PPC_FEATURE2_HAS_IEEE128      =   0x00400000
+#define = PPC_FEATURE2_ARCH_3_10          = 0x00200000


Thanks,
Lijun
= --Apple-Mail=_4328898D-CD54-42A7-A4EC-1771B91DC396--