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Wed, 8 Jul 2020 10:56:35 +0000 (GMT) Received: from [9.199.55.23] (unknown [9.199.55.23]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTPS; Wed, 8 Jul 2020 10:56:35 +0000 (GMT) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 13.4 \(3608.80.23.2.2\)) Subject: Re: [PATCH v2 06/10] powerpc/perf: power10 Performance Monitoring support From: Athira Rajeev In-Reply-To: Date: Wed, 8 Jul 2020 16:26:32 +0530 Content-Transfer-Encoding: quoted-printable Message-Id: References: <1593595262-1433-1-git-send-email-atrajeev@linux.vnet.ibm.com> <1593595262-1433-7-git-send-email-atrajeev@linux.vnet.ibm.com> To: Michael Neuling X-Mailer: Apple Mail (2.3608.80.23.2.2) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-08_07:2020-07-08, 2020-07-08 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 cotscore=-2147483648 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007080073 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: maddy@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" > On 07-Jul-2020, at 12:20 PM, Michael Neuling = wrote: >=20 >=20 >> @@ -480,6 +520,7 @@ int isa207_compute_mmcr(u64 event[], int n_ev, >> mmcr[1] =3D mmcr1; >> mmcr[2] =3D mmcra; >> mmcr[3] =3D mmcr2; >> + mmcr[4] =3D mmcr3; >=20 > This is fragile like the kvm vcpu case I commented on before but it = gets passed > in via a function parameter?! Can you create a struct to store these = in rather > than this odd ball numbering? Mikey, Yes, it gets passed as cpuhw->mmcr array=20 I will check on these cleanup changes for the kvm vcpu case as well as = cpu_hw_events mmcr array Thanks Athira >=20 > The cleanup should start in patch 1/10 here: >=20 > /* > * The order of the MMCR array is: > - * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2 > + * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2, MMCR3 > * - 32-bit, MMCR0, MMCR1, MMCR2 > */ > - unsigned long mmcr[4]; > + unsigned long mmcr[5]; >=20 >=20 >=20 > mikey