From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Tian, Kevin" <kevin.tian@intel.com>
Subject: Re: [PATCH v3 09/10] VT-d: use qword MMIO access for
 MSI address writes
Date: Thu, 11 Jun 2015 07:45:21 +0000
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To: Jan Beulich <JBeulich@suse.com>, xen-devel <xen-devel@lists.xenproject.org>
Cc: "Zhang, Yang Z" <yang.z.zhang@intel.com>
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> From: Jan Beulich [mailto:JBeulich@suse.com]
> Sent: Friday, June 05, 2015 7:26 PM
> 
> Also make dmar_{read,write}q() actually do what their names suggest (we
> don't need to be concerned of 32-bit restrictions anymore).
> 
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Acked-by: Kevin Tian <kevin.tian@intel.com>

> 
> --- a/xen/drivers/passthrough/vtd/iommu.c
> +++ b/xen/drivers/passthrough/vtd/iommu.c
> @@ -1054,8 +1054,7 @@ static void dma_msi_set_affinity(struct
> 
>      spin_lock_irqsave(&iommu->register_lock, flags);
>      dmar_writel(iommu->reg, DMAR_FEDATA_REG, msg.data);
> -    dmar_writel(iommu->reg, DMAR_FEADDR_REG, msg.address_lo);
> -    dmar_writel(iommu->reg, DMAR_FEUADDR_REG, msg.address_hi);
> +    dmar_writeq(iommu->reg, DMAR_FEADDR_REG, msg.address);
>      spin_unlock_irqrestore(&iommu->register_lock, flags);
>  }
> 
> --- a/xen/drivers/passthrough/vtd/iommu.h
> +++ b/xen/drivers/passthrough/vtd/iommu.h
> @@ -51,17 +51,10 @@
>  #define    DMAR_IRTA_REG   0xB8    /* intr remap */
> 
>  #define OFFSET_STRIDE        (9)
> -#define dmar_readl(dmar, reg) readl(dmar + reg)
> -#define dmar_writel(dmar, reg, val) writel(val, dmar + reg)
> -#define dmar_readq(dmar, reg) ({ \
> -        u32 lo, hi; \
> -        lo = dmar_readl(dmar, reg); \
> -        hi = dmar_readl(dmar, reg + 4); \
> -        (((u64) hi) << 32) + lo; })
> -#define dmar_writeq(dmar, reg, val) do {\
> -        dmar_writel(dmar, reg, (u32)val); \
> -        dmar_writel(dmar, reg + 4, (u32)((u64) val >> 32)); \
> -    } while (0)
> +#define dmar_readl(dmar, reg) readl((dmar) + (reg))
> +#define dmar_readq(dmar, reg) readq((dmar) + (reg))
> +#define dmar_writel(dmar, reg, val) writel(val, (dmar) + (reg))
> +#define dmar_writeq(dmar, reg, val) writeq(val, (dmar) + (reg))
> 
>  #define VER_MAJOR(v)        (((v) & 0xf0) >> 4)
>  #define VER_MINOR(v)        ((v) & 0x0f)
> 
>