From: "Tian, Kevin" <kevin.tian@intel.com>
To: 'Jan Beulich' <JBeulich@suse.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
Xuquan <xuquan8@huawei.com>,
"osstest-admin@xenproject.org" <osstest-admin@xenproject.org>,
xen-devel <xen-devel@lists.xenproject.org>,
"Gao, Chao" <chao.gao@intel.com>
Subject: Re: [xen-unstable test] 106504: regressions - FAIL
Date: Fri, 24 Mar 2017 08:49:14 +0000 [thread overview]
Message-ID: <AADFC41AFE54684AB9EE6CBC0274A5D190C7D036@SHSMSX101.ccr.corp.intel.com> (raw)
In-Reply-To: <AADFC41AFE54684AB9EE6CBC0274A5D190C7CFB9@SHSMSX101.ccr.corp.intel.com>
> From: Tian, Kevin
> Sent: Friday, March 24, 2017 4:26 PM
>
> > From: Jan Beulich [mailto:JBeulich@suse.com]
> > Sent: Friday, March 24, 2017 4:18 PM
> >
> > >>> On 24.03.17 at 08:48, <kevin.tian@intel.com> wrote:
> > >> From: Jan Beulich [mailto:JBeulich@suse.com]
> > >> Sent: Wednesday, March 22, 2017 8:48 PM
> > >>
> > >> > 3. We read RTE 3 times. 1st happens when we set vIRR. 2nd happens
> > >> > when
> > >> > pt_update_irq() returns. 3rd happens in pt_intr_post(). If guest
> > >> > changes the vector in RTE during the window, it will also incur
> > >> > losing or getting more periodic timer interrupt.
> > >>
> > >> Which raises the question whether latching the value read the first
> > >> time would address the issue you demonstrate with the test case.
> > >> Or alternatively deferring writes to take effect only once readers
> > >> are done with their perhaps multiple accesses?
> > >>
> > >> Can you get in touch with your chipset folks to find out whether
> > >> hardware has cases where multiple reads occur during the processing
> > >> of a single
> > > event?
> > >>
> > >
> > > There is a similar case. For level-triggered interrupt, there is a
> > > "remote IRR"
> > > bit in RTE which is set to 1 when LAPIC accepts the level interrupt
> > > sent by IOAPIC. It's then cleared by EOI broadcast from LAPIC
> > > later, based on matching interrupt vectors. If software happens to
> > > change the vector of the said RTE in-between, "remote IRR" bit will
> > > never be cleared (it expects an EOI with new vector now while actual
> > > EOI for previous injection contains old vector).
> >
> > Hmm, I'd expect such a write to clear IRR at once, if somebody really
> > wrote code this way. Or is the bit wrongly documented R/W?
> >
>
> It's read-only to software, but cleared only when accepting EOI.
>
btw it's also the reason why we set EOI exit bitmap for level-triggered
interrupt in APICv, to allow proper emulation of above behavior. :-)
Thanks
Kevin
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next prev parent reply other threads:[~2017-03-24 8:49 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-07 5:52 [xen-unstable test] 106504: regressions - FAIL osstest service owner
2017-03-07 9:16 ` Jan Beulich
2017-03-07 4:24 ` Chao Gao
2017-03-07 14:11 ` Jan Beulich
2017-03-22 4:53 ` Chao Gao
2017-03-22 12:47 ` Jan Beulich
2017-03-22 6:13 ` Chao Gao
2017-03-22 13:40 ` Jan Beulich
2017-03-29 3:28 ` Xuquan (Quan Xu)
2017-03-28 20:48 ` Chao Gao
2017-03-24 7:48 ` Tian, Kevin
2017-03-24 8:17 ` Jan Beulich
2017-03-24 8:25 ` Tian, Kevin
[not found] ` <AADFC41AFE54684AB9EE6CBC0274A5D190C7CFB9@SHSMSX101.ccr.corp.intel.com>
2017-03-24 8:49 ` Tian, Kevin [this message]
2017-03-24 9:00 ` Andrew Cooper
2017-04-04 23:57 ` Chao Gao
2017-04-05 7:48 ` Jan Beulich
2017-04-05 1:49 ` Chao Gao
2017-04-07 8:56 ` Xuquan (Quan Xu)
2017-03-08 3:16 ` Xuquan (Quan Xu)
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