Re: [Qemu-devel] [PATCH 4/8] target-arm: fiddle decoding of 64 bit shift by imm and narrow

[Peter Maydell <peter.maydell@linaro.org>]

On 31 January 2011 18:06,  <christophe.lyon@st.com> wrote:
> From: Christophe Lyon <christophe.lyon@st.com>
>
> Tweak decoding of the shift-by-imm and narrow 64 bit insns
> (VSHRN, VRSHRN, VQSHRN, VQSHRUN, VQRSHRN, VQRSHRUN).
>
> Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
> ---
>  target-arm/translate.c |   28 ++++++++++++++++++----------
>  1 files changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 9ca5b82..a614e34 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -4831,21 +4831,29 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
>                     if (size == 3) {
>                         neon_load_reg64(cpu_V0, rm + pass);
>                         if (q) {
> -                          if (u)
> -                            gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64);
> -                          else
> -                            gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64);
> +                            if ((op == 8 && !u) || (op == 9 && u)) {

This patch would improved if you started with:
                int input_unsigned = (op == 8) ? !u : u;
and then used that here and:

> +                            if ((op == 8 && !u) || (op == 9 && u)) {

here...

> +                        gen_neon_shift_narrow(size, tmp, tmp2, q,
> +                                              (op == 8) ? !u : u);

here...

> +                        gen_neon_shift_narrow(size, tmp3, tmp2, q,
> +                                              (op == 8) ? !u : u);

and here.

(What all these things are trying to check is whether the
input elements for the operations are signed or unsigned;
this isn't the same as the u bit, which is whether the output
is unsigned.)

-- PMM