From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dima Zavin Subject: Re: [PATCH v2 02/11] msm: Generalize timer register mappings Date: Wed, 26 Jan 2011 14:12:59 -0800 Message-ID: References: <1292384961-8851-1-git-send-email-stepanm@codeaurora.org> <1295468747-22796-1-git-send-email-davidb@codeaurora.org> <1295468747-22796-3-git-send-email-davidb@codeaurora.org> <1295908604.29639.62.camel@c-dwalke-linux.qualcomm.com> <8yaei81kjlc.fsf@huya.qualcomm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Received: from smtp-out.google.com ([216.239.44.51]:45831 "EHLO smtp-out.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753487Ab1AZWNC convert rfc822-to-8bit (ORCPT ); Wed, 26 Jan 2011 17:13:02 -0500 Received: from hpaq7.eem.corp.google.com (hpaq7.eem.corp.google.com [172.25.149.7]) by smtp-out.google.com with ESMTP id p0QMD0Os002302 for ; Wed, 26 Jan 2011 14:13:01 -0800 Received: from qyk32 (qyk32.prod.google.com [10.241.83.160]) by hpaq7.eem.corp.google.com with ESMTP id p0QMCnZE001527 (version=TLSv1/SSLv3 cipher=RC4-MD5 bits=128 verify=NOT) for ; Wed, 26 Jan 2011 14:12:59 -0800 Received: by qyk32 with SMTP id 32so5697583qyk.16 for ; Wed, 26 Jan 2011 14:12:59 -0800 (PST) In-Reply-To: <8yaei81kjlc.fsf@huya.qualcomm.com> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: David Brown Cc: Daniel Walker , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org On Mon, Jan 24, 2011 at 2:44 PM, David Brown wr= ote: > On Mon, Jan 24 2011, Daniel Walker wrote: > >> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote: >>> + =A0 =A0 =A0 int global_offset =3D 0; >>> + >>> + =A0 =A0 =A0 if (cpu_is_msm7x01()) { >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 msm_clocks[MSM_CLOCK_GPT].regbase =3D= MSM_CSR_BASE; >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 msm_clocks[MSM_CLOCK_DGT].regbase =3D= MSM_CSR_BASE + 0x10; >>> + =A0 =A0 =A0 } else if (cpu_is_msm7x30()) { >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 msm_clocks[MSM_CLOCK_GPT].regbase =3D= MSM_CSR_BASE + 0x04; >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 msm_clocks[MSM_CLOCK_DGT].regbase =3D= MSM_CSR_BASE + 0x24; >>> + =A0 =A0 =A0 } else if (cpu_is_qsd8x50()) { >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 msm_clocks[MSM_CLOCK_GPT].regbase =3D= MSM_CSR_BASE; >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 msm_clocks[MSM_CLOCK_DGT].regbase =3D= MSM_CSR_BASE + 0x10; >>> + =A0 =A0 =A0 } else if (cpu_is_msm8x60()) { >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 msm_clocks[MSM_CLOCK_GPT].regbase =3D= MSM_TMR_BASE + 0x04; >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 msm_clocks[MSM_CLOCK_DGT].regbase =3D= MSM_TMR_BASE + 0x24; >>> + >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* Use CPU0's timer as the global tim= er. */ >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 global_offset =3D MSM_TMR0_BASE - MSM= _TMR_BASE; >>> + =A0 =A0 =A0 } else >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 BUG(); >> >> Ifdef's here would be OK I think, your already using the "runtime" >> checks .. > > The point of the change is to get rid of the ifdefs so that we can > dynamically detect which target we are on. =A0Yes, there are other pl= aces > where it doesn't work, but we'll get there gradually. To be honest I don't understand why you would want to do this at runtime. You cannot select multiple SoCs in the kernel build anyway, nor would you want to. Trying to have same kernel to boot on ARM v6 and ARM v7 would already be freaky enough. On top of that mixing 7201a with all the baggage that it comes with 8x60 just wouldn't make sense. These architectures are so different that it I can't see that ever being useful. When would you ever envision building for multiple of these SoCs at the same time? --Dima > > David > > -- > Sent by an employee of the Qualcomm Innovation Center, Inc. > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora F= orum. > -- > To unsubscribe from this list: send the line "unsubscribe linux-kerne= l" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at =A0http://vger.kernel.org/majordomo-info.html > Please read the FAQ at =A0http://www.tux.org/lkml/ > -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm= " in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753903Ab1AZWNF (ORCPT ); Wed, 26 Jan 2011 17:13:05 -0500 Received: from smtp-out.google.com ([74.125.121.67]:26062 "EHLO smtp-out.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753424Ab1AZWND convert rfc822-to-8bit (ORCPT ); Wed, 26 Jan 2011 17:13:03 -0500 DomainKey-Signature: a=rsa-sha1; c=nofws; d=google.com; s=beta; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=Xg8TukPNshsHnp471EntXDbvLaxidYKAE7d4IexPD/xuGcyZvgUHZjQdhtnsaQKcmg T2jikKZg6r1W/v/zqtOg== MIME-Version: 1.0 In-Reply-To: <8yaei81kjlc.fsf@huya.qualcomm.com> References: <1292384961-8851-1-git-send-email-stepanm@codeaurora.org> <1295468747-22796-1-git-send-email-davidb@codeaurora.org> <1295468747-22796-3-git-send-email-davidb@codeaurora.org> <1295908604.29639.62.camel@c-dwalke-linux.qualcomm.com> <8yaei81kjlc.fsf@huya.qualcomm.com> Date: Wed, 26 Jan 2011 14:12:59 -0800 Message-ID: Subject: Re: [PATCH v2 02/11] msm: Generalize timer register mappings From: Dima Zavin To: David Brown Cc: Daniel Walker , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-System-Of-Record: true Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 24, 2011 at 2:44 PM, David Brown wrote: > On Mon, Jan 24 2011, Daniel Walker wrote: > >> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote: >>> +       int global_offset = 0; >>> + >>> +       if (cpu_is_msm7x01()) { >>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; >>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; >>> +       } else if (cpu_is_msm7x30()) { >>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04; >>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24; >>> +       } else if (cpu_is_qsd8x50()) { >>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; >>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; >>> +       } else if (cpu_is_msm8x60()) { >>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04; >>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24; >>> + >>> +               /* Use CPU0's timer as the global timer. */ >>> +               global_offset = MSM_TMR0_BASE - MSM_TMR_BASE; >>> +       } else >>> +               BUG(); >> >> Ifdef's here would be OK I think, your already using the "runtime" >> checks .. > > The point of the change is to get rid of the ifdefs so that we can > dynamically detect which target we are on.  Yes, there are other places > where it doesn't work, but we'll get there gradually. To be honest I don't understand why you would want to do this at runtime. You cannot select multiple SoCs in the kernel build anyway, nor would you want to. Trying to have same kernel to boot on ARM v6 and ARM v7 would already be freaky enough. On top of that mixing 7201a with all the baggage that it comes with 8x60 just wouldn't make sense. These architectures are so different that it I can't see that ever being useful. When would you ever envision building for multiple of these SoCs at the same time? --Dima > > David > > -- > Sent by an employee of the Qualcomm Innovation Center, Inc. > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at  http://vger.kernel.org/majordomo-info.html > Please read the FAQ at  http://www.tux.org/lkml/ > From mboxrd@z Thu Jan 1 00:00:00 1970 From: dmitriyz@google.com (Dima Zavin) Date: Wed, 26 Jan 2011 14:12:59 -0800 Subject: [PATCH v2 02/11] msm: Generalize timer register mappings In-Reply-To: <8yaei81kjlc.fsf@huya.qualcomm.com> References: <1292384961-8851-1-git-send-email-stepanm@codeaurora.org> <1295468747-22796-1-git-send-email-davidb@codeaurora.org> <1295468747-22796-3-git-send-email-davidb@codeaurora.org> <1295908604.29639.62.camel@c-dwalke-linux.qualcomm.com> <8yaei81kjlc.fsf@huya.qualcomm.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Jan 24, 2011 at 2:44 PM, David Brown wrote: > On Mon, Jan 24 2011, Daniel Walker wrote: > >> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote: >>> + ? ? ? int global_offset = 0; >>> + >>> + ? ? ? if (cpu_is_msm7x01()) { >>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; >>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; >>> + ? ? ? } else if (cpu_is_msm7x30()) { >>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04; >>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24; >>> + ? ? ? } else if (cpu_is_qsd8x50()) { >>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; >>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; >>> + ? ? ? } else if (cpu_is_msm8x60()) { >>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04; >>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24; >>> + >>> + ? ? ? ? ? ? ? /* Use CPU0's timer as the global timer. */ >>> + ? ? ? ? ? ? ? global_offset = MSM_TMR0_BASE - MSM_TMR_BASE; >>> + ? ? ? } else >>> + ? ? ? ? ? ? ? BUG(); >> >> Ifdef's here would be OK I think, your already using the "runtime" >> checks .. > > The point of the change is to get rid of the ifdefs so that we can > dynamically detect which target we are on. ?Yes, there are other places > where it doesn't work, but we'll get there gradually. To be honest I don't understand why you would want to do this at runtime. You cannot select multiple SoCs in the kernel build anyway, nor would you want to. Trying to have same kernel to boot on ARM v6 and ARM v7 would already be freaky enough. On top of that mixing 7201a with all the baggage that it comes with 8x60 just wouldn't make sense. These architectures are so different that it I can't see that ever being useful. When would you ever envision building for multiple of these SoCs at the same time? --Dima > > David > > -- > Sent by an employee of the Qualcomm Innovation Center, Inc. > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at ?http://vger.kernel.org/majordomo-info.html > Please read the FAQ at ?http://www.tux.org/lkml/ >