From mboxrd@z Thu Jan  1 00:00:00 1970
From: zhangfei gao <zhangfei.gao@gmail.com>
Subject: Re: [Patch 1/1]sdhci: verify ddr50 mode
Date: Wed, 3 Nov 2010 23:26:50 -0400
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Cc: Adrian Hunter <adrian.hunter@nokia.com>, Hanumath Prasad <hanumath.prasad@stericsson.com>, Chris Ball <cjb@laptop.org>, Matt Fleming <matt@console-pimps.org>, eric.y.miao@gmail.com, Haojian Zhuang <haojian.zhuang@gmail.com>

Hi All,

The regulator voltage change need some time to keep stable, how could
we put in set_ios, which inside spin_lock, can not use msleep.

>>From spec 3.0.
1.8V Signaling Enable Setting
Setting this bit from 1 to 1 starts changing signal voltage from 3.3v
to 1.8v. 1.8v voltage output shall be stable within 5ms. Host
Contrller clears this bit if switching to 1.8v fails.
Clearing this bit from 1 to 0 starts changing signal voltage from 1.8v
to 3.3v . 3.3V regulatro output shall be stable within 5ms.

According to spec, we should wait 5ms to check SDHCI_CTRL2_1_8V
whether it is set or not.
However, here is spin_lock, and we can not put msleep inside.
Our controller does not switch to 1.8v in fact, so the ddr50 mode work
at 3.3v in fact.
Currently our controller count on external pmic to provide 1.8v when
support SBR mode, however, how to consider wait 5ms or so to wait
regulator to be stable.

Thanks

+       if (ddr & MMC_1_8V_DDR_MODE) {
+               con = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+               con |= SDHCI_CTRL2_1_8V;
+               sdhci_writew(host, con, SDHCI_HOST_CONTROL2);
+
+               /* Wait 5 ms to check 1.8v regulator swithing success or not */
+               msleep(5);
+               if (!(sdhci_readw(host, SDHCI_HOST_CONTROL2)
+                                       & SDHCI_CTRL2_1_8V)) {
+                       printk(KERN_ERR "%s: HOST CONTROL fail switch
to 1.8v\n",
+                                       mmc_hostname(host->mmc));
+                       sdhci_dumpregs(host);
+                       return;
+               }
+               con = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+               con &= ~SDHCI_CTRL2_UHS_MASK;
+               if (ddr & MMC_1_8V_DDR_MODE)
+                       con |= SDHCI_CTRL2_DDR50;
+               sdhci_writew(host, con, SDHCI_HOST_CONTROL2);
+       }