From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=60467 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PU1vC-0004FV-0w for qemu-devel@nongnu.org; Sat, 18 Dec 2010 13:54:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PU1v9-0003My-Td for qemu-devel@nongnu.org; Sat, 18 Dec 2010 13:54:21 -0500 Received: from mail-px0-f174.google.com ([209.85.212.174]:38042) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PU1v9-0003MS-GR for qemu-devel@nongnu.org; Sat, 18 Dec 2010 13:54:19 -0500 Received: by pxi15 with SMTP id 15so325526pxi.33 for ; Sat, 18 Dec 2010 10:54:18 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <4D0CEAB0.9030706@mc.net> References: <4D0CEAB0.9030706@mc.net> From: Blue Swirl Date: Sat, 18 Dec 2010 18:53:58 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] Re: [PATCH] sparc32: ledma extra registers List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bob Breuer Cc: qemu-devel@nongnu.org Thanks, applied. On Sat, Dec 18, 2010 at 5:09 PM, Bob Breuer wrote: > ledma has 0x20 bytes of registers according to OBP, and at least Solaris9 > reads the 5th register which is beyond what we've mapped. =C2=A0So let's = setup > a flag (inspired by a previous patch from Blue Swirl) to identify ledma > from espdma, and map another 16 bytes of registers which return 0. > > Signed-off-by: Bob Breuer > --- > =C2=A0hw/sparc32_dma.c | =C2=A0 15 ++++++++++++++- > =C2=A0hw/sun4m.c =C2=A0 =C2=A0 =C2=A0 | =C2=A0 16 +++++++++------- > =C2=A02 files changed, 23 insertions(+), 8 deletions(-) > > diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c > index e78f025..56be8c8 100644 > --- a/hw/sparc32_dma.c > +++ b/hw/sparc32_dma.c > @@ -44,6 +44,9 @@ > =C2=A0/* We need the mask, because one instance of the device is not page > =C2=A0 =C2=A0aligned (ledma, start address 0x0010) */ > =C2=A0#define DMA_MASK (DMA_SIZE - 1) > +/* ledma has more than 4 registers, Solaris reads the 5th one */ > +#define DMA_ETH_SIZE (8 * sizeof(uint32_t)) > +#define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1) > > =C2=A0#define DMA_VER 0xa0000000 > =C2=A0#define DMA_INTR 1 > @@ -65,6 +68,7 @@ struct DMAState { > =C2=A0 =C2=A0 qemu_irq irq; > =C2=A0 =C2=A0 void *iommu; > =C2=A0 =C2=A0 qemu_irq gpio[2]; > + =C2=A0 =C2=A0uint32_t is_ledma; > =C2=A0}; > > =C2=A0enum { > @@ -165,6 +169,9 @@ static uint32_t dma_mem_readl(void *opaque, target_ph= ys_addr_t addr) > =C2=A0 =C2=A0 DMAState *s =3D opaque; > =C2=A0 =C2=A0 uint32_t saddr; > > + =C2=A0 =C2=A0if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0; /* extra mystery register(s) */ > + =C2=A0 =C2=A0} > =C2=A0 =C2=A0 saddr =3D (addr & DMA_MASK) >> 2; > =C2=A0 =C2=A0 trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]); > =C2=A0 =C2=A0 return s->dmaregs[saddr]; > @@ -175,6 +182,9 @@ static void dma_mem_writel(void *opaque, target_phys_= addr_t addr, uint32_t val) > =C2=A0 =C2=A0 DMAState *s =3D opaque; > =C2=A0 =C2=A0 uint32_t saddr; > > + =C2=A0 =C2=A0if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0return; /* extra mystery register(s) */ > + =C2=A0 =C2=A0} > =C2=A0 =C2=A0 saddr =3D (addr & DMA_MASK) >> 2; > =C2=A0 =C2=A0 trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val); > =C2=A0 =C2=A0 switch (saddr) { > @@ -254,12 +264,14 @@ static int sparc32_dma_init1(SysBusDevice *dev) > =C2=A0{ > =C2=A0 =C2=A0 DMAState *s =3D FROM_SYSBUS(DMAState, dev); > =C2=A0 =C2=A0 int dma_io_memory; > + =C2=A0 =C2=A0int reg_size; > > =C2=A0 =C2=A0 sysbus_init_irq(dev, &s->irq); > > =C2=A0 =C2=A0 dma_io_memory =3D cpu_register_io_memory(dma_mem_read, dma_= mem_write, s, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0DEVICE_NATIVE_ENDIAN); > - =C2=A0 =C2=A0sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory); > + =C2=A0 =C2=A0reg_size =3D s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE; > + =C2=A0 =C2=A0sysbus_init_mmio(dev, reg_size, dma_io_memory); > > =C2=A0 =C2=A0 qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1); > =C2=A0 =C2=A0 qdev_init_gpio_out(&dev->qdev, s->gpio, 2); > @@ -275,6 +287,7 @@ static SysBusDeviceInfo sparc32_dma_info =3D { > =C2=A0 =C2=A0 .qdev.reset =3D dma_reset, > =C2=A0 =C2=A0 .qdev.props =3D (Property[]) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_PTR("iommu_opaque", DMAState, iom= mu), > + =C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_UINT32("is_ledma", DMAState, is_= ledma, 0), > =C2=A0 =C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_END_OF_LIST(), > =C2=A0 =C2=A0 } > =C2=A0}; > diff --git a/hw/sun4m.c b/hw/sun4m.c > index 4795b3f..30e8a21 100644 > --- a/hw/sun4m.c > +++ b/hw/sun4m.c > @@ -378,13 +378,14 @@ static void *iommu_init(target_phys_addr_t addr, ui= nt32_t version, qemu_irq irq) > =C2=A0} > > =C2=A0static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq pa= rent_irq, > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0void *iommu, qemu_irq *dev_irq) > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0void *iommu, qemu_irq *dev_irq, int is_le= dma) > =C2=A0{ > =C2=A0 =C2=A0 DeviceState *dev; > =C2=A0 =C2=A0 SysBusDevice *s; > > =C2=A0 =C2=A0 dev =3D qdev_create(NULL, "sparc32_dma"); > =C2=A0 =C2=A0 qdev_prop_set_ptr(dev, "iommu_opaque", iommu); > + =C2=A0 =C2=A0qdev_prop_set_uint32(dev, "is_ledma", is_ledma); > =C2=A0 =C2=A0 qdev_init_nofail(dev); > =C2=A0 =C2=A0 s =3D sysbus_from_qdev(dev); > =C2=A0 =C2=A0 sysbus_connect_irq(s, 0, parent_irq); > @@ -862,10 +863,10 @@ static void sun4m_hw_init(const struct sun4m_hwdef = *hwdef, ram_addr_t RAM_size, > =C2=A0 =C2=A0 } > > =C2=A0 =C2=A0 espdma =3D sparc32_dma_init(hwdef->dma_base, slavio_irq[18]= , > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0iommu, &espdma_irq); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0iommu, &espdma_irq, 0); > > =C2=A0 =C2=A0 ledma =3D sparc32_dma_init(hwdef->dma_base + 16ULL, > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 slavio_irq[16], iommu, &ledma_irq); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 slavio_irq[16], iommu, &ledma_irq, 1); > > =C2=A0 =C2=A0 if (graphic_depth !=3D 8 && graphic_depth !=3D 24) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 fprintf(stderr, "qemu: Unsupported depth: %d\= n", graphic_depth); > @@ -1524,10 +1525,11 @@ static void sun4d_hw_init(const struct sun4d_hwde= f *hwdef, ram_addr_t RAM_size, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 sbi_irq[0]); > > =C2=A0 =C2=A0 espdma =3D sparc32_dma_init(hwdef->espdma_base, sbi_irq[3], > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0iounits[0], &espdma_irq); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0iounits[0], &espdma_irq, 0); > > + =C2=A0 =C2=A0/* should be lebuffer instead */ > =C2=A0 =C2=A0 ledma =3D sparc32_dma_init(hwdef->ledma_base, sbi_irq[4], > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 iounits[0], &ledma_irq); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 iounits[0], &ledma_irq, 0); > > =C2=A0 =C2=A0 if (graphic_depth !=3D 8 && graphic_depth !=3D 24) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 fprintf(stderr, "qemu: Unsupported depth: %d\= n", graphic_depth); > @@ -1707,10 +1709,10 @@ static void sun4c_hw_init(const struct sun4c_hwde= f *hwdef, ram_addr_t RAM_size, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0slavio_irq[1]); > > =C2=A0 =C2=A0 espdma =3D sparc32_dma_init(hwdef->dma_base, slavio_irq[2], > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0iommu, &espdma_irq); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0iommu, &espdma_irq, 0); > > =C2=A0 =C2=A0 ledma =3D sparc32_dma_init(hwdef->dma_base + 16ULL, > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 slavio_irq[3], iommu, &ledma_irq); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 slavio_irq[3], iommu, &ledma_irq, 1); > > =C2=A0 =C2=A0 if (graphic_depth !=3D 8 && graphic_depth !=3D 24) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 fprintf(stderr, "qemu: Unsupported depth: %d\= n", graphic_depth); > > >