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Date: Fri, 25 Feb 2011 12:51:55 +0100
Message-ID: <AANLkTik-pxvNsmcZkbq+oE7Cb=AAZF2FShuOc44Z2A2a@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH 02/10] pxa2xx_pic: update to use qdev and
	arm-pic
From: andrzej zaborowski <balrogg@gmail.com>
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To: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Cc: qemu-devel@nongnu.org

Hi Dmitry,

On 20 February 2011 14:50, Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> w=
rote:
> Use qdev/sysbus framework to handle pxa2xx-pic. Instead of exposing IRQs
> via array, reference them via qdev_get_gpio_in(). Also pxa2xx_pic duplica=
ted
> some code from arm-pic. Drop it, replacing with references to arm-pic,
> as all other ARM SoCs do for their PIC code.

As I said earlier not using arm-pic was deliberate (and I also asked
what the gain was from converting the pic to a separate sysbus device
from the CPU) so I skipped this part of the patch and pushed the rest
of it, please check that everything works.

>
> Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
> ---
> =C2=A0hw/mainstone.c =C2=A0 =C2=A0| =C2=A0 =C2=A02 +-
> =C2=A0hw/pxa.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 12 +++--
> =C2=A0hw/pxa2xx.c =C2=A0 =C2=A0 =C2=A0 | =C2=A0 84 ++++++++++++++++++++++=
+------------
> =C2=A0hw/pxa2xx_gpio.c =C2=A0| =C2=A0 11 +++--
> =C2=A0hw/pxa2xx_pic.c =C2=A0 | =C2=A0126 ++++++++++++++++++++++++++++----=
---------------------
> =C2=A0hw/pxa2xx_timer.c | =C2=A0 16 +++---
> =C2=A06 files changed, 144 insertions(+), 107 deletions(-)
>
> diff --git a/hw/mainstone.c b/hw/mainstone.c
> index aec8d34..4eabdb9 100644
> --- a/hw/mainstone.c
> +++ b/hw/mainstone.c
> @@ -140,7 +140,7 @@ static void mainstone_common_init(ram_addr_t ram_size=
,
> =C2=A0 =C2=A0 }
>
> =C2=A0 =C2=A0 mst_irq =3D sysbus_create_simple("mainstone-fpga", MST_FPGA=
_PHYS,
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cp=
u->pic[PXA2XX_PIC_GPIO_0]);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qd=
ev_get_gpio_in(cpu->pic, PXA2XX_PIC_GPIO_0));

I'm also wondering if this device should really use the interrupt line
instead of using a GPIO.  It seems wrong that both the fpga and the
gpio module are connected to the same line.

>
> =C2=A0 =C2=A0 /* setup keypad */
> =C2=A0 =C2=A0 printf("map addr %p\n", &map);
> diff --git a/hw/pxa.h b/hw/pxa.h
> index f73d33b..7c6fd44 100644
> --- a/hw/pxa.h
> +++ b/hw/pxa.h
> @@ -63,15 +63,16 @@
> =C2=A0# define PXA2XX_INTERNAL_SIZE =C2=A00x40000
>
> =C2=A0/* pxa2xx_pic.c */
> -qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
> +DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq *arm_pic);
>
> =C2=A0/* pxa2xx_timer.c */
> -void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
> -void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq=
 irq4);
> +void pxa25x_timer_init(target_phys_addr_t base, DeviceState *pic);
> +void pxa27x_timer_init(target_phys_addr_t base, DeviceState *pic);
>
> =C2=A0/* pxa2xx_gpio.c */
> =C2=A0DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0CPUState *env, q=
emu_irq *pic, int lines);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0CPUState *env, D=
eviceState *pic, int lines);
> =C2=A0void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
>
> =C2=A0/* pxa2xx_dma.c */
> @@ -125,7 +126,7 @@ typedef struct PXA2xxFIrState PXA2xxFIrState;
>
> =C2=A0typedef struct {
> =C2=A0 =C2=A0 CPUState *env;
> - =C2=A0 =C2=A0qemu_irq *pic;
> + =C2=A0 =C2=A0DeviceState *pic;
> =C2=A0 =C2=A0 qemu_irq reset;
> =C2=A0 =C2=A0 PXA2xxDMAState *dma;
> =C2=A0 =C2=A0 DeviceState *gpio;
> @@ -180,6 +181,7 @@ typedef struct {
> =C2=A0 =C2=A0 QEMUTimer *rtc_swal1;
> =C2=A0 =C2=A0 QEMUTimer *rtc_swal2;
> =C2=A0 =C2=A0 QEMUTimer *rtc_pi;
> + =C2=A0 =C2=A0qemu_irq rtc_irq;
> =C2=A0} PXA2xxState;
>
> =C2=A0struct PXA2xxI2SState {
> diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
> index 9ebbce6..58e6e7b 100644
> --- a/hw/pxa2xx.c
> +++ b/hw/pxa2xx.c
> @@ -16,6 +16,7 @@
> =C2=A0#include "qemu-timer.h"
> =C2=A0#include "qemu-char.h"
> =C2=A0#include "blockdev.h"
> +#include "arm-misc.h"
>
> =C2=A0static struct {
> =C2=A0 =C2=A0 target_phys_addr_t io_base;
> @@ -888,7 +889,7 @@ static int pxa2xx_ssp_init(SysBusDevice *dev)
>
> =C2=A0static inline void pxa2xx_rtc_int_update(PXA2xxState *s)
> =C2=A0{
> - =C2=A0 =C2=A0qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2=
553));
> + =C2=A0 =C2=A0qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
> =C2=A0}
>
> =C2=A0static void pxa2xx_rtc_hzupdate(PXA2xxState *s)
> @@ -1197,6 +1198,8 @@ static void pxa2xx_rtc_init(PXA2xxState *s)
> =C2=A0 =C2=A0 s->rtc_swal1 =3D qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_=
tick, s);
> =C2=A0 =C2=A0 s->rtc_swal2 =3D qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_=
tick, s);
> =C2=A0 =C2=A0 s->rtc_pi =C2=A0 =C2=A0=3D qemu_new_timer(rt_clock, pxa2xx_=
rtc_pi_tick, =C2=A0 =C2=A0s);
> +
> + =C2=A0 =C2=A0s->rtc_irq =3D qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALAR=
M);
> =C2=A0}
>
> =C2=A0static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
> @@ -2069,6 +2072,8 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, c=
onst char *revision)
> =C2=A0 =C2=A0 PXA2xxState *s;
> =C2=A0 =C2=A0 int iomemtype, i;
> =C2=A0 =C2=A0 DriveInfo *dinfo;
> + =C2=A0 =C2=A0qemu_irq *arm_pic;
> +
> =C2=A0 =C2=A0 s =3D (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
>
> =C2=A0 =C2=A0 if (revision && strncmp(revision, "pxa27", 5)) {
> @@ -2093,12 +2098,13 @@ PXA2xxState *pxa270_init(unsigned int sdram_size,=
 const char *revision)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x4=
0000, qemu_ram_alloc(NULL, "pxa270.internal",
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 0x40000) | IO_MEM_RAM);
>
> - =C2=A0 =C2=A0s->pic =3D pxa2xx_pic_init(0x40d00000, s->env);
> + =C2=A0 =C2=A0arm_pic =3D arm_pic_init_cpu(s->env);
> + =C2=A0 =C2=A0s->pic =3D pxa2xx_pic_init(0x40d00000, s->env, arm_pic);
>
> - =C2=A0 =C2=A0s->dma =3D pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_D=
MA]);
> + =C2=A0 =C2=A0s->dma =3D pxa27x_dma_init(0x40000000,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2X=
X_PIC_DMA));
>
> - =C2=A0 =C2=A0pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s-=
>pic[PXA27X_PIC_OST_4_11]);
> + =C2=A0 =C2=A0pxa27x_timer_init(0x40a00000, s->pic);
>
> =C2=A0 =C2=A0 s->gpio =3D pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 12=
1);
>
> @@ -2108,26 +2114,30 @@ PXA2xxState *pxa270_init(unsigned int sdram_size,=
 const char *revision)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> =C2=A0 =C2=A0 }
> =C2=A0 =C2=A0 s->mmc =3D pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->pic[PXA2XX_PIC_MMC], s->dma);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),=
 s->dma);
>
> =C2=A0 =C2=A0 for (i =3D 0; pxa270_serial[i].io_base; i ++)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (serial_hds[i])
> =C2=A0#ifdef TARGET_WORDS_BIGENDIAN
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 serial_mm_init(pxa270_serial[i]=
.io_base, 2,
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 s->pic[pxa270_serial[i].irqn], 14857000/16,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 14857000/16,
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0serial_hds[i], 1, 1);
> =C2=A0#else
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 serial_mm_init(pxa270_serial[i]=
.io_base, 2,
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 s->pic[pxa270_serial[i].irqn], 14857000/16,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 14857000/16,
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0serial_hds[i], 1, 0);
> =C2=A0#endif
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 else
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> =C2=A0 =C2=A0 if (serial_hds[i])
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0s->fir =3D pxa2xx_fir_init(0x40800000, s->pi=
c[PXA2XX_PIC_ICP],
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->fir =3D pxa2xx_fir_init(0x40800000,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 s->dma, serial_hds[i]);
>
> - =C2=A0 =C2=A0s->lcd =3D pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_=
LCD]);
> + =C2=A0 =C2=A0s->lcd =3D pxa2xx_lcdc_init(0x44000000,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
>
> =C2=A0 =C2=A0 s->cm_base =3D 0x41300000;
> =C2=A0 =C2=A0 s->cm_regs[CCCR >> 2] =3D 0x02000210; =C2=A0 =C2=A0 =C2=A0 =
=C2=A0/* 416.0 MHz */
> @@ -2159,13 +2169,13 @@ PXA2xxState *pxa270_init(unsigned int sdram_size,=
 const char *revision)
> =C2=A0 =C2=A0 for (i =3D 0; pxa27x_ssp[i].io_base; i ++) {
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 DeviceState *dev;
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev =3D sysbus_create_simple("pxa2xx-ssp", px=
a27x_ssp[i].io_base,
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->pic[pxa27x_ssp[i].irqn]=
);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].i=
rqn));
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->ssp[i] =3D (SSIBus *)qdev_get_child_bus(de=
v, "ssi");
> =C2=A0 =C2=A0 }
>
> =C2=A0 =C2=A0 if (usb_enabled) {
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", 0x4c00000=
0,
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->pic[PXA2XX_PIC_USBH1]);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
> =C2=A0 =C2=A0 }
>
> =C2=A0 =C2=A0 s->pcmcia[0] =3D pxa2xx_pcmcia_init(0x20000000);
> @@ -2179,12 +2189,17 @@ PXA2xxState *pxa270_init(unsigned int sdram_size,=
 const char *revision)
> =C2=A0 =C2=A0 register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 pxa=
2xx_rtc_load, s);
>
> - =C2=A0 =C2=A0s->i2c[0] =3D pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PI=
C_I2C], 0xffff);
> - =C2=A0 =C2=A0s->i2c[1] =3D pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PI=
C_PWRI2C], 0xff);
> + =C2=A0 =C2=A0s->i2c[0] =3D pxa2xx_i2c_init(0x40301600,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2X=
X_PIC_I2C), 0xffff);
> + =C2=A0 =C2=A0s->i2c[1] =3D pxa2xx_i2c_init(0x40f00100,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2X=
X_PIC_PWRI2C), 0xff);
>
> - =C2=A0 =C2=A0s->i2s =3D pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I=
2S], s->dma);
> + =C2=A0 =C2=A0s->i2s =3D pxa2xx_i2s_init(0x40400000,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2X=
X_PIC_I2S),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->dma);
>
> - =C2=A0 =C2=A0s->kp =3D pxa27x_keypad_init(0x41500000, s->pic[PXA2XX_PIC=
_KEYPAD]);
> + =C2=A0 =C2=A0s->kp =3D pxa27x_keypad_init(0x41500000,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2X=
X_PIC_KEYPAD));
>
> =C2=A0 =C2=A0 /* GPIO1 resets the processor */
> =C2=A0 =C2=A0 /* The handler can be overridden by board-specific code */
> @@ -2198,6 +2213,7 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
> =C2=A0 =C2=A0 PXA2xxState *s;
> =C2=A0 =C2=A0 int iomemtype, i;
> =C2=A0 =C2=A0 DriveInfo *dinfo;
> + =C2=A0 =C2=A0qemu_irq *arm_pic;
>
> =C2=A0 =C2=A0 s =3D (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
>
> @@ -2216,11 +2232,13 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qem=
u_ram_alloc(NULL, "pxa255.internal",
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PXA2XX_INTERNAL_SIZE) |=
 IO_MEM_RAM);
>
> - =C2=A0 =C2=A0s->pic =3D pxa2xx_pic_init(0x40d00000, s->env);
> + =C2=A0 =C2=A0arm_pic =3D arm_pic_init_cpu(s->env);
> + =C2=A0 =C2=A0s->pic =3D pxa2xx_pic_init(0x40d00000, s->env, arm_pic);
>
> - =C2=A0 =C2=A0s->dma =3D pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_D=
MA]);
> + =C2=A0 =C2=A0s->dma =3D pxa255_dma_init(0x40000000,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2X=
X_PIC_DMA));
>
> - =C2=A0 =C2=A0pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
> + =C2=A0 =C2=A0pxa25x_timer_init(0x40a00000, s->pic);
>
> =C2=A0 =C2=A0 s->gpio =3D pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85=
);
>
> @@ -2230,27 +2248,31 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> =C2=A0 =C2=A0 }
> =C2=A0 =C2=A0 s->mmc =3D pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->pic[PXA2XX_PIC_MMC], s->dma);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),=
 s->dma);
>
> =C2=A0 =C2=A0 for (i =3D 0; pxa255_serial[i].io_base; i ++)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (serial_hds[i]) {
> =C2=A0#ifdef TARGET_WORDS_BIGENDIAN
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 serial_mm_init(pxa255_serial[i]=
.io_base, 2,
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 s->pic[pxa255_serial[i].irqn], 14745600/16,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 14745600/16,
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0serial_hds[i], 1, 1);
> =C2=A0#else
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 serial_mm_init(pxa255_serial[i]=
.io_base, 2,
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 s->pic[pxa255_serial[i].irqn], 14745600/16,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 14745600/16,
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0serial_hds[i], 1, 0);
> =C2=A0#endif
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> =C2=A0 =C2=A0 if (serial_hds[i])
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0s->fir =3D pxa2xx_fir_init(0x40800000, s->pi=
c[PXA2XX_PIC_ICP],
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->fir =3D pxa2xx_fir_init(0x40800000,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 s->dma, serial_hds[i]);
>
> - =C2=A0 =C2=A0s->lcd =3D pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_=
LCD]);
> + =C2=A0 =C2=A0s->lcd =3D pxa2xx_lcdc_init(0x44000000,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2X=
X_PIC_LCD));
>
> =C2=A0 =C2=A0 s->cm_base =3D 0x41300000;
> =C2=A0 =C2=A0 s->cm_regs[CCCR >> 2] =3D 0x02000210; =C2=A0 =C2=A0 =C2=A0 =
=C2=A0/* 416.0 MHz */
> @@ -2282,13 +2304,13 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
> =C2=A0 =C2=A0 for (i =3D 0; pxa255_ssp[i].io_base; i ++) {
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 DeviceState *dev;
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev =3D sysbus_create_simple("pxa2xx-ssp", px=
a255_ssp[i].io_base,
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->pic[pxa255_ssp[i].irqn]=
);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_get_gpio_in(s->pic, pxa255_ssp[i].i=
rqn));
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->ssp[i] =3D (SSIBus *)qdev_get_child_bus(de=
v, "ssi");
> =C2=A0 =C2=A0 }
>
> =C2=A0 =C2=A0 if (usb_enabled) {
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_create_simple("sysbus-ohci", 0x4c00000=
0,
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->pic[PXA2XX_PIC_USBH1]);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
> =C2=A0 =C2=A0 }
>
> =C2=A0 =C2=A0 s->pcmcia[0] =3D pxa2xx_pcmcia_init(0x20000000);
> @@ -2302,10 +2324,14 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
> =C2=A0 =C2=A0 register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 pxa=
2xx_rtc_load, s);
>
> - =C2=A0 =C2=A0s->i2c[0] =3D pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PI=
C_I2C], 0xffff);
> - =C2=A0 =C2=A0s->i2c[1] =3D pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PI=
C_PWRI2C], 0xff);
> + =C2=A0 =C2=A0s->i2c[0] =3D pxa2xx_i2c_init(0x40301600,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2X=
X_PIC_I2C), 0xffff);
> + =C2=A0 =C2=A0s->i2c[1] =3D pxa2xx_i2c_init(0x40f00100,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2X=
X_PIC_PWRI2C), 0xff);
>
> - =C2=A0 =C2=A0s->i2s =3D pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I=
2S], s->dma);
> + =C2=A0 =C2=A0s->i2s =3D pxa2xx_i2s_init(0x40400000,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(s->pic, PXA2X=
X_PIC_I2S),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->dma);
>
> =C2=A0 =C2=A0 /* GPIO1 resets the processor */
> =C2=A0 =C2=A0 /* The handler can be overridden by board-specific code */
> diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
> index 789965d..16a8865 100644
> --- a/hw/pxa2xx_gpio.c
> +++ b/hw/pxa2xx_gpio.c
> @@ -253,7 +253,7 @@ static CPUWriteMemoryFunc * const pxa2xx_gpio_writefn=
[] =3D {
> =C2=A0};
>
> =C2=A0DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0CPUState *env, q=
emu_irq *pic, int lines)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0CPUState *env, D=
eviceState *pic, int lines)
> =C2=A0{
> =C2=A0 =C2=A0 DeviceState *dev;
>
> @@ -263,9 +263,12 @@ DeviceState *pxa2xx_gpio_init(target_phys_addr_t bas=
e,
> =C2=A0 =C2=A0 qdev_init_nofail(dev);
>
> =C2=A0 =C2=A0 sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
> - =C2=A0 =C2=A0sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[PXA2XX_PI=
C_GPIO_0]);
> - =C2=A0 =C2=A0sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[PXA2XX_PI=
C_GPIO_1]);
> - =C2=A0 =C2=A0sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[PXA2XX_PI=
C_GPIO_X]);
> + =C2=A0 =C2=A0sysbus_connect_irq(sysbus_from_qdev(dev), 0,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(pic, PXA2XX_P=
IC_GPIO_0));
> + =C2=A0 =C2=A0sysbus_connect_irq(sysbus_from_qdev(dev), 1,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(pic, PXA2XX_P=
IC_GPIO_1));
> + =C2=A0 =C2=A0sysbus_connect_irq(sysbus_from_qdev(dev), 2,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(pic, PXA2XX_P=
IC_GPIO_X));
>
> =C2=A0 =C2=A0 return dev;
> =C2=A0}
> diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c
> index a36da23..1053b92 100644
> --- a/hw/pxa2xx_pic.c
> +++ b/hw/pxa2xx_pic.c
> @@ -10,6 +10,8 @@
>
> =C2=A0#include "hw.h"
> =C2=A0#include "pxa.h"
> +#include "arm-misc.h"
> +#include "sysbus.h"
>
> =C2=A0#define ICIP =C2=A0 0x00 =C2=A0 =C2=A0/* Interrupt Controller IRQ P=
ending register */
> =C2=A0#define ICMR =C2=A0 0x04 =C2=A0 =C2=A0/* Interrupt Controller Mask =
register */
> @@ -31,7 +33,10 @@
> =C2=A0#define PXA2XX_PIC_SRCS =C2=A0 =C2=A0 =C2=A0 =C2=A040
>
> =C2=A0typedef struct {
> - =C2=A0 =C2=A0CPUState *cpu_env;
> + =C2=A0 =C2=A0SysBusDevice busdev;
> + =C2=A0 =C2=A0qemu_irq hard_irq;
> + =C2=A0 =C2=A0qemu_irq fiq_irq;
> + =C2=A0 =C2=A0qemu_irq wake_irq;
> =C2=A0 =C2=A0 uint32_t int_enabled[2];
> =C2=A0 =C2=A0 uint32_t int_pending[2];
> =C2=A0 =C2=A0 uint32_t is_fiq[2];
> @@ -44,25 +49,18 @@ static void pxa2xx_pic_update(void *opaque)
> =C2=A0 =C2=A0 uint32_t mask[2];
> =C2=A0 =C2=A0 PXA2xxPICState *s =3D (PXA2xxPICState *) opaque;
>
> - =C2=A0 =C2=A0if (s->cpu_env->halted) {
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0mask[0] =3D s->int_pending[0] & (s->int_enab=
led[0] | s->int_idle);
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0mask[1] =3D s->int_pending[1] & (s->int_enab=
led[1] | s->int_idle);
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0if (mask[0] || mask[1])
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_interrupt(s->cpu_env, CPU_=
INTERRUPT_EXITTB);
> - =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0mask[0] =3D s->int_pending[0] & (s->int_enabled[0] | s->in=
t_idle);
> + =C2=A0 =C2=A0mask[1] =3D s->int_pending[1] & (s->int_enabled[1] | s->in=
t_idle);
> + =C2=A0 =C2=A0qemu_set_irq(s->wake_irq, mask[0] || mask[1]);
>
> =C2=A0 =C2=A0 mask[0] =3D s->int_pending[0] & s->int_enabled[0];
> =C2=A0 =C2=A0 mask[1] =3D s->int_pending[1] & s->int_enabled[1];
>
> - =C2=A0 =C2=A0if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1]))
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ)=
;
> - =C2=A0 =C2=A0else
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_reset_interrupt(s->cpu_env, CPU_INTERRUP=
T_FIQ);
> + =C2=A0 =C2=A0qemu_set_irq(s->fiq_irq,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0((mask[0] & s->is_fiq[0]) || (=
mask[1] & s->is_fiq[1])));
>
> - =C2=A0 =C2=A0if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])=
)
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD=
);
> - =C2=A0 =C2=A0else
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_reset_interrupt(s->cpu_env, CPU_INTERRUP=
T_HARD);
> + =C2=A0 =C2=A0qemu_set_irq(s->hard_irq,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0((mask[0] & ~s->is_fiq[0]) || =
(mask[1] & ~s->is_fiq[1])));
> =C2=A0}
>
> =C2=A0/* Note: Here level means state of the signal on a pin, not
> @@ -241,53 +239,33 @@ static CPUWriteMemoryFunc * const pxa2xx_pic_writef=
n[] =3D {
> =C2=A0 =C2=A0 pxa2xx_pic_mem_write,
> =C2=A0};
>
> -static void pxa2xx_pic_save(QEMUFile *f, void *opaque)
> +static int pxa2xx_pic_post_load(void *opaque, int version_id)
> =C2=A0{
> - =C2=A0 =C2=A0PXA2xxPICState *s =3D (PXA2xxPICState *) opaque;
> - =C2=A0 =C2=A0int i;
> -
> - =C2=A0 =C2=A0for (i =3D 0; i < 2; i ++)
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_put_be32s(f, &s->int_enabled[i]);
> - =C2=A0 =C2=A0for (i =3D 0; i < 2; i ++)
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_put_be32s(f, &s->int_pending[i]);
> - =C2=A0 =C2=A0for (i =3D 0; i < 2; i ++)
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_put_be32s(f, &s->is_fiq[i]);
> - =C2=A0 =C2=A0qemu_put_be32s(f, &s->int_idle);
> - =C2=A0 =C2=A0for (i =3D 0; i < PXA2XX_PIC_SRCS; i ++)
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_put_be32s(f, &s->priority[i]);
> + =C2=A0 =C2=A0pxa2xx_pic_update(opaque);
> + =C2=A0 =C2=A0return 0;
> =C2=A0}
>
> -static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id)
> +DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq *arm_pic)
> =C2=A0{
> - =C2=A0 =C2=A0PXA2xxPICState *s =3D (PXA2xxPICState *) opaque;
> - =C2=A0 =C2=A0int i;
> -
> - =C2=A0 =C2=A0for (i =3D 0; i < 2; i ++)
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_get_be32s(f, &s->int_enabled[i]);
> - =C2=A0 =C2=A0for (i =3D 0; i < 2; i ++)
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_get_be32s(f, &s->int_pending[i]);
> - =C2=A0 =C2=A0for (i =3D 0; i < 2; i ++)
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_get_be32s(f, &s->is_fiq[i]);
> - =C2=A0 =C2=A0qemu_get_be32s(f, &s->int_idle);
> - =C2=A0 =C2=A0for (i =3D 0; i < PXA2XX_PIC_SRCS; i ++)
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_get_be32s(f, &s->priority[i]);
> + =C2=A0 =C2=A0DeviceState *dev;
>
> - =C2=A0 =C2=A0pxa2xx_pic_update(opaque);
> - =C2=A0 =C2=A0return 0;
> + =C2=A0 =C2=A0dev =3D sysbus_create_varargs("pxa2xx_pic", base,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0arm_pic[ARM_PIC_CPU_IRQ],
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0arm_pic[ARM_PIC_CPU_FIQ],
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0arm_pic[ARM_PIC_CPU_WAKE],
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0NULL);
> +
> + =C2=A0 =C2=A0/* Enable IC coprocessor access. =C2=A0*/
> + =C2=A0 =C2=A0cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_c=
p_write, dev);

I changed the last parameter to "s" as passing dev here was hacky.

Cheers