[U-Boot] [PATCH V4] mpc83xx:fix pcie configuration space read/write

[Leo Liu <liucai.lfn@gmail.com>]

Hi:

2011/1/19 Leo Liu <liucai.lfn@gmail.com>:
> This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is
> connected with switch or we use both of the two pcie controller.
>
> Signed-off-by: Leo Liu <liucai.lfn@gmail.com>
> ---
> Changes for V2:
> ? ? ? ?- Avoid line wrap in the patch
> Changes for V3
> ? ? ? ?- Add space between ) and {
> Changes for V4
> ? ? ? ?- Add and use priv_data pointer in pci_controller to save the
> ? ? ? ? ?mpc83xx pcie private data
>
> ?arch/powerpc/cpu/mpc83xx/pcie.c | ? 20 +++++++++++++++++++-
> ?include/pci.h ? ? ? ? ? ? ? ? ? | ? ?2 ++
> ?2 files changed, 21 insertions(+), 1 deletions(-)
>
> diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
> index 46a706d..ee94a8b 100644
> --- a/arch/powerpc/cpu/mpc83xx/pcie.c
> +++ b/arch/powerpc/cpu/mpc83xx/pcie.c
> @@ -30,6 +30,21 @@ DECLARE_GLOBAL_DATA_PTR;
>
> ?#define PCIE_MAX_BUSES 2
>
> +/*private structure for mpc83xx pcie hose*/
> +static struct mpc83xx_pcie_priv {
> + ? ? ? u8 index;
> +} pcie_priv[PCIE_MAX_BUSES] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? /*pcie controller 1*/
> + ? ? ? ? ? ? ? .index = 0,
> + ? ? ? },
> + ? ? ? {
> + ? ? ? ? ? ? ? /*pcie controller 2*/
> + ? ? ? ? ? ? ? .index = 1,
> + ? ? ? },
> +};
> +
> +
> ?static struct {
> ? ? ? ?u32 base;
> ? ? ? ?u32 size;
> @@ -52,7 +67,8 @@ static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
> ?{
> ? ? ? ?int bus = PCI_BUS(dev) - hose->first_busno;
> ? ? ? ?immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
> - ? ? ? pex83xx_t *pex = &immr->pciexp[bus];
> + ? ? ? struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
> + ? ? ? pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
> ? ? ? ?struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
> ? ? ? ?u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
> ? ? ? ?u32 dev_base = bus << 24 | devfn << 16;
> @@ -142,6 +158,8 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
>
> ? ? ? ?hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
>
> + ? ? ? hose->priv_data = &pcie_priv[bus];
> +
> ? ? ? ?pci_set_ops(hose,
> ? ? ? ? ? ? ? ? ? ? ? ?pcie_read_config_byte,
> ? ? ? ? ? ? ? ? ? ? ? ?pcie_read_config_word,
> diff --git a/include/pci.h b/include/pci.h
> index c456006..8b3bdbb 100644
> --- a/include/pci.h
> +++ b/include/pci.h
> @@ -420,6 +420,8 @@ struct pci_controller {
> ? ? ? ?/* Used by ppc405 autoconfig*/
> ? ? ? ?struct pci_region *pci_fb;
> ? ? ? ?int current_busno;
> +
> + ? ? ? void *priv_data;
> ?};
>
> ?extern __inline__ void pci_set_ops(struct pci_controller *hose,
> --
> 1.7.3.1.msysgit.0
>
>

Will this patch be applied in the next release?
This patch is not for performence improvement, it is a critical bug
fix. Without this, the mpc83xx pcie can not work correctly.

Thanks