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Date: Tue, 8 Feb 2011 15:59:46 +0000
Message-ID: <AANLkTim_TSvJVnyHFzmOiu52bmMu3_d=4Uz690S15o=1@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH v3] Softfloat: Add support to softfloat to
	return floatxx_default_nan when,
	the corresponding target status flag is set.
From: Peter Maydell <peter.maydell@linaro.org>
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To: Christophe Lyon <christophe.lyon@st.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>

On 7 February 2011 17:00, Christophe Lyon <christophe.lyon@st.com> wrote:
>
> Some CPUs have a status flag imposing to return floatxx_default_nan
> whatever the input value, when converting from one FP format to
> another. Implement this, using the already existing default_nan_mode
> status flag (currently used on ARM and SH4 at the moment).
>
> Signed-off-by: Christophe Lyon <christophe.lyon@st.com>

Your subject is a bit long, which can make it wrap annoyingly in git logs.
I'd suggest something like:

=3D=3D=3Dbegin=3D=3D=3D
softfloat: Honour default_nan_mode for float-to-float conversions

Honour the default_nan_mode flag when doing conversions between
different floating point formats, as well as when returning a NaN from
a two-operand floating point function. This corrects the behaviour
of float<->double conversions on both ARM and SH4.
=3D=3D=3Dendit=3D=3D=3D

> +/*----------------------------------------------------------------------=
------
> +| The pattern for a default generated haft-precision NaN.
> +*-----------------------------------------------------------------------=
-----*/

"half-precision".

> @@ -2767,11 +2767,7 @@ bits16 float32_to_float16( float32 a, flag ieee ST=
ATUS_PARAM)
> =C2=A0 =C2=A0 aExp =3D extractFloat32Exp( a );
> =C2=A0 =C2=A0 aSign =3D extractFloat32Sign( a );
> =C2=A0 =C2=A0 if ( aExp =3D=3D 0xFF ) {
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0if (aSig) {
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Make sure correct exception=
s are raised. =C2=A0*/
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0float32ToCommonNaN(a STATUS_VA=
R);
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0aSig |=3D 0x00400000;
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0if ( aSig ) return commonNaNToFloat16( float=
32ToCommonNaN( a STATUS_VAR ) STATUS_VAR );
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 return packFloat16(aSign, 0x1f, aSig >> 13);
> =C2=A0 =C2=A0 }
> =C2=A0 =C2=A0 if (aExp =3D=3D 0 && aSign =3D=3D 0) {

This is float32_to_float16() but it looks like you've missed
float16_to_float32() ?

Otherwise, looks good, and I can confirm that it fixes
behaviour of VCVT.F32.F64 and VCVT.F64.F32 when
the FPSCR.DN bit is set.

-- PMM