From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=55689 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OLBbq-0001ZL-9V for qemu-devel@nongnu.org; Sun, 06 Jun 2010 04:54:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OLBbk-0002Uc-GC for qemu-devel@nongnu.org; Sun, 06 Jun 2010 04:53:29 -0400 Received: from mail-pz0-f199.google.com ([209.85.222.199]:42916) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OLBbk-0002UL-1n for qemu-devel@nongnu.org; Sun, 06 Jun 2010 04:53:28 -0400 Received: by pzk37 with SMTP id 37so976140pzk.27 for ; Sun, 06 Jun 2010 01:53:27 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <29c348b1e7c8c88759914a55015d72ee8c02fc1a.1275811861.git.jan.kiszka@web.de> References: <29c348b1e7c8c88759914a55015d72ee8c02fc1a.1275811861.git.jan.kiszka@web.de> From: Blue Swirl Date: Sun, 6 Jun 2010 08:53:07 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] Re: [PATCH 11/16] hpet/rtc: Rework RTC IRQ replacement by HPET List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jan Kiszka Cc: Jan Kiszka , Paul Brook , qemu-devel@nongnu.org, Gleb Natapov , Juan Quintela On Sun, Jun 6, 2010 at 8:11 AM, Jan Kiszka wrote: > From: Jan Kiszka > > Allow the intercept the RTC IRQ for the HPET legacy mode. Then push > routing to IRQ8 completely into the HPET. This allows to turn > hpet_in_legacy_mode() into a private function. Furthermore, this stops > the RTC from clearing IRQ8 even if the HPET is in control. > > This patch comes with a side effect: The RTC timers will no longer be > stoppend when there is no IRQ consumer, possibly causing a minor > performance degration. But as the guest may want to redirect the RTC to > the SCI in that mode, it should normally disable unused IRQ source > anyway. > > Signed-off-by: Jan Kiszka > --- > =C2=A0hw/hpet.c =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 42 ++++++++++++++++++= +++++++++++++++++------- > =C2=A0hw/hpet_emul.h =C2=A0 | =C2=A0 =C2=A04 ---- > =C2=A0hw/mc146818rtc.c | =C2=A0 54 +++++++++++++++-----------------------= ---------------- > =C2=A0hw/mc146818rtc.h | =C2=A0 =C2=A04 +++- > =C2=A0hw/mips_jazz.c =C2=A0 | =C2=A0 =C2=A02 +- > =C2=A0hw/mips_malta.c =C2=A0| =C2=A0 =C2=A02 +- > =C2=A0hw/mips_r4k.c =C2=A0 =C2=A0| =C2=A0 =C2=A02 +- > =C2=A0hw/pc.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 14 ++++++++-----= - > =C2=A0hw/ppc_prep.c =C2=A0 =C2=A0| =C2=A0 =C2=A02 +- > =C2=A09 files changed, 65 insertions(+), 61 deletions(-) > > diff --git a/hw/hpet.c b/hw/hpet.c > index 041dd84..d26cad5 100644 > --- a/hw/hpet.c > +++ b/hw/hpet.c > @@ -30,6 +30,7 @@ > =C2=A0#include "qemu-timer.h" > =C2=A0#include "hpet_emul.h" > =C2=A0#include "sysbus.h" > +#include "mc146818rtc.h" > > =C2=A0//#define HPET_DEBUG > =C2=A0#ifdef HPET_DEBUG > @@ -58,6 +59,7 @@ typedef struct HPETState { > =C2=A0 =C2=A0 SysBusDevice busdev; > =C2=A0 =C2=A0 uint64_t hpet_offset; > =C2=A0 =C2=A0 qemu_irq irqs[HPET_NUM_IRQ_ROUTES]; > + =C2=A0 =C2=A0uint8_t rtc_irq_level; > =C2=A0 =C2=A0 HPETTimer timer[HPET_NUM_TIMERS]; > > =C2=A0 =C2=A0 /* Memory-mapped, software visible registers */ > @@ -69,12 +71,9 @@ typedef struct HPETState { > > =C2=A0static HPETState *hpet_statep; > > -uint32_t hpet_in_legacy_mode(void) > +static uint32_t hpet_in_legacy_mode(HPETState *s) > =C2=A0{ > - =C2=A0 =C2=A0if (!hpet_statep) { > - =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0; > - =C2=A0 =C2=A0} > - =C2=A0 =C2=A0return hpet_statep->config & HPET_CFG_LEGACY; > + =C2=A0 =C2=A0return s->config & HPET_CFG_LEGACY; > =C2=A0} > > =C2=A0static uint32_t timer_int_route(struct HPETTimer *timer) > @@ -166,12 +165,12 @@ static void update_irq(struct HPETTimer *timer) > =C2=A0{ > =C2=A0 =C2=A0 int route; > > - =C2=A0 =C2=A0if (timer->tn <=3D 1 && hpet_in_legacy_mode()) { > + =C2=A0 =C2=A0if (timer->tn <=3D 1 && hpet_in_legacy_mode(timer->state))= { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* if LegacyReplacementRoute bit is set, HPET= specification requires > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* timer0 be routed to IRQ0 in NON-APIC = or IRQ2 in the I/O APIC, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* timer1 be routed to IRQ8 in NON-APIC = or IRQ8 in the I/O APIC. > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/ > - =C2=A0 =C2=A0 =C2=A0 =C2=A0route =3D (timer->tn =3D=3D 0) ? 0 : 8; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0route =3D (timer->tn =3D=3D 0) ? 0 : RTC_ISA= _IRQ; > =C2=A0 =C2=A0 } else { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 route =3D timer_int_route(timer); > =C2=A0 =C2=A0 } > @@ -515,8 +514,10 @@ static void hpet_ram_writel(void *opaque, target_phy= s_addr_t addr, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* i8254 and RTC are disabled w= hen HPET is in legacy mode */ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (activating_bit(old_val, new= _val, HPET_CFG_LEGACY)) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 hpet_pit_disable(= ); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_lower(s= ->irqs[RTC_ISA_IRQ]); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (deactivating_bit(old= _val, new_val, HPET_CFG_LEGACY)) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 hpet_pit_enable()= ; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_set_irq(s->= irqs[RTC_ISA_IRQ], s->rtc_irq_level); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 case HPET_CFG + 4: > @@ -607,6 +608,30 @@ static void hpet_reset(DeviceState *d) > =C2=A0 =C2=A0 count =3D 1; > =C2=A0} > > +static void hpet_rtc_delivery_cb(qemu_irq irq, void *opaque, int n, int = level, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int result) > +{ > + =C2=A0 =C2=A0qemu_irq orig_irq =3D opaque; > + > + =C2=A0 =C2=A0qemu_irq_fire_delivery_cb(orig_irq, level, result); > +} > + > +static void hpet_handle_rtc_irq(qemu_irq irq, void *opaque, int n, int l= evel) > +{ > + =C2=A0 =C2=A0HPETState *s =3D FROM_SYSBUS(HPETState, opaque); > + =C2=A0 =C2=A0IRQMsg msg =3D { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0.delivery_cb =3D hpet_rtc_delivery_cb, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0.delivery_opaque =3D irq, > + =C2=A0 =C2=A0}; > + > + =C2=A0 =C2=A0s->rtc_irq_level =3D level; > + =C2=A0 =C2=A0if (hpet_in_legacy_mode(s)) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_fire_delivery_cb(irq, level, QEMU_I= RQ_MASKED); > + =C2=A0 =C2=A0} else { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_set_irq_msg(s->irqs[RTC_ISA_IRQ], level= , &msg); This is the problem with passing around stack allocated objects: after this function finishes, s->irqs[RTC_ISA_IRQ].msg is a dangling pointer to some stack space. > + =C2=A0 =C2=A0} > +} > + > =C2=A0static int hpet_init(SysBusDevice *dev) > =C2=A0{ > =C2=A0 =C2=A0 HPETState *s =3D FROM_SYSBUS(HPETState, dev); > @@ -625,6 +650,9 @@ static int hpet_init(SysBusDevice *dev) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 timer->state =3D s; > =C2=A0 =C2=A0 } > > + =C2=A0 =C2=A0isa_reserve_irq(RTC_ISA_IRQ); > + =C2=A0 =C2=A0qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1); > + > =C2=A0 =C2=A0 /* HPET Area */ > =C2=A0 =C2=A0 iomemtype =3D cpu_register_io_memory(hpet_ram_read, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hpet_ram_= write, s); > diff --git a/hw/hpet_emul.h b/hw/hpet_emul.h > index 785f850..9c268cc 100644 > --- a/hw/hpet_emul.h > +++ b/hw/hpet_emul.h > @@ -47,8 +47,4 @@ > =C2=A0#define HPET_TN_INT_ROUTE_CAP_SHIFT 32 > =C2=A0#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U > > -#if defined TARGET_I386 > -extern uint32_t hpet_in_legacy_mode(void); > -#endif > - > =C2=A0#endif > diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c > index cbb98a4..ac82810 100644 > --- a/hw/mc146818rtc.c > +++ b/hw/mc146818rtc.c > @@ -26,7 +26,6 @@ > =C2=A0#include "sysemu.h" > =C2=A0#include "pc.h" > =C2=A0#include "isa.h" > -#include "hpet_emul.h" > =C2=A0#include "mc146818rtc.h" > > =C2=A0//#define DEBUG_CMOS > @@ -100,24 +99,6 @@ typedef struct RTCState { > =C2=A0 =C2=A0 QEMUTimer *second_timer2; > =C2=A0} RTCState; > > -static void rtc_irq_raise(RTCState *s, IRQMsg *msg) > -{ > - =C2=A0 =C2=A0/* When HPET is operating in legacy mode, RTC interrupts a= re disabled > - =C2=A0 =C2=A0 * We block qemu_irq_raise, but not qemu_irq_lower, in cas= e legacy > - =C2=A0 =C2=A0 * mode is established while interrupt is raised. We want = it to > - =C2=A0 =C2=A0 * be lowered in any case > - =C2=A0 =C2=A0 */ > -#if defined TARGET_I386 > - =C2=A0 =C2=A0if (hpet_in_legacy_mode()) { > - =C2=A0 =C2=A0 =C2=A0 =C2=A0if (msg) { > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0msg->delivery_cb(s->irq, s, -1= , -1, QEMU_IRQ_MASKED); > - =C2=A0 =C2=A0 =C2=A0 =C2=A0} > - =C2=A0 =C2=A0 =C2=A0 =C2=A0return; > - =C2=A0 =C2=A0} > -#endif > - =C2=A0 =C2=A0qemu_irq_raise_msg(s->irq, msg); > -} > - > =C2=A0static void rtc_set_time(RTCState *s); > =C2=A0static void rtc_copy_date(RTCState *s); > > @@ -169,7 +150,7 @@ static void rtc_coalesced_timer(void *opaque) > =C2=A0 =C2=A0 if (s->irq_coalesced !=3D 0) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->cmos_data[RTC_REG_C] |=3D 0xc0; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 DPRINTF_C("cmos: injecting from timer\n"); > - =C2=A0 =C2=A0 =C2=A0 =C2=A0rtc_irq_raise(s, &msg); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_raise_msg(s->irq, &msg); > =C2=A0 =C2=A0 } > > =C2=A0 =C2=A0 rtc_coalesced_timer_update(s); > @@ -180,19 +161,10 @@ static void rtc_timer_update(RTCState *s, int64_t c= urrent_time) > =C2=A0{ > =C2=A0 =C2=A0 int period_code, period; > =C2=A0 =C2=A0 int64_t cur_clock, next_irq_clock; > - =C2=A0 =C2=A0int enable_pie; > > =C2=A0 =C2=A0 period_code =3D s->cmos_data[RTC_REG_A] & 0x0f; > -#if defined TARGET_I386 > - =C2=A0 =C2=A0/* disable periodic timer if hpet is in legacy mode, since= interrupts are > - =C2=A0 =C2=A0 * disabled anyway. > - =C2=A0 =C2=A0 */ > - =C2=A0 =C2=A0enable_pie =3D !hpet_in_legacy_mode(); > -#else > - =C2=A0 =C2=A0enable_pie =3D 1; > -#endif > =C2=A0 =C2=A0 if (period_code !=3D 0 > - =C2=A0 =C2=A0 =C2=A0 =C2=A0&& (((s->cmos_data[RTC_REG_B] & REG_B_PIE) &= & enable_pie) > + =C2=A0 =C2=A0 =C2=A0 =C2=A0&& ((s->cmos_data[RTC_REG_B] & REG_B_PIE) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 || ((s->cmos_data[RTC_REG_B] & = REG_B_SQWE) && s->sqw_irq))) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (period_code <=3D 2) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 period_code +=3D 7; > @@ -236,10 +208,10 @@ static void rtc_periodic_timer(void *opaque) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (s->irq_reinject_on_ack_coun= t >=3D RTC_REINJECT_ON_ACK_COUNT) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->irq_reinject_o= n_ack_count =3D 0; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rtc_irq_raise(s, &msg); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_raise_msg(s->irq, &ms= g); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 } else > =C2=A0#endif > - =C2=A0 =C2=A0 =C2=A0 =C2=A0rtc_irq_raise(s, NULL); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_raise(s->irq); > =C2=A0 =C2=A0 } > =C2=A0 =C2=A0 if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Not square wave at all but we don't want 2= 048Hz interrupts! > @@ -468,15 +440,15 @@ static void rtc_update_second2(void *opaque) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->cmos_data[RTC_HOURS_AL= ARM] =3D=3D s->current_tm.tm_hour)) { > > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->cmos_data[RTC_REG_C] |=3D 0x= a0; > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rtc_irq_raise(s, NULL); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_raise(s->irq); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > =C2=A0 =C2=A0 } > > =C2=A0 =C2=A0 /* update ended interrupt */ > =C2=A0 =C2=A0 s->cmos_data[RTC_REG_C] |=3D REG_C_UF; > =C2=A0 =C2=A0 if (s->cmos_data[RTC_REG_B] & REG_B_UIE) { > - =C2=A0 =C2=A0 =C2=A0s->cmos_data[RTC_REG_C] |=3D REG_C_IRQF; > - =C2=A0 =C2=A0 =C2=A0rtc_irq_raise(s, NULL); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->cmos_data[RTC_REG_C] |=3D REG_C_IRQF; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_raise(s->irq); > =C2=A0 =C2=A0 } > > =C2=A0 =C2=A0 /* clear update in progress bit */ > @@ -629,9 +601,6 @@ static int rtc_initfn(ISADevice *dev) > =C2=A0{ > =C2=A0 =C2=A0 RTCState *s =3D DO_UPCAST(RTCState, dev, dev); > =C2=A0 =C2=A0 int base =3D 0x70; > - =C2=A0 =C2=A0int isairq =3D 8; > - > - =C2=A0 =C2=A0isa_init_irq(dev, &s->irq, isairq); > > =C2=A0 =C2=A0 s->cmos_data[RTC_REG_A] =3D 0x26; > =C2=A0 =C2=A0 s->cmos_data[RTC_REG_B] =3D 0x02; > @@ -661,13 +630,20 @@ static int rtc_initfn(ISADevice *dev) > =C2=A0 =C2=A0 return 0; > =C2=A0} > > -ISADevice *rtc_init(int base_year) > +ISADevice *rtc_init(int base_year, qemu_irq intercept_irq) > =C2=A0{ > =C2=A0 =C2=A0 ISADevice *dev; > + =C2=A0 =C2=A0RTCState *s; > > =C2=A0 =C2=A0 dev =3D isa_create("mc146818rtc"); > + =C2=A0 =C2=A0s =3D DO_UPCAST(RTCState, dev, dev); > =C2=A0 =C2=A0 qdev_prop_set_int32(&dev->qdev, "base_year", base_year); > =C2=A0 =C2=A0 qdev_init_nofail(&dev->qdev); > + =C2=A0 =C2=A0if (intercept_irq) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->irq =3D intercept_irq; > + =C2=A0 =C2=A0} else { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0isa_init_irq(dev, &s->irq, RTC_ISA_IRQ); > + =C2=A0 =C2=A0} > =C2=A0 =C2=A0 return dev; > =C2=A0} > > diff --git a/hw/mc146818rtc.h b/hw/mc146818rtc.h > index 6f46a68..575968c 100644 > --- a/hw/mc146818rtc.h > +++ b/hw/mc146818rtc.h > @@ -3,7 +3,9 @@ > > =C2=A0#include "isa.h" > > -ISADevice *rtc_init(int base_year); > +#define RTC_ISA_IRQ 8 > + > +ISADevice *rtc_init(int base_year, qemu_irq intercept_irq); > =C2=A0void rtc_set_memory(ISADevice *dev, int addr, int val); > =C2=A0void rtc_set_date(ISADevice *dev, const struct tm *tm); > > diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c > index da1bf6e..5e52f59 100644 > --- a/hw/mips_jazz.c > +++ b/hw/mips_jazz.c > @@ -259,7 +259,7 @@ void mips_jazz_init (ram_addr_t ram_size, > =C2=A0 =C2=A0 fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds); > > =C2=A0 =C2=A0 /* Real time clock */ > - =C2=A0 =C2=A0rtc_init(1980); > + =C2=A0 =C2=A0rtc_init(1980, NULL); > =C2=A0 =C2=A0 s_rtc =3D cpu_register_io_memory(rtc_read, rtc_write, NULL)= ; > =C2=A0 =C2=A0 cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc)= ; > > diff --git a/hw/mips_malta.c b/hw/mips_malta.c > index bd86636..438e4e3 100644 > --- a/hw/mips_malta.c > +++ b/hw/mips_malta.c > @@ -959,7 +959,7 @@ void mips_malta_init (ram_addr_t ram_size, > =C2=A0 =C2=A0 /* Super I/O */ > =C2=A0 =C2=A0 isa_dev =3D isa_create_simple("i8042"); > > - =C2=A0 =C2=A0rtc_state =3D rtc_init(2000); > + =C2=A0 =C2=A0rtc_state =3D rtc_init(2000, NULL); > =C2=A0 =C2=A0 serial_isa_init(0, serial_hds[0]); > =C2=A0 =C2=A0 serial_isa_init(1, serial_hds[1]); > =C2=A0 =C2=A0 if (parallel_hds[0]) > diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c > index f1fcfcd..5a96dea 100644 > --- a/hw/mips_r4k.c > +++ b/hw/mips_r4k.c > @@ -267,7 +267,7 @@ void mips_r4k_init (ram_addr_t ram_size, > =C2=A0 =C2=A0 isa_bus_new(NULL); > =C2=A0 =C2=A0 isa_bus_irqs(i8259); > > - =C2=A0 =C2=A0rtc_state =3D rtc_init(2000); > + =C2=A0 =C2=A0rtc_state =3D rtc_init(2000, NULL); > > =C2=A0 =C2=A0 /* Register 64 KB of ISA IO space at 0x14000000 */ > =C2=A0#ifdef TARGET_WORDS_BIGENDIAN > diff --git a/hw/pc.c b/hw/pc.c > index 6129e59..8460303 100644 > --- a/hw/pc.c > +++ b/hw/pc.c > @@ -965,6 +965,7 @@ void pc_basic_device_init(qemu_irq *isa_irq, > =C2=A0 =C2=A0 int i; > =C2=A0 =C2=A0 DriveInfo *fd[MAX_FD]; > =C2=A0 =C2=A0 PITState *pit; > + =C2=A0 =C2=A0qemu_irq rtc_irq =3D NULL; > =C2=A0 =C2=A0 qemu_irq *a20_line; > =C2=A0 =C2=A0 ISADevice *i8042; > =C2=A0 =C2=A0 qemu_irq *cpu_exit_irq; > @@ -973,19 +974,20 @@ void pc_basic_device_init(qemu_irq *isa_irq, > > =C2=A0 =C2=A0 register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); > > - =C2=A0 =C2=A0*rtc_state =3D rtc_init(2000); > - > - =C2=A0 =C2=A0qemu_register_boot_set(pc_boot_set, *rtc_state); > - > - =C2=A0 =C2=A0pit =3D pit_init(0x40, isa_reserve_irq(0)); > - =C2=A0 =C2=A0pcspk_init(pit); > =C2=A0 =C2=A0 if (!no_hpet) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 DeviceState *hpet =3D sysbus_create_simple("h= pet", HPET_BASE, NULL); > > =C2=A0 =C2=A0 =C2=A0 =C2=A0 for (i =3D 0; i < 24; i++) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_connect_irq(sysbus_from_= qdev(hpet), i, isa_irq[i]); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > + =C2=A0 =C2=A0 =C2=A0 =C2=A0rtc_irq =3D qdev_get_gpio_in(hpet, 0); > =C2=A0 =C2=A0 } > + =C2=A0 =C2=A0*rtc_state =3D rtc_init(2000, rtc_irq); > + > + =C2=A0 =C2=A0qemu_register_boot_set(pc_boot_set, *rtc_state); > + > + =C2=A0 =C2=A0pit =3D pit_init(0x40, isa_reserve_irq(0)); > + =C2=A0 =C2=A0pcspk_init(pit); > > =C2=A0 =C2=A0 for(i =3D 0; i < MAX_SERIAL_PORTS; i++) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (serial_hds[i]) { > diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c > index fd1ca86..f44a144 100644 > --- a/hw/ppc_prep.c > +++ b/hw/ppc_prep.c > @@ -696,7 +696,7 @@ static void ppc_prep_init (ram_addr_t ram_size, > =C2=A0 =C2=A0 pci_vga_init(pci_bus, 0, 0); > =C2=A0 =C2=A0 // =C2=A0 =C2=A0openpic =3D openpic_init(0x00000000, 0xF000= 0000, 1); > =C2=A0 =C2=A0 // =C2=A0 =C2=A0pit =3D pit_init(0x40, i8259[0]); > - =C2=A0 =C2=A0rtc_init(2000); > + =C2=A0 =C2=A0rtc_init(2000, NULL); > > =C2=A0 =C2=A0 if (serial_hds[0]) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 serial_isa_init(0, serial_hds[0]); > -- > 1.6.0.2 > >