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Date: Mon, 22 Nov 2010 21:01:59 +0800
Message-ID: <AANLkTinbsQzDKvkZGkkc=pHuKvSyAXxdq8jC51jpjAd_@mail.gmail.com>
Subject: Re: [PATCH 3/4] perf-events: Add support for supplementary event
 registers v3
From: Lin Ming <lin@ming.vg>
To: Stephane Eranian <eranian@google.com>
Cc: Andi Kleen <andi@firstfloor.org>, a.p.zijlstra@chello.nl,
        linux-kernel@vger.kernel.org, x86@kernel.org,
        Andi Kleen <ak@linux.intel.com>
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On Mon, Nov 22, 2010 at 8:47 PM, Stephane Eranian <eranian@google.com> wrote:
> On Mon, Nov 22, 2010 at 1:23 PM, Lin Ming <lin@ming.vg> wrote:
>> On Thu, Nov 18, 2010 at 6:47 PM, Andi Kleen <andi@firstfloor.org> wrote:
>>> From: Andi Kleen <ak@linux.intel.com>
>>>
>>> Intel Nehalem/Westmere have a special OFFCORE_RESPONSE event
>>> that can be used to monitor any offcore accesses from a core.
>>> This is a very useful event for various tunings, and it's
>>> also needed to implement the generic LLC-* events correctly.
>>>
>>> Unfortunately this event requires programming a mask in a separate
>>> register. And worse this separate register is per core, not per
>>> CPU thread.
>>
>> This "separate register" is MSR_OFFCORE_RSP_0, right?
>> But from the SDM,  MSR_OFFCORE_RSP_0 is "thread" scope,
>> see SDM 3b, Appendix B.4 MSRS IN THE INTELŪ MICROARCHITECTURE CODENAME NEHALEM
>>
>> Or am I missing some obvious thing?
>>
> The manual is wrong on this.

Well, thanks for the info.