From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48578) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WwneL-0005Hm-DM for qemu-devel@nongnu.org; Tue, 17 Jun 2014 03:17:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WwneG-0006MP-5n for qemu-devel@nongnu.org; Tue, 17 Jun 2014 03:17:45 -0400 Received: from edge20.ethz.ch ([82.130.99.26]:43597) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WwneF-0006ME-Rn for qemu-devel@nongnu.org; Tue, 17 Jun 2014 03:17:40 -0400 From: "Aggeler Fabian" Date: Tue, 17 Jun 2014 07:17:38 +0000 Message-ID: References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> <1402444514-19658-32-git-send-email-aggelerf@ethz.ch> In-Reply-To: Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-ID: <1220727201BC9E4AB6BDA490BB0E6931@intern.ethz.ch> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH v3 31/32] target-arm: make VBAR banked List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Greg Bellows Cc: Peter Maydell , Peter Crosthwaite , QEMU Developers , Sergey Fedorov , "Edgar E. Iglesias" , Christoffer Dall On 14 Jun 2014, at 00:43, Greg Bellows > wrote: On 10 June 2014 18:55, Fabian Aggeler > wrote: When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) VBAR has a secure and a non-secure instance, which are mapped to VBAR_EL1 and VBAR_EL3. Signed-off-by: Fabian Aggeler > --- target-arm/cpu.h | 12 +++++++++++- target-arm/helper-a64.c | 6 +++++- target-arm/helper.c | 14 +++++++------- 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 048ede9..c7d606e 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -317,7 +317,17 @@ typedef struct CPUARMState { uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; - uint64_t vbar_el[4]; /* vector base address register */ + struct { /* vector base address register */ + union { + uint64_t vbar_ns; + uint64_t vbar_s; + }; + union { + uint64_t vbar_el1; + uint64_t vbar_el3; + }; + }; + uint64_t vbar_el2; This is broken. I think the intent is a union of 2 structs rather than a s= truct of two unions. Plus, vbar_el2 should be added in and hvbar made a un= ion of it. union { struct { uint64_t vbar_ns; uint64_t hvbar; uint64_t vbar_s; }; struct { uint64_t vbar_el1; uint64_t vbar_el2; uint64_t vbar_el3; }; }; Indeed. I left out the hvbar mapping to avoid introducing Virtualization Ex= tension changes in this patchset but I guess it makes sense since we are touching it anyways. uint64_t mvbar; /* (monitor) vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 1fc0d3c..a66ec94 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -444,19 +444,23 @@ void aarch64_cpu_do_interrupt(CPUState *cs) ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; unsigned int new_el =3D arm_excp_target_el(cs, cs->exception_index); - target_ulong addr =3D env->cp15.vbar_el[new_el]; + target_ulong addr =3D 0; unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); int i; uint64_t *target_esr; + switch (new_el) { case 3: target_esr =3D &env->cp15.esr_el3; + addr =3D env->cp15.vbar_el3; break; case 2: target_esr =3D &env->cp15.esr_el2; + addr =3D env->cp15.vbar_el2; break; case 1: target_esr =3D &env->cp15.esr_el1; + addr =3D env->cp15.vbar_el1; break; } diff --git a/target-arm/helper.c b/target-arm/helper.c index c3195bd..2d085aa 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -803,11 +803,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_NO_MIGRATE, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), .resetvalue =3D 0, .writefn =3D pmintenclr_write, }, - { .name =3D "VBAR", .state =3D ARM_CP_STATE_BOTH, + { .name =3D "VBAR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 12, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .writefn =3D vbar_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[1]), - .resetvalue =3D 0 }, + .access =3D PL1_RW, .writefn =3D vbar_write, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), + offsetof(CPUARMState, cp15.vbar_ns) } }, In the cases where we are registering banked registers, it may be clearer t= o keep the v7 name such as VBAR, because a banked VBAR_EL1 is counter intui= tive. { .name =3D "CCSIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, .access =3D PL1_R, .readfn =3D ccsidr_read, .type =3D ARM_CP_NO_MIGR= ATE }, @@ -2207,7 +2207,7 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] =3D { { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .writefn =3D vbar_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[2]), + .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el2), .resetvalue =3D 0 }, REGINFO_SENTINEL }; @@ -2319,7 +2319,7 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] =3D { { .name =3D "VBAR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, .access =3D PL3_RW, .writefn =3D vbar_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[3]), + .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el3), .resetvalue =3D 0 }, { .name =3D "SCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, @@ -3910,7 +3910,7 @@ void arm_cpu_do_interrupt(CPUState *cs) * This register is only followed in non-monitor mode, and is bank= ed. * Note: only bits 31:5 are valid. */ - addr +=3D env->cp15.vbar_el[1]; + addr +=3D A32_BANKED_CURRENT_REG_GET(env, vbar); } if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON) { -- 1.8.3.2