From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aisheng Dong Subject: RE: [PATCH 2/4] dt-bindings: clock: imx-lpcg: add support to parse clocks from device tree Date: Tue, 2 Apr 2019 14:55:29 +0000 Message-ID: References: <1550771836-10014-1-git-send-email-aisheng.dong@nxp.com> <1550771836-10014-3-git-send-email-aisheng.dong@nxp.com> <155112397472.191923.18309287020361500256@swboyd.mtv.corp.google.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Stephen Boyd , "linux-clk@vger.kernel.org" Cc: Rob Herring , "devicetree@vger.kernel.org" , "mturquette@baylibre.com" , dl-linux-imx , "kernel@pengutronix.de" , Fabio Estevam , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" List-Id: devicetree@vger.kernel.org Hi Stephen, > > > a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt > > > b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt > > > index 965cfa4..a317844 100644 > > > --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt > > > +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt > > > @@ -11,6 +11,20 @@ enabled by these control bits, it might still not > > > be running based on the base resource. > > > > > > Required properties: > > > +- compatible: Should be one of: > > > + "fsl,imx8qxp-lpcg" > > > + "fsl,imx8qm-lpcg" followed by > > "fsl,imx8qxp-lpcg". > > > +- reg: Address and length of the register set. > > > +- #clock-cells: Should be 1. One LPCG supports multiple > > clocks. > > > +- clocks: Input parent clocks phandle array for each clock. > > > +- bit-offset: An integer array indicating the bit offset for each > > clock. > > > +- hw-autogate: Boolean array indicating whether supports HW > > autogate for > > > + each clock. > > > > This looks like one clk per node style of bindings which is a > > direction we don't want DT bindings to go in. It leads to a bunch of > > time parsing DT to generate clks and in general doesn't represent the > > clock controller hardware that is there. Basically, anything with 'bit-offset' > > in the binding is not going to be acceptable. > > > > This is not one clk per node but one clock controller per node which strictly > describes the HW. > > On MX8, each LPCG is a separate clock controller which can control a couple of > clock output gates for one specific device to use. Each device has a > corresponding LPCG clock controller and those LPCGs are independent with > each other with separate IO space. > > Those LPCGs are distributed in various SS (subsystems) along with device > resources. > Describing them in device tree SS dtsi doesn't seem to be an issue as it is > representing the real hardware. > > For SCU clocks, they're similar case that each SS having separate clock > controllers In HW which are managed by SCU firmware. So it seems also okay > to put them in device tree SS dtsi file, right? > > If you're concerning each node having one compatible string, how about doing > like many power domain does as below? > > Having only one compatible string in clock parent nodes. > > //LSIO SS > lsio_scu_clk: lsio-scu-clock-controller { > compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; > > fspi0_clk: clock-fspi0{ > #clock-cells = <0>; > rsrc-id = ; > clk-type = ; > power-domains = <&pd IMX_SC_R_FSPI_0>; > }; > > fspi1_clk: clock-fspi1{ > ... > }; > ... > }; > > /* LPCG clocks */ > lsio_lpcg_clk: lsio-lpcg-clock-controller { > compatible = "fsl,imx8qxp-lpcg"; > > pwm0_lpcg: clock-controller@5d400000 { > reg = <0x5d400000 0x10000>; > #clock-cells = <1>; > clocks = <&pwm0_clk>, <&pwm0_clk>, <&pwm0_clk>, > <&lsio_bus_clk>, <&pwm0_clk>; > bit-offset = <0 4 16 20 24>; > clock-output-names = "pwm0_lpcg_ipg_clk", > "pwm0_lpcg_ipg_hf_clk", > "pwm0_lpcg_ipg_s_clk", > "pwm0_lpcg_ipg_slv_clk", > "pwm0_lpcg_ipg_mstr_clk"; > power-domains = <&pd IMX_SC_R_PWM_0>; > status = "disabled"; > }; > ... > }; > > I also have spent a lot time to investigate how TI and Samsung does. However, > finally i.MX is still different and I still believe current way is better for i.MX, > mainly due to below reasons: > > 1) IMX having separate clock controllers in HW, not shared one like others > 2) IMX SoC is comprised of various HW SS (Subsystem) while others don't have. > Describing clocks in DT can help a better SW architecture to describe HW. > 3) Each clock is associated with a power domain. DT is the best place to > indicate it. > 4) Clock availability (Both SCU and LPCG) are configurable according to > different HW partition configuration by SCU firmware. > Defining them all in driver will cause annoying and continued churn in driver > all the time when adding new SoC support. > e.g. > Handling availability for different SS in different SoC. > Defining Clock IDs for diferent SS in different SoC for same clocks. > > By putting clocks in DT, we can make the clock driver completely generic and > no more churn in the driver anymore in the future for adding new SoC support. > It can significantly save the driver maintain effort. > Shawn is okay with the whole point of MX8 Arch improvement[1]. (e.g. moving clocks into DT) But we still need the your agreement on the clock part first. Could you help review if this is okay to you? [1] https://patchwork.kernel.org/cover/10824537/ Regards Dong Aisheng > Last, this won't break compatibility. It's just introduce a new binding. > > Regards > Dong Aisheng > > > > +- clock-output-names: Shall be the corresponding names of the outputs. > > > + NOTE this property must be specified in the > > same order > > > + as the clock bit-offset and hw-autogate > property. > > > + > > > +Legacy binding (DEPRECATED): > > > - compatible: Should be one of: > > > "fsl,imx8qxp-lpcg-adma", From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BA8DC4360F for ; Tue, 2 Apr 2019 14:57:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by 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Received: from AM0PR04MB4211.eurprd04.prod.outlook.com (52.134.92.158) by AM0PR04MB5025.eurprd04.prod.outlook.com (20.177.40.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1750.22; Tue, 2 Apr 2019 14:55:30 +0000 Received: from AM0PR04MB4211.eurprd04.prod.outlook.com ([fe80::4514:91e2:16b7:ee2b]) by AM0PR04MB4211.eurprd04.prod.outlook.com ([fe80::4514:91e2:16b7:ee2b%4]) with mapi id 15.20.1750.014; Tue, 2 Apr 2019 14:55:30 +0000 From: Aisheng Dong To: Stephen Boyd , "linux-clk@vger.kernel.org" CC: "linux-arm-kernel@lists.infradead.org" , "mturquette@baylibre.com" , "shawnguo@kernel.org" , Fabio Estevam , dl-linux-imx , "kernel@pengutronix.de" , Rob Herring , "devicetree@vger.kernel.org" Subject: RE: [PATCH 2/4] dt-bindings: clock: imx-lpcg: add support to parse clocks from device tree Thread-Topic: [PATCH 2/4] dt-bindings: clock: imx-lpcg: add support to parse clocks from device tree Thread-Index: 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S1HOY16ArqZDcL9f1FPF6tpUPQMPa9CGoh0IM6+mOeESRK25JG+2jmeKHR+eOiTOV3ktb1tTR+jSsT5MCBz1/c1780V+NYMOwYRHSa9k4cECNgbD6C/x5Vkhnap5HW0sT8FQS5Yd1rOq8uflJSfdCARHUce1eMYTEG7eiWoGUe0pGKbD6NFrGoOClwwY8d9KMybKuycUpievttpAwCWBB5T01G7nDdExp995zBOUKLKRdOOA27cEvdMov6jBRymMcWzIPD5pr+BIiCvbduHCpjarj3jYbcdakjyTWcJIX+ZPsPzAVYjNDnE+IFEYn1u94b7979esYUrsNzGNOYAF/hxpZPtXb+php3P0HNiUiic4zQl99IJios4aJ7fCyifTlH0c+DRqh4dm7QVv39xcqPxkG+aCHoiIKifixG1GBqU= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6bdfd9f5-a845-43bc-5452-08d6b77b3fe8 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Apr 2019 14:55:29.9834 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5025 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190402_075533_959821_11A8E99B X-CRM114-Status: GOOD ( 26.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , "devicetree@vger.kernel.org" , "mturquette@baylibre.com" , dl-linux-imx , "kernel@pengutronix.de" , Fabio Estevam , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Stephen, > > > a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt > > > b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt > > > index 965cfa4..a317844 100644 > > > --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt > > > +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt > > > @@ -11,6 +11,20 @@ enabled by these control bits, it might still not > > > be running based on the base resource. > > > > > > Required properties: > > > +- compatible: Should be one of: > > > + "fsl,imx8qxp-lpcg" > > > + "fsl,imx8qm-lpcg" followed by > > "fsl,imx8qxp-lpcg". > > > +- reg: Address and length of the register set. > > > +- #clock-cells: Should be 1. One LPCG supports multiple > > clocks. > > > +- clocks: Input parent clocks phandle array for each clock. > > > +- bit-offset: An integer array indicating the bit offset for each > > clock. > > > +- hw-autogate: Boolean array indicating whether supports HW > > autogate for > > > + each clock. > > > > This looks like one clk per node style of bindings which is a > > direction we don't want DT bindings to go in. It leads to a bunch of > > time parsing DT to generate clks and in general doesn't represent the > > clock controller hardware that is there. Basically, anything with 'bit-offset' > > in the binding is not going to be acceptable. > > > > This is not one clk per node but one clock controller per node which strictly > describes the HW. > > On MX8, each LPCG is a separate clock controller which can control a couple of > clock output gates for one specific device to use. Each device has a > corresponding LPCG clock controller and those LPCGs are independent with > each other with separate IO space. > > Those LPCGs are distributed in various SS (subsystems) along with device > resources. > Describing them in device tree SS dtsi doesn't seem to be an issue as it is > representing the real hardware. > > For SCU clocks, they're similar case that each SS having separate clock > controllers In HW which are managed by SCU firmware. So it seems also okay > to put them in device tree SS dtsi file, right? > > If you're concerning each node having one compatible string, how about doing > like many power domain does as below? > > Having only one compatible string in clock parent nodes. > > //LSIO SS > lsio_scu_clk: lsio-scu-clock-controller { > compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; > > fspi0_clk: clock-fspi0{ > #clock-cells = <0>; > rsrc-id = ; > clk-type = ; > power-domains = <&pd IMX_SC_R_FSPI_0>; > }; > > fspi1_clk: clock-fspi1{ > ... > }; > ... > }; > > /* LPCG clocks */ > lsio_lpcg_clk: lsio-lpcg-clock-controller { > compatible = "fsl,imx8qxp-lpcg"; > > pwm0_lpcg: clock-controller@5d400000 { > reg = <0x5d400000 0x10000>; > #clock-cells = <1>; > clocks = <&pwm0_clk>, <&pwm0_clk>, <&pwm0_clk>, > <&lsio_bus_clk>, <&pwm0_clk>; > bit-offset = <0 4 16 20 24>; > clock-output-names = "pwm0_lpcg_ipg_clk", > "pwm0_lpcg_ipg_hf_clk", > "pwm0_lpcg_ipg_s_clk", > "pwm0_lpcg_ipg_slv_clk", > "pwm0_lpcg_ipg_mstr_clk"; > power-domains = <&pd IMX_SC_R_PWM_0>; > status = "disabled"; > }; > ... > }; > > I also have spent a lot time to investigate how TI and Samsung does. However, > finally i.MX is still different and I still believe current way is better for i.MX, > mainly due to below reasons: > > 1) IMX having separate clock controllers in HW, not shared one like others > 2) IMX SoC is comprised of various HW SS (Subsystem) while others don't have. > Describing clocks in DT can help a better SW architecture to describe HW. > 3) Each clock is associated with a power domain. DT is the best place to > indicate it. > 4) Clock availability (Both SCU and LPCG) are configurable according to > different HW partition configuration by SCU firmware. > Defining them all in driver will cause annoying and continued churn in driver > all the time when adding new SoC support. > e.g. > Handling availability for different SS in different SoC. > Defining Clock IDs for diferent SS in different SoC for same clocks. > > By putting clocks in DT, we can make the clock driver completely generic and > no more churn in the driver anymore in the future for adding new SoC support. > It can significantly save the driver maintain effort. > Shawn is okay with the whole point of MX8 Arch improvement[1]. (e.g. moving clocks into DT) But we still need the your agreement on the clock part first. Could you help review if this is okay to you? [1] https://patchwork.kernel.org/cover/10824537/ Regards Dong Aisheng > Last, this won't break compatibility. It's just introduce a new binding. > > Regards > Dong Aisheng > > > > +- clock-output-names: Shall be the corresponding names of the outputs. > > > + NOTE this property must be specified in the > > same order > > > + as the clock bit-offset and hw-autogate > property. > > > + > > > +Legacy binding (DEPRECATED): > > > - compatible: Should be one of: > > > "fsl,imx8qxp-lpcg-adma", _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel