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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM0PR04MB6004.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f27cf617-adb3-4844-3d35-08db34d31159 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2023 06:08:53.6700 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vl3aCA2w8fdZuANAQ5z2bz/Ap3g+cJ9eLhVvq2Xtkbe0OlIi3SqHsZ7DZixZB+OdQUod/PAh/SCib9w05C6tDQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6910 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Hi > -----Original Message----- > From: Meenakshi Aggarwal > Sent: Wednesday, March 22, 2023 11:47 AM > To: Horia Geanta ; Varun Sethi ; > Pankaj Gupta ; Gaurav Jain ; > herbert@gondor.apana.org.au; davem@davemloft.net; linux- > crypto@vger.kernel.org; linux-kernel@vger.kernel.org > Cc: Meenakshi Aggarwal > Subject: [PATCH v2 2/2] crypto: caam - OP-TEE firmware support >=20 > From: Horia GeantA >=20 > caam driver needs to be aware of OP-TEE f/w presence, since some things a= re > done differently: >=20 > 1. there is no access to controller's register page (note however that so= me > registers are aliased in job rings' register pages) >=20 > 2 Due to this, MCFGR[PS] cannot be read and driver assumes MCFGR[PS] =3D = b'0 - > engine using 32-bit address pointers. >=20 > This is in sync with the fact that: > -all i.MX SoCs currently use MCFGR[PS] =3D b'0 -only i.MX OP-TEE use case= s don't > allow access to controller register page >=20 > Signed-off-by: Horia GeantA > Signed-off-by: Meenakshi Aggarwal > --- > drivers/crypto/caam/ctrl.c | 23 ++++++++++++++++++++++- > drivers/crypto/caam/debugfs.c | 3 +++ > drivers/crypto/caam/intern.h | 1 + > 3 files changed, 26 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c inde= x > ae07c1e5fd38..d96c81540957 100644 > --- a/drivers/crypto/caam/ctrl.c > +++ b/drivers/crypto/caam/ctrl.c > @@ -633,6 +633,7 @@ static int caam_probe(struct platform_device *pdev) > int pg_size; > int BLOCK_OFFSET =3D 0; > bool pr_support =3D false; > + bool reg_access =3D true; >=20 > ctrlpriv =3D devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL); > if (!ctrlpriv) > @@ -646,6 +647,17 @@ static int caam_probe(struct platform_device *pdev) > caam_imx =3D (bool)imx_soc_match; >=20 > if (imx_soc_match) { > + /* > + * Until Layerscape and i.MX OP-TEE get in sync, > + * only i.MX OP-TEE use cases disallow access to > + * caam page 0 (controller) registers. > + */ > + np =3D of_find_compatible_node(NULL, NULL, "linaro,optee-tz"); > + ctrlpriv->optee_en =3D !!np; > + of_node_put(np); > + > + reg_access =3D ctrlpriv->optee_en; When optee is enabled in imx, we need to skip the operations done by optee. Update this to reg_access =3D !ctrlpriv->optee_en; Regards Gaurav Jain > + > if (!imx_soc_match->data) { > dev_err(dev, "No clock data provided for i.MX SoC"); > return -EINVAL; > @@ -696,7 +708,8 @@ static int caam_probe(struct platform_device *pdev) > caam_little_end =3D !(bool)(rd_reg32(&perfmon->status) & > (CSTA_PLEND | CSTA_ALT_PLEND)); > comp_params =3D rd_reg32(&perfmon->comp_parms_ms); > - if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & > MCFGR_LONG_PTR) > + if (reg_access && comp_params & CTPR_MS_PS && > + rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR) > caam_ptr_sz =3D sizeof(u64); > else > caam_ptr_sz =3D sizeof(u32); > @@ -761,6 +774,9 @@ static int caam_probe(struct platform_device *pdev) > } > #endif >=20 > + if (!reg_access) > + goto set_dma_mask; > + > /* > * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, > * long pointers in master configuration register. > @@ -800,6 +816,7 @@ static int caam_probe(struct platform_device *pdev) > JRSTART_JR1_START | JRSTART_JR2_START | > JRSTART_JR3_START); >=20 > +set_dma_mask: > ret =3D dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev)); > if (ret) { > dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret); > @@ -842,6 +859,9 @@ static int caam_probe(struct platform_device *pdev) > return -ENOMEM; > } >=20 > + if (!reg_access) > + goto report_live; > + > comp_params =3D rd_reg32(&perfmon->comp_parms_ls); > ctrlpriv->blob_present =3D !!(comp_params & CTPR_LS_BLOB); >=20 > @@ -943,6 +963,7 @@ static int caam_probe(struct platform_device *pdev) > clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); > } >=20 > +report_live: > /* NOTE: RTIC detection ought to go here, around Si time */ >=20 > caam_id =3D (u64)rd_reg32(&perfmon->caam_id_ms) << 32 | diff --git > a/drivers/crypto/caam/debugfs.c b/drivers/crypto/caam/debugfs.c index > 798ba989a8a0..cec93498836d 100644 > --- a/drivers/crypto/caam/debugfs.c > +++ b/drivers/crypto/caam/debugfs.c > @@ -77,6 +77,9 @@ void caam_debugfs_init(struct caam_drv_private *ctrlpri= v, > debugfs_create_file("fault_status", 0444, ctrlpriv->ctl, > &perfmon->status, &caam_fops_u32_ro); >=20 > + if (ctrlpriv->optee_en) > + return; > + > /* Internal covering keys (useful in non-secure mode only) */ > ctrlpriv->ctl_kek_wrap.data =3D (__force void *)&ctrlpriv->ctrl->kek[0]= ; > ctrlpriv->ctl_kek_wrap.size =3D KEK_KEY_SIZE * sizeof(u32); diff --git > a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h index > 572cf66c887a..86ed1b91c22d 100644 > --- a/drivers/crypto/caam/intern.h > +++ b/drivers/crypto/caam/intern.h > @@ -94,6 +94,7 @@ struct caam_drv_private { > u8 qi_present; /* Nonzero if QI present in device */ > u8 blob_present; /* Nonzero if BLOB support present in device */ > u8 mc_en; /* Nonzero if MC f/w is active */ > + u8 optee_en; /* Nonzero if OP-TEE f/w is active */ > int secvio_irq; /* Security violation interrupt number */ > int virt_en; /* Virtualization enabled in CAAM */ > int era; /* CAAM Era (internal HW revision) */ > -- > 2.25.1