From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shahaf Shuler Subject: Re: [PATCH 14/14] net/mlx5: add source vport match to the ingress rules Date: Thu, 21 Mar 2019 12:15:16 +0000 Message-ID: References: <1551376985-11096-1-git-send-email-viacheslavo@mellanox.com> <1553155888-27498-1-git-send-email-viacheslavo@mellanox.com> <1553155888-27498-15-git-send-email-viacheslavo@mellanox.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable To: Slava Ovsiienko , "dev@dpdk.org" Return-path: Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-eopbgr130050.outbound.protection.outlook.com [40.107.13.50]) by dpdk.org (Postfix) with ESMTP id 278D51B4C0 for ; Thu, 21 Mar 2019 13:15:25 +0100 (CET) In-Reply-To: <1553155888-27498-15-git-send-email-viacheslavo@mellanox.com> Content-Language: en-US List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Thursday, March 21, 2019 10:11 AM, Viacheslav Ovsiienko: > Subject: [PATCH 14/14] net/mlx5: add source vport match to the ingress ru= les >=20 > For E-Switch configurations over multiport Infiniband devices we should a= dd > source vport match to correctly distribute traffic between representors. >=20 > Signed-off-by: Viacheslav Ovsiienko > --- > drivers/net/mlx5/mlx5_flow_dv.c | 38 > ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 38 insertions(+) >=20 > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c index b8943da..489b3bd 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -3095,6 +3095,29 @@ struct field_modify_info modify_tcp[] =3D { } >=20 > /** > + * Add source vport match to the specified matcher. > + * > + * @param[in, out] matcher > + * Flow matcher. > + * @param[in, out] key > + * Flow matcher value. > + * @param[in] port > + * Source vport value to match > + * @param[in] mask > + * Mask > + */ > +static void > +flow_dv_translate_source_vport(void *matcher, void *key, > + int16_t port, uint16_t mask) > +{ > + void *misc_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > misc_parameters); > + void *misc_v =3D MLX5_ADDR_OF(fte_match_param, key, > misc_parameters); > + > + MLX5_SET(fte_match_set_misc, misc_m, source_port, mask); > + MLX5_SET(fte_match_set_misc, misc_v, source_port, port); } > + > +/** > * Fill the flow with DV spec. > * > * @param[in] dev > @@ -3389,6 +3412,21 @@ struct field_modify_info modify_tcp[] =3D { > } > dev_flow->dv.actions_n =3D actions_n; > flow->actions =3D action_flags; > + if (attr->ingress && !attr->transfer && > + (priv->representor || priv->master)) { > + /* It was validated - we support unidirections flows only. */ > + assert(!attr->egress); > + /* > + * Add matching on source vport index only > + * for ingress rules in E-Switch configurations. > + */ > + flow_dv_translate_source_vport(matcher.mask.buf, > + dev_flow->dv.value.buf, > + priv->representor_id < 0 ? > + priv->representor_id : > + priv->representor_id + 1, The vport of representor_id 0 will be 1?=20 Who owns vport 0?=20 > + 0xffff); > + } > for (; items->type !=3D RTE_FLOW_ITEM_TYPE_END; items++) { > int tunnel =3D !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > void *match_mask =3D matcher.mask.buf; > -- > 1.8.3.1