From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932081AbcBALzE (ORCPT ); Mon, 1 Feb 2016 06:55:04 -0500 Received: from mail-db3on0056.outbound.protection.outlook.com ([157.55.234.56]:28125 "EHLO emea01-db3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753900AbcBALy7 convert rfc822-to-8bit (ORCPT ); Mon, 1 Feb 2016 06:54:59 -0500 X-Greylist: delayed 1037 seconds by postgrey-1.27 at vger.kernel.org; Mon, 01 Feb 2016 06:54:59 EST From: Yunhui Cui To: Cyrille Pitchen , Yunhui Cui , "dwmw2@infradead.org" , "computersforpeace@gmail.com" , "han.xu@freescale.com" CC: "linux-mtd@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Yao Yuan Subject: RE: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support Thread-Topic: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support Thread-Index: AQHRWqSPInF4fbCuCUuYDvUznHASCJ8XD90g Date: Mon, 1 Feb 2016 11:23:16 +0000 Message-ID: References: <1454067669-35274-1-git-send-email-B56489@freescale.com> <1454067669-35274-4-git-send-email-B56489@freescale.com> <56AB7C6E.2050300@atmel.com> In-Reply-To: <56AB7C6E.2050300@atmel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: atmel.com; dkim=none (message not signed) header.d=none;atmel.com; dmarc=none action=none header.from=nxp.com; x-originating-ip: [192.158.241.86] x-microsoft-exchange-diagnostics: 1;AM3PR04MB0726;5:hG/hLxmI+3hHSCDAlUGYGf/w/MtItmQicgTiuyx5vMzf542sMT5uEqVggea2wbvj7vaPy2l4haL6iZf48wdNry4DItVpRDPoqYWxuuQSEVOmIjGcJ0J0Fvo1Yk+Ku5b4VEAo//fZJvaCZpZ9K/tIzg==;24:qoB5ZcipaQd0120Y24b4TWsVzrlFfLZ+H+eTegkn3qXBQAQAox/EyaH0U8xs1ic4zh5EDsvA+dVoCUA5YOCEZLrUW9yxtotp96H+GDczpg0= x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AM3PR04MB0726; x-ms-office365-filtering-correlation-id: 2725f7bf-15f0-4a6c-d43d-08d32afa14eb x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(101931422205132); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046);SRVR:AM3PR04MB0726;BCL:0;PCL:0;RULEID:;SRVR:AM3PR04MB0726; x-forefront-prvs: 0839D067E7 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(377454003)(13464003)(479174004)(66066001)(4326007)(5004730100002)(2906002)(92566002)(5001770100001)(54356999)(86362001)(575784001)(106116001)(76176999)(19580395003)(189998001)(19580405001)(50986999)(5001960100002)(40100003)(2950100001)(76576001)(1220700001)(1096002)(87936001)(586003)(3846002)(5008740100001)(102836003)(74316001)(5250100002)(2501003)(33656002)(3470700001)(5002640100001)(3280700002)(11100500001)(2201001)(3660700001)(5003600100002)(7059030);DIR:OUT;SFP:1101;SCL:1;SRVR:AM3PR04MB0726;H:AM3PR04MB1441.eurprd04.prod.outlook.com;FPR:;SPF:None;MLV:sfv;LANG:en; spamdiagnosticoutput: 1:23 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Feb 2016 11:23:16.9312 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR04MB0726 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Cyrille, Thanks for your suggestions very much, I'll resend version 2 patch set. Best Regards Yunhui -----Original Message----- From: Cyrille Pitchen [mailto:cyrille.pitchen@atmel.com] Sent: Friday, January 29, 2016 10:51 PM To: Yunhui Cui; dwmw2@infradead.org; computersforpeace@gmail.com; han.xu@freescale.com Cc: linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Yao Yuan Subject: Re: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support Hi Yunhui, Le 29/01/2016 12:41, Yunhui Cui a écrit : > The qspi driver add generic fast-read mode for different flash > venders, including Micron family. Also add some special operations for > Micron flash read/write in spi-nor.c. > > Signed-off-by: Yunhui Cui > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------ > drivers/mtd/spi-nor/spi-nor.c | 6 +++++- > 2 files changed, 26 insertions(+), 7 deletions(-) > [...] > diff --git a/drivers/mtd/spi-nor/spi-nor.c > b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..79a025c 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -763,7 +763,8 @@ static const struct flash_info spi_nor_ids[] = { > { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_FAST | > + SPI_NOR_QUAD_READ) }, > { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | > USE_FSR | SPI_NOR_QUAD_READ) }, This modification looks wrong. First SPI_NOR_FAST is part of enum read_mode (from spi-nor.h) and is not intended to be used as a flag, unlike SPI_NOR_QUAD_READ (defined in spi-nor.c just below the flags field of struct flash_info). Also, creating a new flag to choose between the Read and the Fast Read commands is not needed: see my last comment below. > @@ -1233,6 +1234,7 @@ int spi_nor_scan(struct spi_nor *nor, const char > *name, enum read_mode mode) > > if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || > JEDEC_MFR(info) == SNOR_MFR_INTEL || > + JEDEC_MFR(info) == SNOR_MFR_MICRON || > JEDEC_MFR(info) == SNOR_MFR_SST) { > write_enable(nor); > write_sr(nor, 0); This update is not related with the support of fast-read mode, it deals with the write protection. Hence it should be moved into a dedicated patch. Also be careful as some bits of the Status Register are non-volatile on Micron memories. This modification may change their values but I guess you only want to clear the write enable/disable (7) bit. > @@ -1317,6 +1319,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) > nor->flash_read = SPI_NOR_QUAD; > } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { > nor->flash_read = SPI_NOR_DUAL; > + } else if (mode == SPI_NOR_FAST && info->flags & SPI_NOR_FAST) { > + nor->flash_read = SPI_NOR_FAST; > } > > /* Default commands */ > The spi-nor framework already checks the "m25p,fast-read" DT property to choose between the Read (0x03) and Fast Read (0x0b) command. So the fsl-quadspi.c driver should rely on this existing property to choose which of SPI_NOR_FAST or SPI_NOR_QUAD is used as the mode argument of spi_nor_scan(). As long as mode is neither SPI_NOR_QUAD nor SPI_NOR_DUAL, the choice of the read op code is done according to whether the "m25p,fast-read" DT property is set or not. Best regards, Cyrille From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yunhui Cui To: Cyrille Pitchen , Yunhui Cui , "dwmw2@infradead.org" , "computersforpeace@gmail.com" , "han.xu@freescale.com" CC: "linux-mtd@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Yao Yuan Subject: RE: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support Date: Mon, 1 Feb 2016 11:23:16 +0000 Message-ID: References: <1454067669-35274-1-git-send-email-B56489@freescale.com> <1454067669-35274-4-git-send-email-B56489@freescale.com> <56AB7C6E.2050300@atmel.com> In-Reply-To: <56AB7C6E.2050300@atmel.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Hi Cyrille, Thanks for your suggestions very much, I'll resend version 2 patch set. Best Regards Yunhui -----Original Message----- From: Cyrille Pitchen [mailto:cyrille.pitchen@atmel.com]=20 Sent: Friday, January 29, 2016 10:51 PM To: Yunhui Cui; dwmw2@infradead.org; computersforpeace@gmail.com; han.xu@fr= eescale.com Cc: linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org; linux-arm-= kernel@lists.infradead.org; Yao Yuan Subject: Re: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support Hi Yunhui, Le 29/01/2016 12:41, Yunhui Cui a =E9crit : > The qspi driver add generic fast-read mode for different flash=20 > venders, including Micron family. Also add some special operations for=20 > Micron flash read/write in spi-nor.c. >=20 > Signed-off-by: Yunhui Cui > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------ > drivers/mtd/spi-nor/spi-nor.c | 6 +++++- > 2 files changed, 26 insertions(+), 7 deletions(-) >=20 [...] > diff --git a/drivers/mtd/spi-nor/spi-nor.c=20 > b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..79a025c 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -763,7 +763,8 @@ static const struct flash_info spi_nor_ids[] =3D { > { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_Q= UAD_READ) }, > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_Q= UAD_READ) }, > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) = }, > - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) = }, > + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_FAST | > + SPI_NOR_QUAD_READ) }, > { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_Q= UAD_READ) }, > { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |= SPI_NOR_QUAD_READ) }, > { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K |=20 > USE_FSR | SPI_NOR_QUAD_READ) }, This modification looks wrong. First SPI_NOR_FAST is part of enum read_mode (from spi-nor.h) and is not in= tended to be used as a flag, unlike SPI_NOR_QUAD_READ (defined in spi-nor.c= just below the flags field of struct flash_info). Also, creating a new flag to choose between the Read and the Fast Read comm= ands is not needed: see my last comment below. > @@ -1233,6 +1234,7 @@ int spi_nor_scan(struct spi_nor *nor, const char=20 > *name, enum read_mode mode) > =20 > if (JEDEC_MFR(info) =3D=3D SNOR_MFR_ATMEL || > JEDEC_MFR(info) =3D=3D SNOR_MFR_INTEL || > + JEDEC_MFR(info) =3D=3D SNOR_MFR_MICRON || > JEDEC_MFR(info) =3D=3D SNOR_MFR_SST) { > write_enable(nor); > write_sr(nor, 0); This update is not related with the support of fast-read mode, it deals wit= h the write protection. Hence it should be moved into a dedicated patch. Also be careful as some bits of the Status Register are non-volatile on Mic= ron memories. This modification may change their values but I guess you onl= y want to clear the write enable/disable (7) bit. > @@ -1317,6 +1319,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *n= ame, enum read_mode mode) > nor->flash_read =3D SPI_NOR_QUAD; > } else if (mode =3D=3D SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ)= { > nor->flash_read =3D SPI_NOR_DUAL; > + } else if (mode =3D=3D SPI_NOR_FAST && info->flags & SPI_NOR_FAST) { > + nor->flash_read =3D SPI_NOR_FAST; > } > =20 > /* Default commands */ >=20 The spi-nor framework already checks the "m25p,fast-read" DT property to ch= oose between the Read (0x03) and Fast Read (0x0b) command. So the fsl-quadspi.c driver should rely on this existing property to choose= which of SPI_NOR_FAST or SPI_NOR_QUAD is used as the mode argument of spi_= nor_scan(). As long as mode is neither SPI_NOR_QUAD nor SPI_NOR_DUAL, the c= hoice of the read op code is done according to whether the "m25p,fast-read"= DT property is set or not. Best regards, Cyrille From mboxrd@z Thu Jan 1 00:00:00 1970 From: yunhui.cui@nxp.com (Yunhui Cui) Date: Mon, 1 Feb 2016 11:23:16 +0000 Subject: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support In-Reply-To: <56AB7C6E.2050300@atmel.com> References: <1454067669-35274-1-git-send-email-B56489@freescale.com> <1454067669-35274-4-git-send-email-B56489@freescale.com> <56AB7C6E.2050300@atmel.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Cyrille, Thanks for your suggestions very much, I'll resend version 2 patch set. Best Regards Yunhui -----Original Message----- From: Cyrille Pitchen [mailto:cyrille.pitchen at atmel.com] Sent: Friday, January 29, 2016 10:51 PM To: Yunhui Cui; dwmw2 at infradead.org; computersforpeace at gmail.com; han.xu at freescale.com Cc: linux-mtd at lists.infradead.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Yao Yuan Subject: Re: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support Hi Yunhui, Le 29/01/2016 12:41, Yunhui Cui a ?crit : > The qspi driver add generic fast-read mode for different flash > venders, including Micron family. Also add some special operations for > Micron flash read/write in spi-nor.c. > > Signed-off-by: Yunhui Cui > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------ > drivers/mtd/spi-nor/spi-nor.c | 6 +++++- > 2 files changed, 26 insertions(+), 7 deletions(-) > [...] > diff --git a/drivers/mtd/spi-nor/spi-nor.c > b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..79a025c 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -763,7 +763,8 @@ static const struct flash_info spi_nor_ids[] = { > { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_FAST | > + SPI_NOR_QUAD_READ) }, > { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | > USE_FSR | SPI_NOR_QUAD_READ) }, This modification looks wrong. First SPI_NOR_FAST is part of enum read_mode (from spi-nor.h) and is not intended to be used as a flag, unlike SPI_NOR_QUAD_READ (defined in spi-nor.c just below the flags field of struct flash_info). Also, creating a new flag to choose between the Read and the Fast Read commands is not needed: see my last comment below. > @@ -1233,6 +1234,7 @@ int spi_nor_scan(struct spi_nor *nor, const char > *name, enum read_mode mode) > > if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || > JEDEC_MFR(info) == SNOR_MFR_INTEL || > + JEDEC_MFR(info) == SNOR_MFR_MICRON || > JEDEC_MFR(info) == SNOR_MFR_SST) { > write_enable(nor); > write_sr(nor, 0); This update is not related with the support of fast-read mode, it deals with the write protection. Hence it should be moved into a dedicated patch. Also be careful as some bits of the Status Register are non-volatile on Micron memories. This modification may change their values but I guess you only want to clear the write enable/disable (7) bit. > @@ -1317,6 +1319,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) > nor->flash_read = SPI_NOR_QUAD; > } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { > nor->flash_read = SPI_NOR_DUAL; > + } else if (mode == SPI_NOR_FAST && info->flags & SPI_NOR_FAST) { > + nor->flash_read = SPI_NOR_FAST; > } > > /* Default commands */ > The spi-nor framework already checks the "m25p,fast-read" DT property to choose between the Read (0x03) and Fast Read (0x0b) command. So the fsl-quadspi.c driver should rely on this existing property to choose which of SPI_NOR_FAST or SPI_NOR_QUAD is used as the mode argument of spi_nor_scan(). As long as mode is neither SPI_NOR_QUAD nor SPI_NOR_DUAL, the choice of the read op code is done according to whether the "m25p,fast-read" DT property is set or not. Best regards, Cyrille