From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751699AbdGZC5j (ORCPT ); Tue, 25 Jul 2017 22:57:39 -0400 Received: from mail-he1eur01on0066.outbound.protection.outlook.com ([104.47.0.66]:6544 "EHLO EUR01-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751503AbdGZC5i (ORCPT ); Tue, 25 Jul 2017 22:57:38 -0400 From: "A.s. Dong" To: "A.s. Dong" , "linux-clk@vger.kernel.org" CC: "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "sboyd@codeaurora.org" , "mturquette@baylibre.com" , "dongas86@gmail.com" , "shawnguo@kernel.org" , Anson Huang , Jacky Bai Subject: RE: [PATCH V2 00/10] clk: add imx7ulp clk support Thread-Topic: [PATCH V2 00/10] clk: add imx7ulp clk support Thread-Index: AQHS+83NWQVyDNLuf0yAGnXwSm7qdqJlfgFw Date: Wed, 26 Jul 2017 02:57:32 +0000 Message-ID: References: <1499946435-7177-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1499946435-7177-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-originating-ip: [192.158.241.86] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;AM3PR04MB308;7:gO3jJwYV//iilUcZHqg9KS5FVlBAAyXEUndYNUH+2fsNWW0SU26fcDGKfhnvFcNNn40Sm31KxfcBQeZvM5uSEY8iHN7OfmDBrZJVMzOcdCCEqwxndi5eKfNVj5qkAvMtBUvVdWaxkmH77cxaGHV+iXRtNaA1jynDwWr365/+w+vmJmkTweKmOo1tkx0BV81DOzi2AUtnuRbf7A5/2mtzxRFcsOggXjzV7cnoYt3upOwh0eL+WZsozEVkgVTYjWxrk56uUk4An6odHEBwCRlY0q3Mo0xkNbf88/gL7Cm8ZpRm3gPJGsJscd4lpEPA3IW9/y73R0qBJdrIpiibj7rOAAVCTBlpPhvBU0qljyKfysb3NQWcehotoMA3jhwx0Pf+16lEk4OtUGFi8LpqYbTFyFOjK1E5HSS3qQOsSHIx/tFy6NF3PQm4dKKQNC9/vpEtbhxb0MU2jr4ZxBHs97ffzo0C2pOiQm7KUEJag9lnt/VDRxgKB4txD4oDnlsYwEeZ38rVh8XKXUM12xFJML5WPtUGsc/Oxr/HfU/URrPjIvxCOXeTq3agJ/fTC+FzmL/cD8+4K7vkT+iAkq//8UL7mctBOdnE3e4e5NXf/v+XeZ3KP0rBAbB1o/lufsgBG3OBNDm3ohnVr28W9bMHsycfo036zWrrAzi/TE/bozJMaQxeOU8nvOzBGUBzaRkUrEx9gjUt0qR34umURkg7H40ysEuFfvAZExzaZxOooqx1gTgA+94xUlCY16gYxoZaU0IeQQelXExP1Lu02adG5IkbN7GOqKLD+Nrgm5dEMEimCCM= x-forefront-antispam-report: SFV:SKI;SCL:-1;SFV:NSPM;SFS:(10009020)(6009001)(39850400002)(39410400002)(39400400002)(39450400003)(39840400002)(39860400002)(377454003)(189002)(13464003)(54534003)(199003)(105586002)(66066001)(76176999)(81156014)(7696004)(478600001)(39060400002)(6506006)(7736002)(86362001)(53546010)(38730400002)(81166006)(25786009)(4326008)(101416001)(5250100002)(8676002)(50986999)(106356001)(14454004)(68736007)(2501003)(54356999)(8936002)(2906002)(5660300001)(2900100001)(3280700002)(9686003)(6246003)(74316002)(2950100002)(55016002)(99286003)(54906002)(229853002)(189998001)(97736004)(3846002)(6436002)(102836003)(6116002)(53936002)(33656002)(3660700001)(305945005);DIR:OUT;SFP:1101;SCL:1;SRVR:AM3PR04MB308;H:AM3PR04MB306.eurprd04.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; x-ms-office365-filtering-correlation-id: 772f3248-c66f-455c-c942-08d4d3d20fc6 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254075)(300000503095)(300135400095)(48565401081)(2017052603031)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);SRVR:AM3PR04MB308; x-ms-traffictypediagnostic: AM3PR04MB308: x-exchange-antispam-report-test: UriScan:(9452136761055)(185117386973197)(258649278758335); x-microsoft-antispam-prvs: x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(8121501046)(5005006)(100000703101)(100105400095)(93006095)(93001095)(10201501046)(3002001)(6055026)(6041248)(20161123558100)(20161123562025)(20161123555025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123560025)(20161123564025)(6072148)(100000704101)(100105200095)(100000705101)(100105500095);SRVR:AM3PR04MB308;BCL:0;PCL:0;RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);SRVR:AM3PR04MB308; x-forefront-prvs: 038002787A spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Jul 2017 02:57:32.5642 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR04MB308 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by nfs id v6Q2vjGa023787 Ping... > -----Original Message----- > From: Dong Aisheng [mailto:aisheng.dong@nxp.com] > Sent: Thursday, July 13, 2017 7:47 PM > To: linux-clk@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > sboyd@codeaurora.org; mturquette@baylibre.com; A.s. Dong; > dongas86@gmail.com; shawnguo@kernel.org; Anson Huang; Jacky Bai > Subject: [PATCH V2 00/10] clk: add imx7ulp clk support > > This patch series intends to add imx7ulp clk support. > > i.MX7ULP Clock functions are under joint control of the System Clock > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core > Mode Controller (CMC)1 blocks > > The clocking scheme provides clear separation between M4 domain and A7 > domain. Except for a few clock sources shared between two domains, such as > the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC > clock (FIRCLK), clock sources and clock management are separated and > contained within each domain. > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > Note: this series only adds A7 clock domain support as M4 clock domain > will be handled by M4 seperately. > > Change Log: > v1->v2: > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers > * use clk_hw apis to register clocks > * use of_clk_add_hw_provider > * split the clocks register process into two parts: early part for > possible > timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part > for > the left normal peripheral clocks registered by a platform driver. > > Dong Aisheng (10): > clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support > clk: reparent orphans after critical clocks enabled > clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support > clk: imx: add pllv4 support > clk: imx: add pfdv2 support > clk: imx: add composite clk support > dt-bindings: clock: add imx7ulp clock binding doc > clk: imx: make mux parent strings const > clk: imx: implement new clk_hw based APIs > clk: imx: add imx7ulp clk driver > > .../devicetree/bindings/clock/imx7ulp-clock.txt | 62 ++++++ > drivers/clk/clk-divider.c | 100 ++++++++- > drivers/clk/clk-fractional-divider.c | 10 + > drivers/clk/clk.c | 39 ++-- > drivers/clk/imx/Makefile | 6 +- > drivers/clk/imx/clk-busy.c | 2 +- > drivers/clk/imx/clk-composite.c | 90 ++++++++ > drivers/clk/imx/clk-fixup-mux.c | 2 +- > drivers/clk/imx/clk-imx7ulp.c | 245 > +++++++++++++++++++++ > drivers/clk/imx/clk-pfdv2.c | 207 > +++++++++++++++++ > drivers/clk/imx/clk-pllv4.c | 188 ++++++++++++++++ > drivers/clk/imx/clk.c | 22 ++ > drivers/clk/imx/clk.h | 92 +++++++- > include/dt-bindings/clock/imx7ulp-clock.h | 108 +++++++++ > include/linux/clk-provider.h | 17 ++ > 15 files changed, 1159 insertions(+), 31 deletions(-) create mode 100644 > Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > create mode 100644 drivers/clk/imx/clk-composite.c create mode 100644 > drivers/clk/imx/clk-imx7ulp.c create mode 100644 drivers/clk/imx/clk- > pfdv2.c create mode 100644 drivers/clk/imx/clk-pllv4.c create mode > 100644 include/dt-bindings/clock/imx7ulp-clock.h > > -- > 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: "A.s. Dong" To: "A.s. Dong" , "linux-clk@vger.kernel.org" CC: "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "sboyd@codeaurora.org" , "mturquette@baylibre.com" , "dongas86@gmail.com" , "shawnguo@kernel.org" , Anson Huang , Jacky Bai Subject: RE: [PATCH V2 00/10] clk: add imx7ulp clk support Date: Wed, 26 Jul 2017 02:57:32 +0000 Message-ID: References: <1499946435-7177-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1499946435-7177-1-git-send-email-aisheng.dong@nxp.com> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 List-ID: Ping... > -----Original Message----- > From: Dong Aisheng [mailto:aisheng.dong@nxp.com] > Sent: Thursday, July 13, 2017 7:47 PM > To: linux-clk@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > sboyd@codeaurora.org; mturquette@baylibre.com; A.s. Dong; > dongas86@gmail.com; shawnguo@kernel.org; Anson Huang; Jacky Bai > Subject: [PATCH V2 00/10] clk: add imx7ulp clk support >=20 > This patch series intends to add imx7ulp clk support. >=20 > i.MX7ULP Clock functions are under joint control of the System Clock > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Cor= e > Mode Controller (CMC)1 blocks >=20 > The clocking scheme provides clear separation between M4 domain and A7 > domain. Except for a few clock sources shared between two domains, such a= s > the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC > clock (FIRCLK), clock sources and clock management are separated and > contained within each domain. >=20 > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. >=20 > Note: this series only adds A7 clock domain support as M4 clock domain > will be handled by M4 seperately. >=20 > Change Log: > v1->v2: > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers > * use clk_hw apis to register clocks > * use of_clk_add_hw_provider > * split the clocks register process into two parts: early part for > possible > timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part > for > the left normal peripheral clocks registered by a platform driver. >=20 > Dong Aisheng (10): > clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support > clk: reparent orphans after critical clocks enabled > clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support > clk: imx: add pllv4 support > clk: imx: add pfdv2 support > clk: imx: add composite clk support > dt-bindings: clock: add imx7ulp clock binding doc > clk: imx: make mux parent strings const > clk: imx: implement new clk_hw based APIs > clk: imx: add imx7ulp clk driver >=20 > .../devicetree/bindings/clock/imx7ulp-clock.txt | 62 ++++++ > drivers/clk/clk-divider.c | 100 ++++++++- > drivers/clk/clk-fractional-divider.c | 10 + > drivers/clk/clk.c | 39 ++-- > drivers/clk/imx/Makefile | 6 +- > drivers/clk/imx/clk-busy.c | 2 +- > drivers/clk/imx/clk-composite.c | 90 ++++++++ > drivers/clk/imx/clk-fixup-mux.c | 2 +- > drivers/clk/imx/clk-imx7ulp.c | 245 > +++++++++++++++++++++ > drivers/clk/imx/clk-pfdv2.c | 207 > +++++++++++++++++ > drivers/clk/imx/clk-pllv4.c | 188 +++++++++++++++= + > drivers/clk/imx/clk.c | 22 ++ > drivers/clk/imx/clk.h | 92 +++++++- > include/dt-bindings/clock/imx7ulp-clock.h | 108 +++++++++ > include/linux/clk-provider.h | 17 ++ > 15 files changed, 1159 insertions(+), 31 deletions(-) create mode 10064= 4 > Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > create mode 100644 drivers/clk/imx/clk-composite.c create mode 100644 > drivers/clk/imx/clk-imx7ulp.c create mode 100644 drivers/clk/imx/clk- > pfdv2.c create mode 100644 drivers/clk/imx/clk-pllv4.c create mode > 100644 include/dt-bindings/clock/imx7ulp-clock.h >=20 > -- > 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: aisheng.dong@nxp.com (A.s. Dong) Date: Wed, 26 Jul 2017 02:57:32 +0000 Subject: [PATCH V2 00/10] clk: add imx7ulp clk support In-Reply-To: <1499946435-7177-1-git-send-email-aisheng.dong@nxp.com> References: <1499946435-7177-1-git-send-email-aisheng.dong@nxp.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Ping... > -----Original Message----- > From: Dong Aisheng [mailto:aisheng.dong at nxp.com] > Sent: Thursday, July 13, 2017 7:47 PM > To: linux-clk at vger.kernel.org > Cc: linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; > sboyd at codeaurora.org; mturquette at baylibre.com; A.s. Dong; > dongas86 at gmail.com; shawnguo at kernel.org; Anson Huang; Jacky Bai > Subject: [PATCH V2 00/10] clk: add imx7ulp clk support > > This patch series intends to add imx7ulp clk support. > > i.MX7ULP Clock functions are under joint control of the System Clock > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core > Mode Controller (CMC)1 blocks > > The clocking scheme provides clear separation between M4 domain and A7 > domain. Except for a few clock sources shared between two domains, such as > the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC > clock (FIRCLK), clock sources and clock management are separated and > contained within each domain. > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > Note: this series only adds A7 clock domain support as M4 clock domain > will be handled by M4 seperately. > > Change Log: > v1->v2: > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers > * use clk_hw apis to register clocks > * use of_clk_add_hw_provider > * split the clocks register process into two parts: early part for > possible > timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part > for > the left normal peripheral clocks registered by a platform driver. > > Dong Aisheng (10): > clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support > clk: reparent orphans after critical clocks enabled > clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support > clk: imx: add pllv4 support > clk: imx: add pfdv2 support > clk: imx: add composite clk support > dt-bindings: clock: add imx7ulp clock binding doc > clk: imx: make mux parent strings const > clk: imx: implement new clk_hw based APIs > clk: imx: add imx7ulp clk driver > > .../devicetree/bindings/clock/imx7ulp-clock.txt | 62 ++++++ > drivers/clk/clk-divider.c | 100 ++++++++- > drivers/clk/clk-fractional-divider.c | 10 + > drivers/clk/clk.c | 39 ++-- > drivers/clk/imx/Makefile | 6 +- > drivers/clk/imx/clk-busy.c | 2 +- > drivers/clk/imx/clk-composite.c | 90 ++++++++ > drivers/clk/imx/clk-fixup-mux.c | 2 +- > drivers/clk/imx/clk-imx7ulp.c | 245 > +++++++++++++++++++++ > drivers/clk/imx/clk-pfdv2.c | 207 > +++++++++++++++++ > drivers/clk/imx/clk-pllv4.c | 188 ++++++++++++++++ > drivers/clk/imx/clk.c | 22 ++ > drivers/clk/imx/clk.h | 92 +++++++- > include/dt-bindings/clock/imx7ulp-clock.h | 108 +++++++++ > include/linux/clk-provider.h | 17 ++ > 15 files changed, 1159 insertions(+), 31 deletions(-) create mode 100644 > Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > create mode 100644 drivers/clk/imx/clk-composite.c create mode 100644 > drivers/clk/imx/clk-imx7ulp.c create mode 100644 drivers/clk/imx/clk- > pfdv2.c create mode 100644 drivers/clk/imx/clk-pllv4.c create mode > 100644 include/dt-bindings/clock/imx7ulp-clock.h > > -- > 2.7.4