From: york sun <york.sun@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding
Date: Mon, 30 Jan 2017 16:08:39 +0000 [thread overview]
Message-ID: <AM4PR0401MB17327557758CC80A60A6C5D19A4B0@AM4PR0401MB1732.eurprd04.prod.outlook.com> (raw)
In-Reply-To: 1485773754-29391-1-git-send-email-Ashish.Kumar@nxp.com
On 01/30/2017 02:56 AM, Ashish Kumar wrote:
> From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
>
> SerDes information is not necessary to be present in RCWSR29 register.
> It may vary from SoC to SoC.
>
> So Avoid RCWSR28 register hard-coding.
>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Ashish,
Please add your signature next time. Even it was created by Prabhakar,
you should sign it if you send it out.
> ---
> .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 28 +++++++++++--------
> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 ++++++
> 2 files changed, 25 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> index 601651a..af2684e 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> @@ -53,20 +53,22 @@ int is_serdes_configured(enum srds_prtcl device)
> int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
> {
> struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> - u32 cfg = gur_in32(&gur->rcwsr[28]);
> + u32 cfg = 0;
> int i;
>
> switch (sd) {
> #ifdef CONFIG_SYS_FSL_SRDS_1
> case FSL_SRDS_1:
> - cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
> - cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
> + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
> + cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
> + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
> break;
> #endif
> #ifdef CONFIG_SYS_FSL_SRDS_2
> case FSL_SRDS_2:
> - cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
> - cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
> + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
> + cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
> + cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
> break;
> #endif
> default:
> @@ -85,8 +87,8 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
> return -ENODEV;
> }
>
> -void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
> - u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
> +void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
> + u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
> {
> struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> u32 cfg;
> @@ -97,7 +99,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
>
> memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
>
> - cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
> + cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
> cfg >>= sd_prctl_shift;
> printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
>
> @@ -154,15 +156,17 @@ void fsl_serdes_init(void)
> #ifdef CONFIG_SYS_FSL_SRDS_1
> serdes_init(FSL_SRDS_1,
> CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
> - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK,
> - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT,
> + FSL_CHASSIS3_SRDS1_REGSR,
> + FSL_CHASSIS3_SRDS1_PRTCL_MASK,
> + FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
> serdes1_prtcl_map);
> #endif
> #ifdef CONFIG_SYS_FSL_SRDS_2
> serdes_init(FSL_SRDS_2,
> CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
> - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK,
> - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT,
> + FSL_CHASSIS3_SRDS2_REGSR,
> + FSL_CHASSIS3_SRDS2_PRTCL_MASK,
> + FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
> serdes2_prtcl_map);
> #endif
> }
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index 43ae686..5ea9130 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -232,10 +232,19 @@ struct ccsr_gur {
> #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
> #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
> #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
> +
> +#if defined(CONFIG_LS2080A)
We are switching to Kconfig macros. Use CONFIG_ARCH_LS2080A instead.
York
prev parent reply other threads:[~2017-01-30 16:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-30 10:55 [U-Boot] [PATCH] armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding Ashish Kumar
2017-01-30 16:08 ` york sun [this message]
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