From mboxrd@z Thu Jan 1 00:00:00 1970 From: york sun Date: Tue, 19 Jul 2016 16:01:49 +0000 Subject: [U-Boot] [PATCH 5/5] fsl-layerscape: Add workaround for PCIe erratum A010315 References: <1467613697-18128-1-git-send-email-Zhiqiang.Hou@nxp.com> <1467613697-18128-5-git-send-email-Zhiqiang.Hou@nxp.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 07/03/2016 11:39 PM, Zhiqiang Hou wrote: > From: Hou Zhiqiang > > As the access to serders protocol unselected PCIe controller will > hang. So disable the R/W permission to unselected PCIe controller > including its CCSR, IO space and memory space according to the > serders protocol field of RCW. > > Signed-off-by: Hou Zhiqiang > --- > Tested on LS1043ARDB, LS1021AQDS boards. > > arch/arm/cpu/armv7/ls102xa/soc.c | 14 ++++++++++++++ > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 16 ++++++++++++++++ > arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++ > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 ++++ > arch/arm/include/asm/arch-ls102xa/config.h | 1 + > arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 4 ++++ > board/freescale/ls1012aqds/ls1012aqds.c | 4 ++++ > board/freescale/ls1012ardb/ls1012ardb.c | 4 ++++ > board/freescale/ls1021aqds/ls1021aqds.c | 4 ++++ > board/freescale/ls1021atwr/ls1021atwr.c | 4 ++++ > board/freescale/ls1043aqds/ls1043aqds.c | 4 ++++ > board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++ > 12 files changed, 65 insertions(+) > Can you put the call of erratum_a010315() in an SoC file, instead of individual board file? York