From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752104AbdGGHDH (ORCPT ); Fri, 7 Jul 2017 03:03:07 -0400 Received: from mail-eopbgr10079.outbound.protection.outlook.com ([40.107.1.79]:20512 "EHLO EUR02-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751059AbdGGHDF (ORCPT ); Fri, 7 Jul 2017 03:03:05 -0400 From: Andy Duan To: Richard Leitner , "robh+dt@kernel.org" , "mark.rutland@arm.com" CC: "netdev@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "dev@g0hl1n.net" , Andrew Lunn Subject: RE: [PATCH 2/2] net: ethernet: fsl: add phy reset after clk enable option Thread-Topic: [PATCH 2/2] net: ethernet: fsl: add phy reset after clk enable option Thread-Index: AQHS9liVhz49Jf19SE+3rJ5oc5evWaJH0raAgAAKjoCAAASU8A== Date: Fri, 7 Jul 2017 07:03:01 +0000 Message-ID: References: <1499346330-12166-1-git-send-email-richard.leitner@skidata.com> <1499346330-12166-2-git-send-email-richard.leitner@skidata.com> <81105c77-d48f-271b-2de1-c877b9413184@skidata.com> In-Reply-To: <81105c77-d48f-271b-2de1-c877b9413184@skidata.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: skidata.com; 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spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Jul 2017 07:03:01.3374 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0401MB2258 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by nfs id v6773CZB003360 From: Richard Leitner Sent: Friday, July 07, 2017 1:51 PM >> Since it is common issue so long as using the PHY, can you move it into smsc >phy driver like in .smsc_phy_reset() function ? >> And get the reset pin from phy dts node. > >Some more points that come into my mind: > - The smsc_phy_reset function is registered as "soft_reset". Would it be OK to >use nRST in it? It is not reasonable. > - Would it be OK to call the phy_init_hw function from within the >smsc_phy_reset? No, phy_init_hw() already call .drv->soft_reset(). > - IMHO I'd have to move the reset gpio binding inside the phy node then. Isn't >that a pretty big change doing that for all PHYs/FECs? Would it be "worth" it? > To make the change to be common, there have big change for phy driver. Maybe somebody can give one good suggestion/solution for it. Andy