From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752507AbdEILNk (ORCPT ); Tue, 9 May 2017 07:13:40 -0400 Received: from mail-db5eur01on0076.outbound.protection.outlook.com ([104.47.2.76]:6976 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751574AbdEILNi (ORCPT ); Tue, 9 May 2017 07:13:38 -0400 From: Andy Duan To: "A.S. Dong" , "linux-serial@vger.kernel.org" CC: "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "gregkh@linuxfoundation.org" , "jslaby@suse.com" , "stefan@agner.ch" , Mingkai Hu , "Y.B. Lu" , "A.S. Dong" Subject: RE: [PATCH 0/6] tty: serial: lpuart: add imx7ulp support Thread-Topic: [PATCH 0/6] tty: serial: lpuart: add imx7ulp support Thread-Index: AQHSyJkGZQ0tYRd8tEyC/AV6xlZltqHr2RmQ Date: Tue, 9 May 2017 11:13:34 +0000 Message-ID: References: <1494316248-24052-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1494316248-24052-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=none action=none header.from=nxp.com; x-originating-ip: [199.59.231.64] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;AMSPR04MB309;7:sTRHUlXb6QSzKiXoetsmqVNjAYvDtyXRDohjiGxyMo2tk4dIRJgFgPUA6CPmhfOrwMYx0wXDOd5QmGi79VQfspTDsEFZCp2o4bpYDhPhUTYdBbe8+owg6brkDnD4PEInJummdM/4va72wnPlpg+gOvkGhwoK9TdRWNNgeXSM9DSwEVdHJXqI06cN0wp4Ei2wudjQbvyvWBCe+vytygu0CXbDDeDAdolXT27hECaICerjGB26mkQKzGTMp36LINuHSgI/g4Cgi4L3EMoR7PXHnJSXj4Hza7XoviY0wUqdGGzetzn7ffqCZKXwN3TIBoA7gOn8gBpcSDTc439SHsvOOQ== x-forefront-antispam-report: SFV:SKI;SCL:-1SFV:NSPM;SFS:(10009020)(6009001)(39450400003)(39840400002)(39860400002)(39410400002)(39400400002)(39850400002)(377454003)(74316002)(478600001)(5250100002)(229853002)(4326008)(189998001)(2900100001)(6506006)(2950100002)(2906002)(55016002)(54356999)(8676002)(9686003)(3660700001)(3280700002)(50986999)(5660300001)(86362001)(8936002)(305945005)(6436002)(76176999)(53936002)(66066001)(6116002)(3846002)(102836003)(81166006)(7736002)(99286003)(38730400002)(25786009)(33656002)(54906002);DIR:OUT;SFP:1101;SCL:1;SRVR:AMSPR04MB309;H:AM4PR0401MB2260.eurprd04.prod.outlook.com;FPR:;SPF:None;MLV:sfv;LANG:en; x-ms-office365-filtering-correlation-id: 1365867b-0735-4c61-d061-08d496cc6f0a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081)(201702281549075);SRVR:AMSPR04MB309; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(9452136761055)(185117386973197)(258649278758335); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040450)(601004)(2401047)(5005006)(8121501046)(3002001)(93006095)(93001095)(10201501046)(6055026)(6041248)(20161123562025)(20161123560025)(20161123555025)(20161123564025)(20161123558100)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(6072148);SRVR:AMSPR04MB309;BCL:0;PCL:0;RULEID:;SRVR:AMSPR04MB309; x-forefront-prvs: 0302D4F392 spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 09 May 2017 11:13:34.5386 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AMSPR04MB309 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v49BDoRe020641 From: Dong Aisheng Sent: Tuesday, May 09, 2017 3:51 PM >To: linux-serial@vger.kernel.org >Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; >gregkh@linuxfoundation.org; jslaby@suse.com; Andy Duan >; stefan@agner.ch; Mingkai Hu >; Y.B. Lu ; A.S. Dong > >Subject: [PATCH 0/6] tty: serial: lpuart: add imx7ulp support > >This patch series mainly intends to add imx7ulp support which is also using FSL >lpuart. > >The lpuart in imx7ulp is basically the same as ls1021a. It's also >32 bit width register, but unlike ls1021a, it's little endian. >Besides that, imx7ulp lpuart has a minor different register layout from ls1021a >that it has four extra registers (verid, param, global, >pincfg) located at the beginning of register map, which are currently not used >by the driver and less to be used later. > >Furthermore, this patch serial also add a new more accurate baud rate >calculation method as MX7ULP can't divide a suitable baud rate with the >default setting. > >Currently the new baud rate calculation is only enabled on MX7ULP. >However, i guess the Layerscape may also be able to use it as there seems to >be no difference in baud rate setting register after checking the Layerscape >Reference Manual. > >As i don't have Layerscape boards, i can't test it, so i only enable it for MX7ULP >by default to avoid a potential break. > >I copied LayerScape guys in this series and hope they can help test later. >If it works on Layerscape as well, then they can switch to the new setting too >and totally remove the old stuff. > >Dong Aisheng (6): > tty: serial: lpuart: introduce lpuart_soc_data to represent SoC > property > tty: serial: lpuart: add little endian 32 bit register support > dt-bindings: serial: fsl-lpuart: add i.MX7ULP support > tty: serial: lpuart: add imx7ulp support > tty: serial: lpuart: add earlycon support for imx7ulp > tty: serial: lpuart: add a more accurate baud rate calculation method > > .../devicetree/bindings/serial/fsl-lpuart.txt | 2 + > drivers/tty/serial/fsl_lpuart.c | 149 ++++++++++++++++++--- > 2 files changed, 136 insertions(+), 15 deletions(-) > >-- >2.7.4 The series looks fine. Acked-by: Fugang Duan From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Duan Subject: RE: [PATCH 0/6] tty: serial: lpuart: add imx7ulp support Date: Tue, 9 May 2017 11:13:34 +0000 Message-ID: References: <1494316248-24052-1-git-send-email-aisheng.dong@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <1494316248-24052-1-git-send-email-aisheng.dong@nxp.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: "linux-serial@vger.kernel.org" Cc: "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "gregkh@linuxfoundation.org" , "jslaby@suse.com" , "stefan@agner.ch" , Mingkai Hu , "Y.B. Lu" , "A.S. Dong" List-Id: linux-serial@vger.kernel.org From: Dong Aisheng Sent: Tuesday, May 09, 2017 3:51 = PM >To: linux-serial@vger.kernel.org >Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; >gregkh@linuxfoundation.org; jslaby@suse.com; Andy Duan >; stefan@agner.ch; Mingkai Hu >; Y.B. Lu ; A.S. Dong > >Subject: [PATCH 0/6] tty: serial: lpuart: add imx7ulp support > >This patch series mainly intends to add imx7ulp support which is also usin= g FSL >lpuart. > >The lpuart in imx7ulp is basically the same as ls1021a. It's also >32 bit width register, but unlike ls1021a, it's little endian. >Besides that, imx7ulp lpuart has a minor different register layout from ls= 1021a >that it has four extra registers (verid, param, global, >pincfg) located at the beginning of register map, which are currently not = used >by the driver and less to be used later. > >Furthermore, this patch serial also add a new more accurate baud rate >calculation method as MX7ULP can't divide a suitable baud rate with the >default setting. > >Currently the new baud rate calculation is only enabled on MX7ULP. >However, i guess the Layerscape may also be able to use it as there seems = to >be no difference in baud rate setting register after checking the Layersca= pe >Reference Manual. > >As i don't have Layerscape boards, i can't test it, so i only enable it fo= r MX7ULP >by default to avoid a potential break. > >I copied LayerScape guys in this series and hope they can help test later. >If it works on Layerscape as well, then they can switch to the new setting= too >and totally remove the old stuff. > >Dong Aisheng (6): > tty: serial: lpuart: introduce lpuart_soc_data to represent SoC > property > tty: serial: lpuart: add little endian 32 bit register support > dt-bindings: serial: fsl-lpuart: add i.MX7ULP support > tty: serial: lpuart: add imx7ulp support > tty: serial: lpuart: add earlycon support for imx7ulp > tty: serial: lpuart: add a more accurate baud rate calculation method > > .../devicetree/bindings/serial/fsl-lpuart.txt | 2 + > drivers/tty/serial/fsl_lpuart.c | 149 ++++++++++++++++= ++--- > 2 files changed, 136 insertions(+), 15 deletions(-) > >-- >2.7.4 The series looks fine. Acked-by: Fugang Duan From mboxrd@z Thu Jan 1 00:00:00 1970 From: fugang.duan@nxp.com (Andy Duan) Date: Tue, 9 May 2017 11:13:34 +0000 Subject: [PATCH 0/6] tty: serial: lpuart: add imx7ulp support In-Reply-To: <1494316248-24052-1-git-send-email-aisheng.dong@nxp.com> References: <1494316248-24052-1-git-send-email-aisheng.dong@nxp.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Dong Aisheng Sent: Tuesday, May 09, 2017 3:51 PM >To: linux-serial at vger.kernel.org >Cc: linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; >gregkh at linuxfoundation.org; jslaby at suse.com; Andy Duan >; stefan at agner.ch; Mingkai Hu >; Y.B. Lu ; A.S. Dong > >Subject: [PATCH 0/6] tty: serial: lpuart: add imx7ulp support > >This patch series mainly intends to add imx7ulp support which is also using FSL >lpuart. > >The lpuart in imx7ulp is basically the same as ls1021a. It's also >32 bit width register, but unlike ls1021a, it's little endian. >Besides that, imx7ulp lpuart has a minor different register layout from ls1021a >that it has four extra registers (verid, param, global, >pincfg) located at the beginning of register map, which are currently not used >by the driver and less to be used later. > >Furthermore, this patch serial also add a new more accurate baud rate >calculation method as MX7ULP can't divide a suitable baud rate with the >default setting. > >Currently the new baud rate calculation is only enabled on MX7ULP. >However, i guess the Layerscape may also be able to use it as there seems to >be no difference in baud rate setting register after checking the Layerscape >Reference Manual. > >As i don't have Layerscape boards, i can't test it, so i only enable it for MX7ULP >by default to avoid a potential break. > >I copied LayerScape guys in this series and hope they can help test later. >If it works on Layerscape as well, then they can switch to the new setting too >and totally remove the old stuff. > >Dong Aisheng (6): > tty: serial: lpuart: introduce lpuart_soc_data to represent SoC > property > tty: serial: lpuart: add little endian 32 bit register support > dt-bindings: serial: fsl-lpuart: add i.MX7ULP support > tty: serial: lpuart: add imx7ulp support > tty: serial: lpuart: add earlycon support for imx7ulp > tty: serial: lpuart: add a more accurate baud rate calculation method > > .../devicetree/bindings/serial/fsl-lpuart.txt | 2 + > drivers/tty/serial/fsl_lpuart.c | 149 ++++++++++++++++++--- > 2 files changed, 136 insertions(+), 15 deletions(-) > >-- >2.7.4 The series looks fine. Acked-by: Fugang Duan