From mboxrd@z Thu Jan 1 00:00:00 1970 From: Nipun Gupta Subject: Re: [PATCH v2 15/15] app/test: add unit tests for SW eventdev driver Date: Wed, 8 Feb 2017 18:02:26 +0000 Message-ID: References: <1484580885-148524-1-git-send-email-harry.van.haaren@intel.com> <1485879273-86228-1-git-send-email-harry.van.haaren@intel.com> <1485879273-86228-16-git-send-email-harry.van.haaren@intel.com> <20170208102306.GA19597@localhost.localdomain> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Cc: "dev@dpdk.org" , Bruce Richardson , David Hunt , "Hemant Agrawal" , "gage.eads@intel.com" To: Jerin Jacob , Harry van Haaren Return-path: Received: from EUR03-AM5-obe.outbound.protection.outlook.com (mail-eopbgr30055.outbound.protection.outlook.com [40.107.3.55]) by dpdk.org (Postfix) with ESMTP id D9F49282 for ; Wed, 8 Feb 2017 19:02:28 +0100 (CET) In-Reply-To: <20170208102306.GA19597@localhost.localdomain> Content-Language: en-US List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > Sent: Wednesday, February 08, 2017 15:53 > To: Harry van Haaren > Cc: dev@dpdk.org; Bruce Richardson ; David > Hunt ; Nipun Gupta ; Hemant > Agrawal ; gage.eads@intel.com > Subject: Re: [PATCH v2 15/15] app/test: add unit tests for SW eventdev dr= iver >=20 > On Tue, Jan 31, 2017 at 04:14:33PM +0000, Harry van Haaren wrote: > > From: Bruce Richardson > > > > Since the sw driver is a standalone lookaside device that has no HW > > requirements, we can provide a set of unit tests that test its > > functionality across the different queue types and with different input > > scenarios. > > >=20 > Thanks for SW driver specific test cases. It provided me a good insight > of expected application behavior from SW driver perspective and in turn i= t > created > some challenge in portable applications. >=20 > I would like highlight a main difference between the implementation and g= et a > consensus on how to abstract it? >=20 > Based on existing header file, We can do event pipelining in two differen= t ways > a) Flow-based event pipelining > b) queue_id based event pipelining >=20 > I will provide an example to showcase application flow in both modes. > Based on my understanding from SW driver source code, it supports only > queue_id based event pipelining. I guess, Flow based event pipelining wil= l > work semantically with SW driver but it will be very slow. >=20 > I think, the reason for the difference is the capability of the context d= efinition. > SW model the context is - queue_id > Cavium HW model the context is queue_id + flow_id + sub_event_type + > event_type >=20 > AFAIK, queue_id based event pipelining will work with NXP HW but I am not > sure about flow based event pipelining model with NXP HW. Appreciate any > input this? [Nipun] Yes Jerin, that's right. NXP HW will not be suitable for flow based= event pipelining. >=20 > In Cavium HW, We support both modes. >=20 > As an open question, Should we add a capability flag to advertise the sup= ported > models and let application choose the model based on implementation > capability. The > downside is, a small portion of stage advance code will be different but = we > can reuse the STAGE specific application code(I think it a fair > trade off) >=20 > Bruce, Harry, Gage, Hemant, Nipun > Thoughts? Or any other proposal? >=20 > I will take an non trivial realworld NW use case show the difference. > A standard IPSec outbound processing will have minimum 4 to 5 stages >=20 > stage_0: > -------- > a) Takes the pkts from ethdev and push to eventdev as > RTE_EVENT_OP_NEW > b) Some HW implementation, This will be done by HW. In SW implementation > it done by service cores >=20 > stage_1:(ORDERED) > ------------------ > a) Receive pkts from stage_0 in ORDERED flow and it process in parallel o= n N > of cores > b) Find a SA belongs that packet move to next stage for SA specific > outbound operations.Outbound processing starts with updating the > sequence number in the critical section and followed by packet encryption= in > parallel. >=20 > stage_2(ATOMIC) based on SA > ---------------------------- > a) Update the sequence number and move to ORDERED sched_type for packet > encryption in parallel >=20 > stage_3(ORDERED) based on SA > ---------------------------- > a) Encrypt the packets in parallel > b) Do output route look-up and figure out tx port and queue to transmit > the packet > c) Move to ATOMIC stage based on tx port and tx queue_id to transmit > the packet _without_ losing the ingress ordering >=20 > stage_4(ATOMIC) based on tx port/tx queue > ----------------------------------------- > a) enqueue the encrypted packet to ethdev tx port/tx_queue >=20 >=20 > 1) queue_id based event pipelining > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D >=20 > stage_1_work(assigned to event queue 1)# N ports/N cores establish > link to queue 1 through rte_event_port_link() >=20 > on_each_cores_linked_to_queue1(stage1) > while(1) > { > /* STAGE 1 processing */ > nr_events =3D rte_event_dequeue_burst(ev,..); > if (!nr_events); > continue; >=20 > sa =3D find_sa_from_packet(ev.mbuf); >=20 > /* move to next stage(ATOMIC) */ > ev.event_type =3D RTE_EVENT_TYPE_CPU; > ev.sub_event_type =3D 2; > ev.sched_type =3D RTE_SCHED_TYPE_ATOMIC; > ev.flow_id =3D sa; > ev.op =3D RTE_EVENT_OP_FORWARD; > ev.queue_id =3D 2; > /* move to stage 2(event queue 2) */ > rte_event_enqueue_burst(ev,..); > } >=20 > on_each_cores_linked_to_queue2(stage2) > while(1) > { > /* STAGE 2 processing */ > nr_events =3D rte_event_dequeue_burst(ev,..); > if (!nr_events); > continue; >=20 > sa_specific_atomic_processing(sa /* ev.flow_id */);/* seq= number > update in critical section */ >=20 > /* move to next stage(ORDERED) */ > ev.event_type =3D RTE_EVENT_TYPE_CPU; > ev.sub_event_type =3D 3; > ev.sched_type =3D RTE_SCHED_TYPE_ORDERED; > ev.flow_id =3D sa; [Nipun] Queue1 has flow_id as an 'sa' with sched_type as RTE_SCHED_TYPE_ATO= MIC and Queue2 has same flow_id but with sched_type as RTE_SCHED_TYPE_ORDERED. Does this mean that same flow_id be associated with separate RTE_SCHED_TYPE= _* as sched_type? My understanding is that one flow can either be parallel or atomic or order= ed. The rte_eventdev.h states that sched_type is associated with flow_id, which= also seems legitimate: uint8_t sched_type:2; /**< Scheduler synchronization type (RTE_SCHED_TYPE_*) * associated with flow id on a given event queue * for the enqueue and dequeue operation. */ > ev.op =3D RTE_EVENT_OP_FORWARD; > ev.queue_id =3D 3; > /* move to stage 3(event queue 3) */ > rte_event_enqueue_burst(ev,..); > } >=20 > on_each_cores_linked_to_queue3(stage3) > while(1) > { > /* STAGE 3 processing */ > nr_events =3D rte_event_dequeue_burst(ev,..); > if (!nr_events); > continue; >=20 > sa_specific_ordered_processing(sa /*ev.flow_id */);/* pac= kets > encryption in parallel */ >=20 > /* move to next stage(ATOMIC) */ > ev.event_type =3D RTE_EVENT_TYPE_CPU; > ev.sub_event_type =3D 4; > ev.sched_type =3D RTE_SCHED_TYPE_ATOMIC; > output_tx_port_queue =3D > find_output_tx_queue_and_tx_port(ev.mbuff); > ev.flow_id =3D output_tx_port_queue; > ev.op =3D RTE_EVENT_OP_FORWARD; > ev.queue_id =3D 4; > /* move to stage 4(event queue 4) */ > rte_event_enqueue_burst(ev,...); > } >=20 > on_each_cores_linked_to_queue4(stage4) > while(1) > { > /* STAGE 4 processing */ > nr_events =3D rte_event_dequeue_burst(ev,..); > if (!nr_events); > continue; >=20 > rte_eth_tx_buffer(); > } >=20 > 2) flow-based event pipelining > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D >=20 > - No need to partition queues for different stages > - All the cores can operate on all the stages, Thus enables > automatic multicore scaling, true dynamic load balancing, > - Fairly large number of SA(kind of 2^16 to 2^20) can be processed in par= allel > Something existing IPSec application has constraints on > http://dpdk.org/doc/guides-16.04/sample_app_ug/ipsec_secgw.html >=20 > on_each_worker_cores() > while(1) > { > rte_event_dequeue_burst(ev,..) > if (!nr_events); > continue; >=20 > /* STAGE 1 processing */ > if(ev.event_type =3D=3D RTE_EVENT_TYPE_ETHDEV) { > sa =3D find_it_from_packet(ev.mbuf); > /* move to next stage2(ATOMIC) */ > ev.event_type =3D RTE_EVENT_TYPE_CPU; > ev.sub_event_type =3D 2; > ev.sched_type =3D RTE_SCHED_TYPE_ATOMIC; > ev.flow_id =3D sa; > ev.op =3D RTE_EVENT_OP_FORWARD; > rte_event_enqueue_burst(ev..); >=20 > } else if(ev.event_type =3D=3D RTE_EVENT_TYPE_CPU && > ev.sub_event_type =3D=3D 2) { /* stage 2 */ [Nipun] I didn't got that in this case on which event queue (and eventually its associated event ports) will the RTE_EVENT_TYPE_CPU type events be rece= ived on? Adding on to what Harry also mentions in other mail, If same code is run in= the case you mentioned in '#1 - queue_id based event pipelining', after specifying the e= v.queue_id with appropriate value then also #1 would be good. Isn't it? >=20 > sa_specific_atomic_processing(sa /* ev.flow_id */);/* seq > number update in critical section */ > /* move to next stage(ORDERED) */ > ev.event_type =3D RTE_EVENT_TYPE_CPU; > ev.sub_event_type =3D 3; > ev.sched_type =3D RTE_SCHED_TYPE_ORDERED; > ev.flow_id =3D sa; > ev.op =3D RTE_EVENT_OP_FORWARD; > rte_event_enqueue_burst(ev,..); >=20 > } else if(ev.event_type =3D=3D RTE_EVENT_TYPE_CPU && > ev.sub_event_type =3D=3D 3) { /* stage 3 */ >=20 > sa_specific_ordered_processing(sa /* ev.flow_id */);/* like > encrypting packets in parallel */ > /* move to next stage(ATOMIC) */ > ev.event_type =3D RTE_EVENT_TYPE_CPU; > ev.sub_event_type =3D 4; > ev.sched_type =3D RTE_SCHED_TYPE_ATOMIC; > output_tx_port_queue =3D > find_output_tx_queue_and_tx_port(ev.mbuff); > ev.flow_id =3D output_tx_port_queue; > ev.op =3D RTE_EVENT_OP_FORWARD; > rte_event_enqueue_burst(ev,..); >=20 > } else if(ev.event_type =3D=3D RTE_EVENT_TYPE_CPU && > ev.sub_event_type =3D=3D 4) { /* stage 4 */ > rte_eth_tx_buffer(); > } > } >=20 > /Jerin > Cavium