All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: Joao Pinto <Joao.Pinto@synopsys.com>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"jingoohan1@gmail.com" <jingoohan1@gmail.com>
Cc: "M.h. Lian" <minghuan.lian@nxp.com>,
	Mingkai Hu <mingkai.hu@nxp.com>, "Roy Zang" <roy.zang@nxp.com>,
	"niklas.cassel@axis.com" <niklas.cassel@axis.com>,
	"jesper.nilsson@axis.com" <jesper.nilsson@axis.com>
Subject: RE: [PATCHv3 6/9] PCI: designware: add accessors for write permission of DBI read-only registers
Date: Mon, 21 Aug 2017 03:21:52 +0000	[thread overview]
Message-ID: <AM5PR0402MB2771AA0E2C85C5575FAD846384870@AM5PR0402MB2771.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <f8c8589e-ebc2-c618-e1cb-2c134c756a77@synopsys.com>

SGkgSm9hbywNCg0KVGhhbmtzIGEgbG90IGZvciB5b3VyIGZlZWRiYWNrIQ0KDQo+IC0tLS0tT3Jp
Z2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEpvYW8gUGludG8gW21haWx0bzpKb2FvLlBpbnRv
QHN5bm9wc3lzLmNvbV0NCj4gU2VudDogMjAxN+W5tDjmnIgxOOaXpSAxOTo1MQ0KPiBUbzogWi5x
LiBIb3UgPHpoaXFpYW5nLmhvdUBueHAuY29tPjsgU3RhbmltaXIgVmFyYmFub3YNCj4gPHN2YXJi
YW5vdkBtbS1zb2wuY29tPjsgbGludXgtcGNpQHZnZXIua2VybmVsLm9yZzsNCj4gYmhlbGdhYXNA
Z29vZ2xlLmNvbTsgamluZ29vaGFuMUBnbWFpbC5jb207IEpvYW8uUGludG9Ac3lub3BzeXMuY29t
DQo+IENjOiBNLmguIExpYW4gPG1pbmdodWFuLmxpYW5AbnhwLmNvbT47IE1pbmdrYWkgSHUgPG1p
bmdrYWkuaHVAbnhwLmNvbT47DQo+IFJveSBaYW5nIDxyb3kuemFuZ0BueHAuY29tPjsgbmlrbGFz
LmNhc3NlbEBheGlzLmNvbTsNCj4gamVzcGVyLm5pbHNzb25AYXhpcy5jb20NCj4gU3ViamVjdDog
UmU6IFtQQVRDSHYzIDYvOV0gUENJOiBkZXNpZ253YXJlOiBhZGQgYWNjZXNzb3JzIGZvciB3cml0
ZQ0KPiBwZXJtaXNzaW9uIG9mIERCSSByZWFkLW9ubHkgcmVnaXN0ZXJzDQo+IA0KPiBIaSBaaGlx
aWFuZyBhbmQgU3RhbmltaXIsDQo+IA0KPiDDgHMgNDowMyBBTSBkZSA4LzE3LzIwMTcsIFoucS4g
SG91IGVzY3JldmV1Og0KPiA+IEhpIFN0YW5pbWlyLA0KPiA+DQo+ID4gVGhhbmtzIGZvciB5b3Vy
IGZlZWRiYWNrIQ0KPiA+DQo+ID4+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+ID4+IEZy
b206IFN0YW5pbWlyIFZhcmJhbm92IFttYWlsdG86c3ZhcmJhbm92QG1tLXNvbC5jb21dDQo+ID4+
IFNlbnQ6IDIwMTflubQ45pyIMTbml6UgMTk6MzQNCj4gPj4gVG86IFoucS4gSG91IDx6aGlxaWFu
Zy5ob3VAbnhwLmNvbT47IGxpbnV4LXBjaUB2Z2VyLmtlcm5lbC5vcmc7DQo+ID4+IGJoZWxnYWFz
QGdvb2dsZS5jb207IGppbmdvb2hhbjFAZ21haWwuY29tOw0KPiBKb2FvLlBpbnRvQHN5bm9wc3lz
LmNvbQ0KPiA+PiBDYzogTS5oLiBMaWFuIDxtaW5naHVhbi5saWFuQG54cC5jb20+OyBNaW5na2Fp
IEh1DQo+ID4+IDxtaW5na2FpLmh1QG54cC5jb20+OyBSb3kgWmFuZyA8cm95LnphbmdAbnhwLmNv
bT47DQo+ID4+IG5pa2xhcy5jYXNzZWxAYXhpcy5jb207IGplc3Blci5uaWxzc29uQGF4aXMuY29t
DQo+ID4+IFN1YmplY3Q6IFJlOiBbUEFUQ0h2MyA2LzldIFBDSTogZGVzaWdud2FyZTogYWRkIGFj
Y2Vzc29ycyBmb3Igd3JpdGUNCj4gPj4gcGVybWlzc2lvbiBvZiBEQkkgcmVhZC1vbmx5IHJlZ2lz
dGVycw0KPiA+Pg0KPiA+PiBIaSwNCj4gPj4NCj4gPj4gT24gMDgvMTYvMjAxNyAwNzo1NiBBTSwg
WmhpcWlhbmcgSG91IHdyb3RlOg0KPiA+Pj4gRnJvbTogSG91IFpoaXFpYW5nIDxaaGlxaWFuZy5I
b3VAbnhwLmNvbT4NCj4gPj4+DQo+ID4+PiBUaGUgcmVhZC1vbmx5IERCSSByZWdpc3RlcnMgY2Fu
IGJlIHdyaXR0ZW4gb3ZlciB0aGUgREJJIHdoZW4gc2V0IHRoZQ0KPiA+Pj4gIldyaXRlIHRvIFJP
IFJlZ2lzdGVycyBVc2luZyBEQkkiIChEQklfUk9fV1JfRU4pIGZpZWxkIG9mIHRoZQ0KPiA+Pj4g
TUlTQ19DT05UUk9MXzFfT0ZGIHJlZ2lzdGVyLg0KPiA+Pj4NCj4gPj4+IFNpZ25lZC1vZmYtYnk6
IEhvdSBaaGlxaWFuZyA8WmhpcWlhbmcuSG91QG54cC5jb20+DQo+ID4+PiAtLS0NCj4gPj4+IFYz
Og0KPiA+Pj4gIC0gTm8gY2hhbmdlDQo+ID4+Pg0KPiA+Pj4gIGRyaXZlcnMvcGNpL2R3Yy9wY2ll
LWRlc2lnbndhcmUuaCB8IDI1ICsrKysrKysrKysrKysrKysrKysrKysrKysNCj4gPj4+ICAxIGZp
bGUgY2hhbmdlZCwgMjUgaW5zZXJ0aW9ucygrKQ0KPiA+Pj4NCj4gPj4+IGRpZmYgLS1naXQgYS9k
cml2ZXJzL3BjaS9kd2MvcGNpZS1kZXNpZ253YXJlLmgNCj4gPj4+IGIvZHJpdmVycy9wY2kvZHdj
L3BjaWUtZGVzaWdud2FyZS5oDQo+ID4+PiBpbmRleCA3MzY2YzgxLi4wYzVmODc0IDEwMDY0NA0K
PiA+Pj4gLS0tIGEvZHJpdmVycy9wY2kvZHdjL3BjaWUtZGVzaWdud2FyZS5oDQo+ID4+PiArKysg
Yi9kcml2ZXJzL3BjaS9kd2MvcGNpZS1kZXNpZ253YXJlLmgNCj4gPj4+IEBAIC03Niw2ICs3Niw5
IEBADQo+ID4+PiAgI2RlZmluZSBQQ0lFX0FUVV9GVU5DKHgpCQkoKCh4KSAmIDB4NykgPDwgMTYp
DQo+ID4+PiAgI2RlZmluZSBQQ0lFX0FUVV9VUFBFUl9UQVJHRVQJCTB4OTFDDQo+ID4+Pg0KPiA+
Pj4gKyNkZWZpbmUgUENJRV9NSVNDX0NPTlRST0xfMV9PRkYJCTB4OEJDDQo+ID4+PiArI2RlZmlu
ZSBQQ0lFX0RCSV9ST19XUl9FTgkJKDB4MSA8PCAwKQ0KPiA+Pg0KPiA+PiBEb2VzIHRob3NlIHJl
Z2lzdGVycyBleGlzdCBmb3IgZHdjIHZlcnNpb24gNC4wMWE/DQo+ID4NCj4gPiBKb2FvLCBjYW4g
eW91IGhlbHAgdG8gY2hlY2sgdGhpcz8NCj4gPiBJIHJlZmVycmVkIHRvIERlc2lnbldhcmUgY29y
ZXMgUENJIEV4cHJlc3MgY29udHJvbGxlciBkYXRhYm9vayB2ZXJzaW9uDQo+IDQuMjFhLg0KPiA+
IFRoZSBGcmVlc2NhbGUgTGF5ZXJzY2FwZSBpbXBsZW1lbnQgZG9lcyBub3QgZXhwb3J0IHRoZSB2
ZXJzaW9uIG9mDQo+IGRlc2lnbndhcmUgUENJZSBjb250cm9sbGVyLCBJIGRvbid0IGtub3cgd2hp
Y2ggdmVyc2lvbnMgaGF2ZSB0aG9zZSByZWdpc3RlcnMsDQo+IGlmIGl0IGRvZXMgbm90IHdvcmsg
b24gcWNvbSBwbGF0Zm9ybSwgSSB3aWxsIHJlbW92ZSB0aGUgcWNvbSByZWxhdGVkIGNoYW5nZXMu
DQo+IA0KPiBJIGNhbiBxdWVyeSB0aGUgUiZELCBidXQgSSB0aGluayBpdCB3b24ndCBiZSB2ZXJ5
IHVzZWZ1bCBzaW5jZSB0aGUgcWNvbScgU29DIGRvDQo+IG5vdCBpbXBsZW1lbnQgdGhlIHJlZ2lz
dGVycyAoaWYgdGhleSBhY3R1YWxseSBleGlzdCkuIEkgdGhpbmsgdGhlIGJlc3Qgd2F5IGlzIG5v
dCB0bw0KPiB1c2UgdGhpcyBpbiBxY29tJyBTb0MgKG1heWJlIG90aGVycyBzaG91bGQgbWFrZSBz
dXJlIHRoZWlyIFNvQ3MgY29udGFpbiB0aGVzZQ0KPiByZWdpc3RlcnMpLg0KDQpHb3QgaXQsIHdp
bGwgZHJvcCB0aGUgY2hhbmdlcyBvZiBxY29tIHBjaWUuDQoNClRoYW5rcywNClpoaXFpYW5nDQo=

  reply	other threads:[~2017-08-21  3:21 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-16  4:56 [PATCHv3 0/9] PCI: dwc: refactor ls-pcie ->host_init() and fix bug for dw_pcie_setup_rc Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 1/9] PCI: layerscape: Add dw_pcie_setup_rc to ls-pcie common host init Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 2/9] PCI: layerscape: move STRFMR1 access out from the DBI write-enable bracket Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 3/9] PCI: layerscape: add class code and multifunction fixups for ls1021a Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 4/9] PCI: layerscape: refactor the host_init function Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 5/9] PCI: layerscape: Disable the outbound windows configured by bootloader Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 6/9] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou
2017-08-16 11:33   ` Stanimir Varbanov
2017-08-17  3:03     ` Z.q. Hou
2017-08-17 11:25       ` Stanimir Varbanov
2017-08-18  5:28         ` Z.q. Hou
2017-08-18 11:51       ` Joao Pinto
2017-08-21  3:21         ` Z.q. Hou [this message]
2017-08-16  4:56 ` [PATCHv3 7/9] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 8/9] PCI: designware: enable write permission before updating DBI RO registers Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 9/9] PCI: dwc: remove the obsolete fixups Zhiqiang Hou

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=AM5PR0402MB2771AA0E2C85C5575FAD846384870@AM5PR0402MB2771.eurprd04.prod.outlook.com \
    --to=zhiqiang.hou@nxp.com \
    --cc=Joao.Pinto@synopsys.com \
    --cc=bhelgaas@google.com \
    --cc=jesper.nilsson@axis.com \
    --cc=jingoohan1@gmail.com \
    --cc=linux-pci@vger.kernel.org \
    --cc=minghuan.lian@nxp.com \
    --cc=mingkai.hu@nxp.com \
    --cc=niklas.cassel@axis.com \
    --cc=roy.zang@nxp.com \
    --cc=svarbanov@mm-sol.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.