From mboxrd@z Thu Jan  1 00:00:00 1970
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Date: Tue, 3 Dec 2019 02:32:18 +0000
Subject: [U-Boot] [EXT] Re: [PATCHv2 1/2] PCI: layerscape: Add Support
 for ls2088 PCIe EP mode
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Hi Ramon,

Do you have any comments about this? Thanks a lot.

Best regards
Xiaowei

From: Xiaowei Bao
Sent: 2019年11月26日 10:52
To: Ramon Fried <ramon.fried@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>; M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>; u-boot at lists.denx.de
Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode

H Ramon,

Thanks for your comments.
If we reimplement the PCIe EP driver base on PCIe UCLASS, we must test it in u-boot, but I have no idea how to test the actual device, do I need to implement our own test case, how to verify the cadence-ep actual device?

Best regards
Xiaowei


From: Ramon Fried <ramon.fried at gmail.com<mailto:ramon.fried@gmail.com>>
Sent: 2019年11月25日 20:15
To: Xiaowei Bao <xiaowei.bao at nxp.com<mailto:xiaowei.bao@nxp.com>>
Cc: Bin Meng <bmeng.cn at gmail.com<mailto:bmeng.cn@gmail.com>>; Simon Glass <sjg at chromium.org<mailto:sjg@chromium.org>>; M.h. Lian <minghuan.lian at nxp.com<mailto:minghuan.lian@nxp.com>>; Z.q. Hou <zhiqiang.hou at nxp.com<mailto:zhiqiang.hou@nxp.com>>; Mingkai Hu <mingkai.hu at nxp.com<mailto:mingkai.hu@nxp.com>>; Hongbo Wang <hongbo.wang at nxp.com<mailto:hongbo.wang@nxp.com>>; York Sun <york.sun at nxp.com<mailto:york.sun@nxp.com>>; u-boot at lists.denx.de<mailto:u-boot@lists.denx.de>
Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode



Hi Ramon,

I need your help on this, could you help explain how to start the PCIe EP test in
u-boot? Thanks a lot.
Hi, you just need to run the test suite and it will test the PCIe EP sandbox class automatically.
See test/README
Why do you care about the EP testing, it's testing the PCIe UCLASS implementation.
To test your implementation you need to test on actual device.
Thanks,
Ramon.