From mboxrd@z Thu Jan 1 00:00:00 1970 From: Xiaowei Bao Date: Wed, 20 Nov 2019 03:27:53 +0000 Subject: [U-Boot] [EXT] Re: [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode In-Reply-To: References: <20190516110408.45169-1-xiaowei.bao@nxp.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de > -----Original Message----- > From: Ramon Fried > Sent: 2019年11月20日 2:50 > To: Xiaowei Bao > Cc: Bin Meng ; Simon Glass ; > M.h. Lian ; Z.q. Hou ; > Mingkai Hu ; Hongbo Wang > ; York Sun ; > u-boot at lists.denx.de > Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support > for ls2088 PCIe EP mode > > On Tue, Nov 19, 2019 at 5:27 AM Xiaowei Bao > wrote: > > > > > > > > > -----Original Message----- > > > From: Xiaowei Bao > > > Sent: 2019年5月22日 18:19 > > > To: Bin Meng ; Ramon Fried > > > ; Simon Glass > > > Cc: M.h. Lian ; Z.q. Hou > > > ; Mingkai Hu ; Hongbo > Wang > > > ; York Sun ; > > > u-boot at lists.denx.de; Jiafei Pan > > > Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add > > > Support for ls2088 PCIe EP mode > > > > > > Hi Bin, > > > > > > -----Original Message----- > > > From: Bin Meng > > > Sent: 2019年5月17日 10:31 > > > To: Xiaowei Bao ; Ramon Fried > > > ; Simon Glass > > > Cc: M.h. Lian ; Z.q. Hou > > > ; Mingkai Hu ; Hongbo > Wang > > > ; York Sun ; > > > u-boot at lists.denx.de; Jiafei Pan > > > Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add > > > Support for ls2088 PCIe EP mode > > > > > > Caution: EXT Email > > > > > > Hi Xiaowei, > > > > > > On Fri, May 17, 2019 at 10:23 AM Xiaowei Bao > > > wrote: > > > > > > > > > > > > > > > > -----Original Message----- > > > > From: Bin Meng > > > > Sent: 2019年5月16日 19:58 > > > > To: Xiaowei Bao > > > > Cc: M.h. Lian ; Z.q. Hou > > > > ; Mingkai Hu ; Hongbo > > > Wang > > > > ; York Sun ; > > > > u-boot at lists.denx.de; Jiafei Pan > > > > Subject: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add > > > > Support for ls2088 PCIe EP mode > > > > > > > > Caution: EXT Email > > > > > > > > Hi, > > > > > > > > On Thu, May 16, 2019 at 7:02 PM Xiaowei Bao > > > wrote: > > > > > > > > > > From: Xiaowei Bao > > > > > > > > > > Signed-off-by: hongbo.wang > > > > > Signed-off-by: Minghuan Lian > > > > > Signed-off-by: Xiaowei Bao > > > > > --- > > > > > v2: > > > > > - Add the NXP copyright and make the function readability. > > > > > > > > > > drivers/pci/pcie_layerscape.c | 117 > > > +++++++++++++++++++++++++++-------------- > > > > > drivers/pci/pcie_layerscape.h | 19 +++++-- > > > > > 2 files changed, 91 insertions(+), 45 deletions(-) > > > > > > > > > > > > > Could you please support the PCIe EP mode using driver model? > > > > [Xiaowei Bao] do you mean that add a EP driver model to separate > > > > the RC > > > and EP with their respective drivers? > > > > > > That's correct. > > > > > > > The purpose of adding EP support under u-boot is to configure the > > > > size of the > > > BAR when the PCIE controller is used as an EP device, and to ensure > > > that the configuration space of the EP can be accessed, so that when > > > the RC scans the bus, the EP device can be scanned, and we also can > > > do simple MEM read and write verification through the md command in > u-boot shell. > > > > When entering the kernel, the kernel has its own PCIE EP > > > > framework, which > > > will reinitialize the EP device, contain of the inbound and outbound > > > window configure, MSI configuration and so no. > > > > > > > > > > It's not kernel PCIe EP framework. Ramon Fried recently added PCIe > > > EP uclass support to U-Boot and you should add NXP layerscape PCIe > > > EP driver using the new EP uclass. > > > [Xiaowei Bao] OK, thanks, I will add NXP layerscape PCIe EP driver > > > using the new EP uclass. > > > > Hi Bin and Ramon, > > > > Do you know how to test the EP device when use Ramon Fried EP > > framework patch, I don't know how to use it in u-boot, take our board > > as an example, we use the RCW to configure the PCIe controller work as > > EP or RC, never use the DTS, another issue, when our PCIe controller > > work in EP mode, we must set this controller is ready before RC scan > > the bus, our main purpose is that set the BAR size and make it ready > > in u-boot, ensure that the EP controller is ready when enter the kernel or > other RC can scan the bus which the EP link, I am not sure whether should > separate the EP and RC driver. Do you have any advice? > > > In this case, where you need to initialize the EP as fast as possible, you should > define the dts node and probably add ""u-boot, dm-pre-reloc". > The you need to forcefully probe the EP in one of the pre-relocation board > callbacks. > This can be done by something like: > rc = uclass_get_device_by_name(UCLASS_PCI_EP, "pcie_ep at 4800000", > &dev);:q Thanks a lot, could you tell me when call the uclass_get_device_by_name function? Actually, I am not very clear how to run the DM_TEST in test/dm/pci_ep.c maybe I need to learn more DM and UCLASS knowledge, if you can explain it, I will be very appreciate. > > root complex and endpoint are totally different drivers, I don't see how you > can combine them together. Thanks a lot form your comments, we combine the RC and EP driver in one file(drivers/pci/pcie_layerscape.c), and we run the different initialize code of EP and RC by reading PCI_HEADER_TYPE register. Like this: pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f; if (pcie->mode == PCI_HEADER_TYPE_NORMAL) { printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint"); ls_pcie_setup_ep(pcie); } else { printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex"); ls_pcie_setup_ctrl(pcie); } Another issue is that, there are many share function will used by RC and EP driver, so, if I separate the RC and EP driver, there will have many duplicate code. Like this: dbi_readl, dbi_writel, ctrl_readl, ctrl_writel and so on. > > Thanks, > Ramon. > > > > Thanks > > Xiaowei > > > > > > > > See > > > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpat > > > chw > > > > ork.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D104952&da > > > > ta=02%7C01%7Cxiaowei.bao%40nxp.com%7Ca1e3da7d57a54520bd3008d6d > > > > a6fbc4d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C63693657 > > > > 0769296107&sdata=5CnEujEtYGbeiBEyv4iY5dXAapdQ65wCh1vs0quSVT > > > Y%3D&reserved=0 > > > > > > Regards, > > > Bin