From mboxrd@z Thu Jan  1 00:00:00 1970
From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
Subject: Re: [dpdk-stable] [PATCH v2 2/4] hash: add local cache
 for TSX region
Date: Tue, 13 Nov 2018 17:16:36 +0000
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References: <20181105173913.61225-1-bruce.richardson@intel.com>
 <20181112104719.62568-3-bruce.richardson@intel.com>
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Cc: "stable@dpdk.org" <stable@dpdk.org>, "dev@dpdk.org" <dev@dpdk.org>, nd
 <nd@arm.com>, nd <nd@arm.com>
To: Thomas Monjalon <thomas@monjalon.net>, Bruce Richardson
 <bruce.richardson@intel.com>, Yipeng Wang <yipeng1.wang@intel.com>
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> > >
> > > From: Yipeng Wang <yipeng1.wang@intel.com>
> > >
> > > This patch adds back the local cache when TSX support is turned on.
> > >
> > > When TSX is turned on, free key-data slot ring would be contended by
> > > various TSX regions. The purpose of this commit is to reduce
> > > possible memory collisions during key insertion.
> > >
> > > Signed-off-by: Yipeng Wang <yipeng1.wang@intel.com>
> > > Acked-by: Bruce Richardson <bruce.richardson@intel.com>
> > > ---
> > >  lib/librte_hash/rte_cuckoo_hash.c | 4 +++-
> > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/lib/librte_hash/rte_cuckoo_hash.c
> > > b/lib/librte_hash/rte_cuckoo_hash.c
> > > index 76f5dc8..5d5f9f1 100644
> > > --- a/lib/librte_hash/rte_cuckoo_hash.c
> > > +++ b/lib/librte_hash/rte_cuckoo_hash.c
> > > @@ -180,8 +180,10 @@ struct rte_hash *
> > >  	}
> > >
> > >  	/* Check extra flags field to check extra options. */
> > > -	if (params->extra_flag &
> > > RTE_HASH_EXTRA_FLAGS_TRANS_MEM_SUPPORT)
> > > +	if (params->extra_flag &
> > > RTE_HASH_EXTRA_FLAGS_TRANS_MEM_SUPPORT) {
> > > +		use_local_cache =3D 1;
> > Do you see the issue even in the case of single writer? Enabling this f=
lag
> creates local caches on all the data plane cores. This increases the memo=
ry
> usage for the single writer use case. Then there is 'writers on the contr=
ol
> plane' use case, the requirement on hash_add rate is comparatively lower
> when compared to 'writers on the data plane'. The writers also are not pi=
nned
> to any core as well. In this use case, I am not sure how much having a lo=
cal
> cache matters.
> >
> > Enabling this flag effectively changes the free slot allocation from a =
ring to a
> stack data structure. Does it indicate that for single writer use case wi=
th TSX,
> the free slot (global) data structure should be a stack (rather than a ri=
ng)?
>=20
> Is it blocking this patchset from entering in 18.11?
> If I understand well, there are some fixes for 18.11.
>=20
I am fine with the other fixes in this patchset