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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Tim Harvey > Sent: Tuesday, November 16, 2021 6:56 AM > To: Hongxing Zhu > Cc: Lucas Stach ; Marcel Ziswiler > ; Kishon Vijay Abraham I > ; vkoul@kernel.org; Rob Herring ; > galak@kernel.crashing.org; Shawn Guo ; > linux-phy@lists.infradead.org; Device Tree Mailing List > ; Linux ARM Mailing List > ; open list > ; Sascha Hauer ; > dl-linux-imx > Subject: Re: [PATCH v5 0/8] Add the imx8m pcie phy driver and imx8mm > pcie support > > On Mon, Nov 1, 2021 at 7:58 PM Richard Zhu > wrote: > > > > Refer to the discussion [1] when try to enable i.MX8MM PCIe support, > > one standalone PCIe PHY driver should be seperated from i.MX PCIe > > driver when enable i.MX8MM PCIe support. > > > > This patch-set adds the standalone PCIe PHY driver suport[1-5], and > > i.MX8MM PCIe support[6-8] to have whole view to review this > patch-set. > > > > The PCIe works on i.MX8MM EVK board based the the blkctrl power > driver > > [2] and this patch-set. And tested by Tim and Marcel on the different > > reference clock modes boards. > > > > [1] > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpa > tc > > > hwork.ozlabs.org%2Fproject%2Flinux-pci%2Fpatch%2F20210510141509. > 929120 > > > -3-l.stach%40pengutronix.de%2F&data=04%7C01%7Chongxing.zhu > %40nxp.c > > > om%7C489971db9c0f4308600208d9a88b2b05%7C686ea1d3bc2b4c6fa9 > 2cd99c5c3016 > > > 35%7C0%7C0%7C637726137953234928%7CUnknown%7CTWFpbGZsb3d > 8eyJWIjoiMC4wLj > > > AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000& > amp;sdata= > > > ltuNZqIAsEH6%2B1KE4cqNOiUul3Ex%2BWmYcyqD%2BFJuUrs%3D& > reserved=0 > > [2] > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpa > tc > > > hwork.kernel.org%2Fproject%2Flinux-arm-kernel%2Fcover%2F20210910 > 202640 > > .980366-1-l.stach%40pengutronix.de%2F&data=04%7C01%7Chon > gxing.zhu% > > > 40nxp.com%7C489971db9c0f4308600208d9a88b2b05%7C686ea1d3bc2 > b4c6fa92cd99 > > > c5c301635%7C0%7C0%7C637726137953234928%7CUnknown%7CTWFp > bGZsb3d8eyJWIjo > > > iMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D% > 7C3000& > > ;sdata=MrT3Re3YttE9AoqmGHksTqt4jF4vitRPz5lkgpZqSZ4%3D&res > erved=0 > > > > Main changes v4 --> v5: > > - Set the AUX_EN always 1b'1, thus it can fix the regression introduced > in v4 > > series on Marcel's board. > > - Use the lower-case letter in the devicetreee refer to Marcel's > comments. > > - Since the default value of the deemphasis parameters are zero, only > set > > the deemphasis registers when the input paramters are none zero. > > > > Main changes v3 --> v4: > > - Update the yaml to fix syntax error, add maxitems and drop > > description of phy > > - Correct the clock name in PHY DT node. > > - Squash the EVK board relalted dts changes into one patch, and drop > the > > useless dummy clock and gpio suffix in DT nodes. > > - Add board specific de-emphasis parameters as DT properties. Thus > each board > > can specify its actual de-emphasis values. > > - Update the commit log of PHY driver. > > - Remove the useless codes from PCIe driver, since they are moved to > > PHY driver > > - After the discussion and verification of the CLKREQ# configurations > with Tim, > > agree to add an optional boolean property "fsl,clkreq-unsupported", > indicates > > the CLKREQ# signal is hooked or not in HW designs. > > - Add "Tested-by: Marcel Ziswiler " tag, > since > > Marcel help to test the v3 patch-set. > > > > Main changes v2 --> v3: > > - Regarding Lucas' comments. > > - to have a whole view to review the patches, send out the i.MX8MM > PCIe support too. > > - move the PHY related bits manipulations of the GPR/SRC to > standalone PHY driver. > > - split the dts changes to SOC and board DT, and use the enum instead > of raw value. > > - update the license of the dt-binding header file. > > > > Changes v1 --> v2: > > - Update the license of the dt-binding header file to make the license > > compatible with dts files. > > - Fix the dt_binding_check errors. > > > > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 > +++ > > Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 95 > ++++++++++++++++++++++++++++++++ > > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | > 55 +++++++++++++++++++ > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | > 46 +++++++++++++++- > > drivers/pci/controller/dwc/pci-imx6.c | > 73 ++++++++++++++++++++++--- > > drivers/phy/freescale/Kconfig | > 9 ++++ > > drivers/phy/freescale/Makefile | > 1 + > > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | > 237 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++ > > include/dt-bindings/phy/phy-imx8-pcie.h | > 14 +++++ > > 9 files changed, 528 insertions(+), 8 deletions(-) > > > > [PATCH v5 1/8] dt-bindings: phy: phy-imx8-pcie: Add binding for the > > [PATCH v5 2/8] dt-bindings: phy: Add imx8 pcie phy driver support > > [PATCH v5 3/8] dt-bindings: imx6q-pcie: Add PHY phandles and name > > [PATCH v5 4/8] arm64: dts: imx8mm: Add the pcie phy support [PATCH > v5 > > 5/8] phy: freescale: pcie: Initialize the imx8 pcie [PATCH v5 6/8] > > arm64: dts: imx8mm: Add the pcie support [PATCH v5 7/8] arm64: dts: > > imx8mm-evk: Add the pcie support on imx8mm [PATCH v5 8/8] PCI: > imx: > > Add the imx8mm pcie support > > Richard, > > Are you posting a v6 of this series or have we already missed the window > for 5.16? [Richard Zhu] Hi Tim: Thanks for your kindly reminder. In my original plan, I prefer to merge the codes refine firstly, then issue the v6 patch-set after the rebase. https://patchwork.kernel.org/project/linux-arm-kernel/cover/1635747478-25562-1-git-send-email-hongxing.zhu@nxp.com/ Unfortunately, I don't get ack from Lucas for other four patches. Anyway, I would post the v6 patch-set immediately after merge Rob's comments. Best Regards Richard Zhu > > Best regards, > > Tim -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0407DC433FE for ; Tue, 16 Nov 2021 01:42:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CA76661BC1 for ; Tue, 16 Nov 2021 01:42:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org CA76661BC1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Tim Harvey > Sent: Tuesday, November 16, 2021 6:56 AM > To: Hongxing Zhu > Cc: Lucas Stach ; Marcel Ziswiler > ; Kishon Vijay Abraham I > ; vkoul@kernel.org; Rob Herring ; > galak@kernel.crashing.org; Shawn Guo ; > linux-phy@lists.infradead.org; Device Tree Mailing List > ; Linux ARM Mailing List > ; open list > ; Sascha Hauer ; > dl-linux-imx > Subject: Re: [PATCH v5 0/8] Add the imx8m pcie phy driver and imx8mm > pcie support > > On Mon, Nov 1, 2021 at 7:58 PM Richard Zhu > wrote: > > > > Refer to the discussion [1] when try to enable i.MX8MM PCIe support, > > one standalone PCIe PHY driver should be seperated from i.MX PCIe > > driver when enable i.MX8MM PCIe support. > > > > This patch-set adds the standalone PCIe PHY driver suport[1-5], and > > i.MX8MM PCIe support[6-8] to have whole view to review this > patch-set. > > > > The PCIe works on i.MX8MM EVK board based the the blkctrl power > driver > > [2] and this patch-set. And tested by Tim and Marcel on the different > > reference clock modes boards. > > > > [1] > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpa > tc > > > hwork.ozlabs.org%2Fproject%2Flinux-pci%2Fpatch%2F20210510141509. > 929120 > > > -3-l.stach%40pengutronix.de%2F&data=04%7C01%7Chongxing.zhu > %40nxp.c > > > om%7C489971db9c0f4308600208d9a88b2b05%7C686ea1d3bc2b4c6fa9 > 2cd99c5c3016 > > > 35%7C0%7C0%7C637726137953234928%7CUnknown%7CTWFpbGZsb3d > 8eyJWIjoiMC4wLj > > > AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000& > amp;sdata= > > > ltuNZqIAsEH6%2B1KE4cqNOiUul3Ex%2BWmYcyqD%2BFJuUrs%3D& > reserved=0 > > [2] > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpa > tc > > > hwork.kernel.org%2Fproject%2Flinux-arm-kernel%2Fcover%2F20210910 > 202640 > > .980366-1-l.stach%40pengutronix.de%2F&data=04%7C01%7Chon > gxing.zhu% > > > 40nxp.com%7C489971db9c0f4308600208d9a88b2b05%7C686ea1d3bc2 > b4c6fa92cd99 > > > c5c301635%7C0%7C0%7C637726137953234928%7CUnknown%7CTWFp > bGZsb3d8eyJWIjo > > > iMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D% > 7C3000& > > ;sdata=MrT3Re3YttE9AoqmGHksTqt4jF4vitRPz5lkgpZqSZ4%3D&res > erved=0 > > > > Main changes v4 --> v5: > > - Set the AUX_EN always 1b'1, thus it can fix the regression introduced > in v4 > > series on Marcel's board. > > - Use the lower-case letter in the devicetreee refer to Marcel's > comments. > > - Since the default value of the deemphasis parameters are zero, only > set > > the deemphasis registers when the input paramters are none zero. > > > > Main changes v3 --> v4: > > - Update the yaml to fix syntax error, add maxitems and drop > > description of phy > > - Correct the clock name in PHY DT node. > > - Squash the EVK board relalted dts changes into one patch, and drop > the > > useless dummy clock and gpio suffix in DT nodes. > > - Add board specific de-emphasis parameters as DT properties. Thus > each board > > can specify its actual de-emphasis values. > > - Update the commit log of PHY driver. > > - Remove the useless codes from PCIe driver, since they are moved to > > PHY driver > > - After the discussion and verification of the CLKREQ# configurations > with Tim, > > agree to add an optional boolean property "fsl,clkreq-unsupported", > indicates > > the CLKREQ# signal is hooked or not in HW designs. > > - Add "Tested-by: Marcel Ziswiler " tag, > since > > Marcel help to test the v3 patch-set. > > > > Main changes v2 --> v3: > > - Regarding Lucas' comments. > > - to have a whole view to review the patches, send out the i.MX8MM > PCIe support too. > > - move the PHY related bits manipulations of the GPR/SRC to > standalone PHY driver. > > - split the dts changes to SOC and board DT, and use the enum instead > of raw value. > > - update the license of the dt-binding header file. > > > > Changes v1 --> v2: > > - Update the license of the dt-binding header file to make the license > > compatible with dts files. > > - Fix the dt_binding_check errors. > > > > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 > +++ > > Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 95 > ++++++++++++++++++++++++++++++++ > > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | > 55 +++++++++++++++++++ > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | > 46 +++++++++++++++- > > drivers/pci/controller/dwc/pci-imx6.c | > 73 ++++++++++++++++++++++--- > > drivers/phy/freescale/Kconfig | > 9 ++++ > > drivers/phy/freescale/Makefile | > 1 + > > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | > 237 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++ > > include/dt-bindings/phy/phy-imx8-pcie.h | > 14 +++++ > > 9 files changed, 528 insertions(+), 8 deletions(-) > > > > [PATCH v5 1/8] dt-bindings: phy: phy-imx8-pcie: Add binding for the > > [PATCH v5 2/8] dt-bindings: phy: Add imx8 pcie phy driver support > > [PATCH v5 3/8] dt-bindings: imx6q-pcie: Add PHY phandles and name > > [PATCH v5 4/8] arm64: dts: imx8mm: Add the pcie phy support [PATCH > v5 > > 5/8] phy: freescale: pcie: Initialize the imx8 pcie [PATCH v5 6/8] > > arm64: dts: imx8mm: Add the pcie support [PATCH v5 7/8] arm64: dts: > > imx8mm-evk: Add the pcie support on imx8mm [PATCH v5 8/8] PCI: > imx: > > Add the imx8mm pcie support > > Richard, > > Are you posting a v6 of this series or have we already missed the window > for 5.16? [Richard Zhu] Hi Tim: Thanks for your kindly reminder. In my original plan, I prefer to merge the codes refine firstly, then issue the v6 patch-set after the rebase. https://patchwork.kernel.org/project/linux-arm-kernel/cover/1635747478-25562-1-git-send-email-hongxing.zhu@nxp.com/ Unfortunately, I don't get ack from Lucas for other four patches. Anyway, I would post the v6 patch-set immediately after merge Rob's comments. Best Regards Richard Zhu > > Best regards, > > Tim _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 030D4C43219 for ; Tue, 16 Nov 2021 01:52:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DE8FD61A7C for ; Tue, 16 Nov 2021 01:52:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382973AbhKPByi (ORCPT ); Mon, 15 Nov 2021 20:54:38 -0500 Received: from mail-vi1eur05on2071.outbound.protection.outlook.com ([40.107.21.71]:43713 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1356481AbhKPBnZ (ORCPT ); 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS8PR04MB8676.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: b335d7f6-cd1b-41a9-f5de-08d9a8a21064 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Nov 2021 01:40:26.0924 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: o4CAvLsOdcYLzVOzOuEtiAtv9Q8a+ANSm+b/JLcKjMkFFE3F857P2TsvaWM5SiCZCoXHOn8j69achlh3mzOgTA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS1PR04MB9432 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Tim Harvey > Sent: Tuesday, November 16, 2021 6:56 AM > To: Hongxing Zhu > Cc: Lucas Stach ; Marcel Ziswiler > ; Kishon Vijay Abraham I > ; vkoul@kernel.org; Rob Herring ; > galak@kernel.crashing.org; Shawn Guo ; > linux-phy@lists.infradead.org; Device Tree Mailing List > ; Linux ARM Mailing List > ; open list > ; Sascha Hauer ; > dl-linux-imx > Subject: Re: [PATCH v5 0/8] Add the imx8m pcie phy driver and imx8mm > pcie support >=20 > On Mon, Nov 1, 2021 at 7:58 PM Richard Zhu > wrote: > > > > Refer to the discussion [1] when try to enable i.MX8MM PCIe support, > > one standalone PCIe PHY driver should be seperated from i.MX PCIe > > driver when enable i.MX8MM PCIe support. > > > > This patch-set adds the standalone PCIe PHY driver suport[1-5], and > > i.MX8MM PCIe support[6-8] to have whole view to review this > patch-set. > > > > The PCIe works on i.MX8MM EVK board based the the blkctrl power > driver > > [2] and this patch-set. And tested by Tim and Marcel on the different > > reference clock modes boards. > > > > [1] > > > https://eur01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fpa > tc > > > hwork.ozlabs.org%2Fproject%2Flinux-pci%2Fpatch%2F20210510141509. > 929120 > > > -3-l.stach%40pengutronix.de%2F&data=3D04%7C01%7Chongxing.zhu > %40nxp.c > > > om%7C489971db9c0f4308600208d9a88b2b05%7C686ea1d3bc2b4c6fa9 > 2cd99c5c3016 > > > 35%7C0%7C0%7C637726137953234928%7CUnknown%7CTWFpbGZsb3d > 8eyJWIjoiMC4wLj > > > AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000& > amp;sdata=3D > > > ltuNZqIAsEH6%2B1KE4cqNOiUul3Ex%2BWmYcyqD%2BFJuUrs%3D& > reserved=3D0 > > [2] > > > https://eur01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fpa > tc > > > hwork.kernel.org%2Fproject%2Flinux-arm-kernel%2Fcover%2F20210910 > 202640 > > .980366-1-l.stach%40pengutronix.de%2F&data=3D04%7C01%7Chon > gxing.zhu% > > > 40nxp.com%7C489971db9c0f4308600208d9a88b2b05%7C686ea1d3bc2 > b4c6fa92cd99 > > > c5c301635%7C0%7C0%7C637726137953234928%7CUnknown%7CTWFp > bGZsb3d8eyJWIjo > > > iMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D% > 7C3000& > > ;sdata=3DMrT3Re3YttE9AoqmGHksTqt4jF4vitRPz5lkgpZqSZ4%3D&res > erved=3D0 > > > > Main changes v4 --> v5: > > - Set the AUX_EN always 1b'1, thus it can fix the regression introduced > in v4 > > series on Marcel's board. > > - Use the lower-case letter in the devicetreee refer to Marcel's > comments. > > - Since the default value of the deemphasis parameters are zero, only > set > > the deemphasis registers when the input paramters are none zero. > > > > Main changes v3 --> v4: > > - Update the yaml to fix syntax error, add maxitems and drop > > description of phy > > - Correct the clock name in PHY DT node. > > - Squash the EVK board relalted dts changes into one patch, and drop > the > > useless dummy clock and gpio suffix in DT nodes. > > - Add board specific de-emphasis parameters as DT properties. Thus > each board > > can specify its actual de-emphasis values. > > - Update the commit log of PHY driver. > > - Remove the useless codes from PCIe driver, since they are moved to > > PHY driver > > - After the discussion and verification of the CLKREQ# configurations > with Tim, > > agree to add an optional boolean property "fsl,clkreq-unsupported", > indicates > > the CLKREQ# signal is hooked or not in HW designs. > > - Add "Tested-by: Marcel Ziswiler " tag, > since > > Marcel help to test the v3 patch-set. > > > > Main changes v2 --> v3: > > - Regarding Lucas' comments. > > - to have a whole view to review the patches, send out the i.MX8MM > PCIe support too. > > - move the PHY related bits manipulations of the GPR/SRC to > standalone PHY driver. > > - split the dts changes to SOC and board DT, and use the enum instead > of raw value. > > - update the license of the dt-binding header file. > > > > Changes v1 --> v2: > > - Update the license of the dt-binding header file to make the license > > compatible with dts files. > > - Fix the dt_binding_check errors. > > > > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 > +++ > > Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 95 > ++++++++++++++++++++++++++++++++ > > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | > 55 +++++++++++++++++++ > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | > 46 +++++++++++++++- > > drivers/pci/controller/dwc/pci-imx6.c | > 73 ++++++++++++++++++++++--- > > drivers/phy/freescale/Kconfig | > 9 ++++ > > drivers/phy/freescale/Makefile | > 1 + > > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | > 237 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++ > > include/dt-bindings/phy/phy-imx8-pcie.h | > 14 +++++ > > 9 files changed, 528 insertions(+), 8 deletions(-) > > > > [PATCH v5 1/8] dt-bindings: phy: phy-imx8-pcie: Add binding for the > > [PATCH v5 2/8] dt-bindings: phy: Add imx8 pcie phy driver support > > [PATCH v5 3/8] dt-bindings: imx6q-pcie: Add PHY phandles and name > > [PATCH v5 4/8] arm64: dts: imx8mm: Add the pcie phy support [PATCH > v5 > > 5/8] phy: freescale: pcie: Initialize the imx8 pcie [PATCH v5 6/8] > > arm64: dts: imx8mm: Add the pcie support [PATCH v5 7/8] arm64: dts: > > imx8mm-evk: Add the pcie support on imx8mm [PATCH v5 8/8] PCI: > imx: > > Add the imx8mm pcie support >=20 > Richard, >=20 > Are you posting a v6 of this series or have we already missed the window > for 5.16? [Richard Zhu] Hi Tim: Thanks for your kindly reminder. In my original plan, I prefer to merge the codes refine firstly, then issue the v6 patch-set after the rebase. https://patchwork.kernel.org/project/linux-arm-kernel/cover/1635747478-2556= 2-1-git-send-email-hongxing.zhu@nxp.com/ Unfortunately, I don't get ack from Lucas for other four patches. Anyway, I would post the v6 patch-set immediately after merge Rob's comment= s. Best Regards Richard Zhu >=20 > Best regards, >=20 > Tim